IRF5 Data Sheet January 22 5.6A, V,.5 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA7. Ordering Information PART NUMBER PACKAGE BRAND IRF5 TO-22AB IRF5 NOTE: When ordering, include the entire part number. Features 5.6A, V r DS(ON) =.5Ω Single Pulse Avalanche Energy Rated SOA is Power Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Related Literature - TB33 Guidelines for Soldering Surface Mount Components to PC Boards Symbol G D S Packaging JEDEC TO-22AB SOURCE DRAIN GATE DRAIN (FLANGE) 22 Fairchild Semiconductor Corporation IRF5 Rev. B
Absolute Maximum Ratings T C = 25 o C, Unless Otherwise Specified IRF5 UNITS Drain to Source Voltage (Note )....................................................... V Drain to Gate Voltage (R GS = 2kΩ) (Note )........................................... V DGR V Continuous Drain Current............................................................. I D 5.6 A T C = o C...................................................................... I D A Pulsed Drain Current (Note 3)......................................................... I DM 2 A Gate to Source Voltage............................................................. V GS ±2 V Maximum Power Dissipation...........................................................P D 3 W Linear Derating Factor...................................................................29 W/ o C Single Pulse Avalanche Energy Rating (Note )...........................................E AS 9 mj Operating and Storage Temperature Range..........................................T J, T STG -55 to 75 o C Maximum Temperature for Soldering Leads at.63in (.6mm) from Case for s............................................. T L 3 Package Body for s, See Techbrief 33............................................. T pkg 26 o C o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. T J = 25 o C to 5 o C. IRF5 Electrical Specifications T C = 25 o C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BS V GS = V, I D = 25µA, (Figure ) - - V Gate to Threshold Voltage V GS(TH) V GS =, I D = 25µA 2. -. V Zero-Gate Voltage Drain Current I DSS = 95V, V GS = V - - 25 µa =.8 x Rated BS, V GS = V, T J = 5 o C - - 25 µa On-State Drain Current (Note 2) I D(ON) > I D(ON) x r DS(ON)MAX, V GS = V (Figure 7) 5.6 - - A Gate to Source Leakage Current I GSS V GS = ±2V - - ± na Drain to Source On Resistance (Note 2) r DS(ON) V GS = V, I D = 3.A (Figures 8, 9) -..5 Ω Forward Transconductance (Note 2) g fs V GS = 5V, I D = 3.A (Figure 2).3 2. - S Turn-On Delay Time t d(on) I D 5.6A, R GS = 2Ω, V DD = 5V, R L = 9Ω, - 8 2 ns Rise Time t V DD = 5V, V GS = V r - 25 63 ns MOSFET switching times are essentially independent Turn-Off Delay Time t d(off) of operating temperature - 5 7 ns Fall Time t f - 2 59 ns Total Gate Charge (Gate to Source + Gate to Drain) Q g(tot) V GS = V, I D = 5.6A, =.8 x Rated BS, I G(REF) =.5mA (Figure ) Gate charge is essentially independent of operating temperature. - 5. 3 nc Gate to Source Charge Q gs - 2. - nc Gate to Drain Miller Charge Q gd - 3. - nc Input Capacitance C ISS V GS = V, = 25V, f =.MHz (Figure ) - 35 - pf Output Capacitance C OSS - 8 - pf Reverse-Transfer Capacitance C RSS - 2 - pf Internal Drain Inductance L D Measured From the Contact Screw On Tab To Center of Die Measured From the Drain Lead, 6mm (.25in) From Package to Center of Die Internal Source Inductance L S Measured From The Source Lead, 6mm (.25in) From Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D - 3.5 - nh -.5 - nh - 7.5 - nh Junction to Case R θjc - - 3.5 o C/W Junction to Ambient R θja Free air operation - - 8 o C/W G L D L S S 22 Fairchild Semiconductor Corporation IRF5 Rev. B
IRF5 Source to Drain Diode Specifications PARAMETER SYMBOL Test Conditions MIN TYP MAX UNITS Continuous Source to Drain Current I SD Modified MOSFET D - - 5.6 A Symbol Showing the Pulse Source to Drain Current I SDM Integral Reverse - - 2 A (Note 3) P-N Junction Diode G S Source to Drain Diode Voltage (Note 2) V SD T J = 25 o C, I SD = 5.6A, V GS = V (Figure 3) - - 2.5 V Reverse Recovery Time t rr T J = 25 o C, I SD = 5.6A, di SD /d t = A/µs.6 96 2 ns Reverse Recovered Charge Q RR T J = 25 o C, I SD = 5.6A, di SD /d t = A/µs.7..83 µc NOTES: 2. Pulse test: pulse width 3µs, duty cycle 2%. 3. Repetitive rating: pulse width limited by max junction temperature. See Transient Thermal Impedance curve (Figure 3).. V DD = 25V, start T J = 25 o C, L = 9µH, R G = 25Ω, peak I AS = 5.6A. Typical Performance Curves Unless Otherwise Specified.2 POWER DISSIPATION MULTIPLIER..8.6..2 I D, DRAIN CURRENT (A) 8 6 2 25 5 75 25 5 75 T C, CASE TEMPERATURE ( o C) 25 5 75 25 5 75 T C, CASE TEMPERATURE ( o C) FIGURE. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE Z θjc, TRANSIENT THERMAL IMPEDANCE ( o C/W).5.2..5..2. t SINGLE PULSE t 2 NOTES: DUTY FACTOR: D = t /t 2 PEAK T J = P DM x Z θjc + T C. -5 - -3-2. t, RECTANGULAR PULSE DURATION (S) P DM FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 22 Fairchild Semiconductor Corporation IRF5 Rev. B
IRF5 Typical Performance Curves Unless Otherwise Specified (Continued) I D, DRAIN CURRENT (A) OPERATION IN THIS REGION IS LIMITED BY r DS(ON) T C = 25 o C T J = 75 o C SINGLE PULSE. 2 µs µs ms, DRAIN TO SOURCE VOLTAGE (V) FIGURE. FORWARD BIAS SAFE OPERATING AREA 3 I D, DRAIN CURRENT (A) V GS = V PULSE DURATION = 8µs 8 DUTY CYCLE =.5% MAX V GS = 8V 6 V GS = 7V V GS = 6V 2 V GS = 5V V GS = V 2 3 5, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. OUTPUT CHARACTERISTICS I D, DRAIN CURRENT (A) 8 6 2 PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V GS = V V GS = 8V V GS = 7V V GS = 6V V GS = 5V V GS = V 2 6 8, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS I D(ON), ON-STATE DRAIN CURRENT (A) 5V PULSE DURATION = 8µs DUTY CYCLE =.5% MAX T J = 75 o T C J = 25 o C. -2 2 6 8 V GS, GATE TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS r DS(ON), DRAIN TO SOURCE ON RESISTANCE (Ω) 5 3 2 PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V GS = V V GS = 2V NORMALIZED ON RESISTANCE 3. 2..8.2.6 I D = 3.A, V GS = V PULSE DURATION = 8µs DUTY CYCLE =.5% MAX 8 2 6 2 I D, DRAIN CURRENT (A) -6 - -2 2 6 8 2 6 8 T J, JUNCTION TEMPERATURE ( o C) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 22 Fairchild Semiconductor Corporation IRF5 Rev. B
IRF5 Typical Performance Curves Unless Otherwise Specified (Continued) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE.25 I D = 25µA.5.5.95.85.75-6 - -2 2 6 8 2 6 8 T J, JUNCTION TEMPERATURE ( o C) C, CAPACITANCE (pf) 5 V GS = V, f = MHz C ISS = C GS + C GD C RSS = C GD C OSS C DS + C GD 3 2 C ISS C OSS C RSS 2 5 2 5 2, DRAIN TO SOURCE VOLTAGE (V) FIGURE. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE g fs, TRANSCONDUCTANCE (S) 2.5 2..5..5 PULSE DURATION = 8µs DUTY CYCLE =.5% MAX 5V T J = 25 o C T J = 75 o C 2 6 8 I D, DRAIN CURRENT (A) I SD, SOURCE TO DRAIN CURRENT (A) PULSE DURATION = 8µs DUTY CYCLE =.5% MAX T J = 75 o C T J = 25 o C...8.2.6 2. V SD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 2. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 3. SOURCE TO DRAIN DIODE VOLTAGE V GS, GATE TO SOURCE VOLTAGE (V) 2 6 2 8 I D = 3.A = 8V = 5V = 2V 2 6 8 Q g, GATE CHARGE (nc) FIGURE. GATE TO SOURCE VOLTAGE vs GATE CHARGE 22 Fairchild Semiconductor Corporation IRF5 Rev. B
IRF5 Test Circuits and Waveforms BS L t P VARY t P TO OBTAIN REQUIRED PEAK I AS V GS R G + V DD - I AS V DD DUT V t P I AS.Ω t AV FIGURE 5. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 6. UNCLAMPED ENERGY WAVEFORMS t ON t d(on) t OFF t d(off) R L t r t f 9% 9% + R G V DD - % % DUT 9% V GS V GS % 5% PULSE WIDTH 5% FIGURE 7. SWITCHING TIME TEST CIRCUIT FIGURE 8. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR (ISOLATED SUPPLY) V DD 2V BATTERY.2µF 5kΩ.3µF SAME TYPE AS DUT Q gs Q gd Q g(tot) V GS D G DUT I G(REF) I G CURRENT SAMPLING RESISTOR S I D CURRENT SAMPLING RESISTOR I G(REF) FIGURE 9. GATE CHARGE TEST CIRCUIT FIGURE 2. GATE CHARGE WAVEFORM 22 Fairchild Semiconductor Corporation IRF5 Rev. B
TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Bottomless CoolFET CROSSVOLT DenseTrench DOME EcoSPARK E 2 CMOS TM EnSigna TM FACT FACT Quiet Series STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms FAST FASTr FRFET GlobalOptoisolator GTO HiSeC ISOPLANAR LittleFET MicroFET MicroPak MICROWIRE OPTOLOGIC OPTOPLANAR PACMAN POP Power27 PowerTrench QFET QS QT Optoelectronics Quiet Series SILENT SWITCHER SMART START STAR*POWER Stealth SuperSOT -3 SuperSOT -6 SuperSOT -8 SyncFET TinyLogic TruTranslation UHC UltraFET 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Datasheet Identification Product Status Definition VCX Advance Information Preliminary No Identification Needed Formative or In Design First Production Full Production This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H
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