Digital Logic Elements, Clock, and Memory Elements

Physics 333 Experiment #9 Fall 999 Digital Logic Elements, Clock, and Memory Elements Purpose This experiment introduces the fundamental circuit elements of digital electronics. These include a basic set of three LOGIC GTES which suffice to build anything digital; the 555 TIMER as a source of logic signals, and two types of memory element. oolean lgebra, the mathematics of two-valued variables, will be used to design digital circuits. Introduction Most physical quantities can assume any value within some continuous range; this value varies with time in a dynamic process. The output voltage of a transducer that observes it will change with time in an analogous way. Such continuous signals, V = V(t), are called analog signals, and circuits which preserve the information in this form, such as linear amplifiers and sine-wave oscillators, are collectively known as nalog Electronics. In contrast to this, the voltages in digital circuits have only two states: HIGH and LOW. Information is conveyed by the pattern of HI and LO voltages. These may occur at the same time in a set of parallel wires (parallel or combinational logic); or as a time sequence of HIGH s and LOW s moving along a single wire (sequential logic). nalog information can be translated into digital form by an nalog-to-digital Converter (DC). set of N on/off values or ITS has 2N possible different values. If you try to represent a voltage, V, by a 7 bit sequence, your uncertainty will be about %, since there are 2 7 = 28 possible combinations of digital values. higher accuracy needs more digits or bits. Readings. D & H,.-.5, 2.-2.5. 2. (Optional) (a) Horowitz and Hill Chapter 8. (b) rophy: Chapter 9 Digital Electronics. Pages 272-29: Digital logic, oolean lgebra, and Logic circuits. (c) TTL Cookbook, Don Lancaster, SMS (974). Experiment #9 9. Fall 999

Outline. Set up and test the -element LEDs as logic state indicators. 2. Verify the truth tables for the NND, NOR, and INVERT gates. Carry out the INVERT operation by making suitable connections first to a NND gate, then to a NOR gate. Thus you can dispense with the INVERT gates if only a few are needed. 3. Verify the truth table for an EXCLUSIVE OR (XOR) gate. Design, build, and test your own XOR circuit using only NND and NOR chips. 4. Design, build, and test a TTL Digital Clock using a 555 timer chip. Convert the clock to an electronic stop-watch. Use a NND gate to control the flow of pulses and the counter/timer to totalize the number of them in your measured interval. 5. Construct a RESET- SET (RS) memory element using two NOR gates. Derive the truth table by reasoning, then verify it with the LEDs. Demonstrate a complete memory cycle: Set, Store, Reset, Store, Set. Examine the effect of the illegal (S=, R=) for both possible previous states. 6. Construct an empirical truth table for the JK flip-flop directly from your observations with LEDs. Does it agree with the oolean expression for the output in Figure 9.5? With the oscilloscope, look at the toggling action of the flip-flop for clock pulses from your TIMER when J=K=. Theory - Electronic Logic and oolean lgebra Logic states The voltage in a digital circuit is allowed to be in only one of two states: HIGH and LOW. We usually abbreviate these as HI and LO. HI is taken to mean logical () or logical TRUE. LO is taken to mean logical () or logical FLSE. In the TTL logic family (see Fig. 9. on following page): ny voltage in the range 2.8 to 5. V is HI. ny voltage in the to.8 V is LO. ny voltage outside this range is undefined, and therefore illegal, except briefly during transitions. We will refer to HI as the 5 volt level, and LO as the volt level. Experiment #9 9.2 Fall 999

Logic operations and logic gates. The flow of digital signals is controlled by transistors which function as switches with just two states: OPEN and CLOSED. The state of a switch is controlled by a digital signal. The switch remains closed so long as a logical () signal is applied. logical () control signal keeps it open. Logic signals interact by means of GTES. The three fundamental gates ND, OR, and NOT, are named after the three fundamental operations of logic that they carry out. The ND and OR gates each have two inputs and one output. The output state is determined by the states of the two inputs. The function of each gate is defined by a TRUTH TLE, which specifies the output state for each possible combination of input states. The physical basis for the truth tables can be understood in terms of two switches. If the switches are in series, you get the ND function. Parallel switches perform the OR operation. The most common gates are shown in the lower table in Fig. 9.. bubble after a gate indicates NOT (the function evaluated). Thus, NND means NOT (ND). The EXCLUSIVE-OR (XOR) contains several basic gates that you will assemble in part 4 of the experiment to make a functional XOR circuit. The basic gates that we will use throughout the logic experiments are two-input NND and NOR, and INVERT. the NND and NOR are especially useful when DeMorgan s theorems are employed to simplify complex circuits (see discussion below). When several gates are combined to perform a complex logical operation, elegance and economy persuade one to use as few as possible. oolean lgebra, the mathematics of two valued variables, is the theoretical tool used to accomplish this circuit simplification. Experiment #9 9.3 Fall 999

Figure 9.. asic logic operations and gates. Volts 5. HIGH typical 3.5 V 2.8.8 LOW TTL logic levels Transition from LOW to HIGH typical.4 V Time Logical States Logical = YES = TRUE = Switch closed = +5 V (TTL Logic) Logical = NO = FLSE = Switch opened = V (TTL) asic Logic Operation Operation Switches Condition that circuit is closed ND ( ND are Series closed) OR NOT Same as invert Parallel Different switch oolean Notation or ( OR is closed) + means open means closed NOT Symbol. + Truth Table. + Other Gates NND NOR XOR. + + =+ Experiment #9 9.4 Fall 999

oolean lgebra Fundamental laws We imagine a logical variable,, that takes on the values or. If = then = and if = then = Equality OR ND NOT + = = + = + = = = + = = = + = = Two oolean expressions are equal if and only if their truth tables are identical. ssociative Laws ( + ) + C = + + C ( )C = ( C) Distributive Laws ( ) ( + C) = + C Related identities: ( + ) = ( + ) = + ( + ) ( + C) = ( + C) DeMorgan s Theorems K = + +K + +K = K Example of Method of Proof: Here s an example of proving theorems by direct comparison of truth tables. We take on DeMorgan s first theorem for two variables, = + : + Experiment #9 9.5 Fall 999

The last columns of the truth tables are identical. Thus, the first theorem is proven for two variables. Examples of simplification: oolean algebra can be used to simplify logical expressions and reduce the number of gates required in a circuit. Here we show two ways to implement the expression, Y = + C: ) DIRECT IMPLEMENTTION using NOT, NOR, and NND C C ) SIMPLIFIED CIRCUIT Y = +C = +C (by identity #2) C = +C (by property of NOT) = (C) (by De Morgan's Law) Fig. 9.2. oolean simplification C C C +C Y = +C Y = +C Expressions with many input variables. In the next experiments, you will form logic expressions with up to six input variables using logic gates with two inputs each. Here are some examples that illustrate the use of the double complement i.e., =, with DeMorgan s Theorems for reducing expressions to form that can be implemented only with NND and NOR, thus reducing the types of gates needed. = = + CD =. CD = + CD C {D Y = CD + = + =. + + C + D = (+) + (C+D) Y { = (+). C (C+D) D Fig. 9.3. Reduction to NND and NOR via DeMorgan s Theorem. = ++C+D The above circuits are examples of combinatorial logic. The output appears almost immediately upon application of the inputs. The logic value of the output depends only upon the present-time combination of a number of parallel inputs and the arrangement of gates. The binary-decimal decoder in Experiment # is an example of combinatorial logic. Memory Elements and Flip Flops In Sequential Logic circuits the output depends upon previous values of the input signals as well as their present-time values. Such circuits necessarily include memory elements that store the Experiment #9 9.6 Fall 999

logic values of the earlier signals. The fundamental circuit is the RS memory element. The JK flip-flop possesses external controls over the input to an RS memory that lies at its core. RS (Reset-Set Memory) Element RS MEMORY R S Signals SET RESET time R S Circuit = R + P P = S + R S Symbol Truth Table S R P= Stays the same P = Disallowed Fig. 9.4. RS memory element. The truth table shows how the circuit remembers. Suppose that it is originally in a state with = and R=S=. positive pulse, S, at the input sets it into the state =, where it remains after S returns to zero. later pulse, R, on the other input resets the circuit to =, where it remains until the next S pulse. JK Flip Flops. (747) There are three kinds of input to the JK flip flop: data inputs J and K the clock input C the direct input CLR ( = clear) There are two outputs, and its complement. JK Flip Flop (747) C n n+ time Clock Input Data inputs Fig. 9.5. JK flip-flop description. J C K CLR Direct Input Outputs CLR C J K n+ n+ n n Stays the same ( = J) ( = J) n n Toggle mode anything lways oolean Expression: n+ = (CLR)(J n K n +J n K n n +J n K n n ) In the absence of a clock pulse, the output remains unchanged at the previously acquired value, n, which is independent of the present-time data inputs J and K. Only on arrival of a clock pulse, C, can the output change to a new value, n +. The value of n + depends on the J and K inputs just before the clock pulse in the way specified in the truth table. The change occurs at the Experiment #9 9.7 Fall 999

downward going trailing edge of the clock pulse, as indicated by the downward arrow in the truth table. The direct input, CLR, overrides the clock and data inputs. During normal operation, CLR =. t the moment CLR goes to zero, the output goes to zero and remains there so long as CLR =. ll these options are contained in the oolean expression in the figure. 555 Timer and digital clock DC supply 8 Control Voltage 5 Threshold 6 Trigger 2 Reset 4 Discharge 7 (a) lock diagram of "555" V+ 5 kω 5 kω 5 kω Upper Comparitor - + - + Lower Comp. Discharge switch R S Clear Output mplifier 3 Output 2 3 4 (b) Pin layout GND TRIG OUT RST 555 + DIS THR YP 8 7 6 5 Ground Figure 9.6 555 Timer chip Experiment #9 9.8 Fall 999

(a) stable circuit (Digital Clock) +5V GND 2 TRIG Output 3 OUT 4 RST 555 + DIS THR YP 8 7 6 5.uf R R VC C V (b) Component values Output High (charge time): T2 = (R+R)C ln2 Output Low (discharge): T = RC ln2 Period: T = T + T2 (c) Limiting Values Max R, R 3.3 MΩ Min R, R kω Min. C 5pf (d) Voltage outputs DC Volts V+.667 V+.333 V+ Pin 6 - Capacitor Voltage Vc Supply Voltage (5V) Threshold Level Trigger Level time t2 t DC Volts Pin 3 Output Voltage V+ C charges through R and R in series C discharges through R only Output is positive while C is charging Output is grounded while C is discharging time Figure 9.7 stable circuit using 555 Timer chip Problems. Enter in your lab book the circuit diagrams and truth tables of all the circuits you will test. 2. Prove DeMorgan s second theorem by comparing the truth table for both sides of the equation: + = Use the laws of oolean algebra (see discussion on following pages) to derive the following: Experiment #9 9.9 Fall 999

+ = ( ) = + + = + 3. Design a circuit to perform the EXCLUSIVE OR function. Try to simplify the circuit so that you use the smallest possible number of NND and NOR gates. Show your oolean calculation. Check the result using truth tables. 4. Derive the truth table for a RS memory element made from two NOR gates. (See Fig. 9.4). Show the details of your derivation. 5. Design a KHz clock based on the type 555 TIMER chip. Make the low level pulses /4 period in length. rrange that the clock can also be made to run at Hz (for visual observation of LEDs) by substituting a larger capacitor. Predict the output for the NND gate in Fig. 9. for V = or 5 V (see Figs. 9.6 and 9.) 6. JK flip-flop with J=K= and CLR= is driven at the clock input by KHz pulses from the NND gate following the TIMER. Diagram the waveforms for the clock and the output on the same time scale. (See Fig. 9.5 and 9.). Experimental Details 74 Series TTL Chips Logic Levels. For the TTL family, logical is V and logical is 5 V, ideally. In practice, LOW is roughly.4 V and HIGH is 3.5 V. DIP Packages. DIP means dual-in-line arrangement of pins. This is the type of chip package that plugs into your circuit board. DUL chip means that there are two elements of the same kind in one package, UD means four and HEX means six. Straighten the pins gently before you plug into the board. Lever out with a screwdriver. Power supply. Check your power supply before connecting to the circuit board: Normal supply voltage: bsolute maximum: +5. V +5.5 V Current: Types 74, 742, 744: 2m per chip. Type 7486: 3m per chip. Output. The output from each individual gate can drive up to ten other TTL inputs. This is called the fan-out number. The output is delayed nsec after the input for the INV, NND, and NOR gates. The delay is 8 nsec for the EXCLUSIVE OR, and 25 nsec for the JK flip-flop. Experiment #9 9. Fall 999

Pin Layouts. Each chip has a dot or notch to indicate the ends at which pins and 4 are located. The pin numbers increase sequentially as you go counter-clockwise around the chip in a top view. In 4 pin chips, Pin 7 is always grounded ( V) and Pin 4 is always connected to the +5 V supply. Fig. 9.8. Pin arrangements for TTL chips. Suggestions Power Supply. Set the voltage to 5 V EFORE connecting to the circuit board. previous user may have left it on 5 V. The logic chips burn out around 6 V. If the voltage drops when you connect to the circuit, DO NOT TRY TO INCRESE V. Increase the current limit instead. Decoupling of Voltage Spikes: Fast voltage spikes originating from electrical machinery in the building, or from other chips on the board, can be transmitted through the power lines to your circuit board and/or other chips, and cause unwanted triggering of the flip flops. s a precaution, always mount a capacitor of at least. µf between the +5V line and ground on your circuit board at each chip. Data Records in the Logic Labs: For the experiments in the logic labs, write in your lab book the circuit, the oolean equation that expresses its function, and the predicted truth table beforehand. Enter the observed logical values of the outputs in an adjacent, but separate column. It is important to have the observed result along-side the predicted ones. Particular discrepancies can suggest where to look for the wiring errors or damaged gates. Logical inputs and observation of logical outputs with LEDs: Input logical values can be set by connecting wires from the gate inputs to either V (logical ) or 5 V (logical ). The logic level of the output can be observed using a light emitting diode (LED) which is connected Experiment #9 9. Fall 999

from the output to ground. The LED lights up when the output is +5 V and is off when the output on V. The cathode of the LED is grounded, and must always have a 47 Ω to 68 Ω resistor in series to limit the current and prevent burnout. bank of ten LEDs in a DIP package (type MV5764) is available. We suggest that you keep one bank of LEDs on your board throughout the logic experiments. The pin diagram is given below. LED Test Circuit Y= + LED ON OFF OFF OFF Fig. 9.9. LED test circuit. Y MV5764 Outputs from gates connect on this side. V is OFF, 5V is ON 9 8 7 6 5 4 3 2 External resistors 47 to 68 ohms. The Experiment LED testing efore doing anything else, check that each LED lights up when the positive end is connected to the 5 V supply. If it fails to light, check the polarity. The truth tables in most parts of the experiment will be verified in this way. Truth tables for the TTL gates Verify the truth tables for the NND (74), NOR (742), and INVERT (744) gates, using the LED indicators. Connect a NND gate so that it performs the INVERT function. Do this for a NOR gate also. This trick will be convenient in effecting economies in complex circuits. Occasionally you will find a non-functioning gate. Label the chip immediately. Throw the complete chip into the trash if an instructor confirms your diagnosis. Remember however, that most problems arise from wiring mistakes. The EXCLUSIVE OR circuit Verify the truth tables for an EXCLUSIVE OR chip (7486). Now build and test the XOR circuit of your own design using only the NNDs and NORs. Experiment #9 9.2 Fall 999

The RS memory uild the RS memory from two NOR gates. Compare the observed truth table with your predicted table, using LED indicators. Demonstrate the memory property by going through a complete memory cycle: Set (R =, S = ), Store (, ), Reset (, ), Store (, ), Set (, ). Examine the effect of the illegal input (R =, S = ), for different initial states of the RS system. The TTL digital clock uild the KHz digital clock using a 555 Timer according to your design in problem 4. Verify with the oscilloscope that the frequency, the pulse length of 25 µsec, and the nominal 5 volt amplitude are approximately correct. Check that a suitable large capacitor placed in parallel with the existing one converts the clock to Hz. Set up a NND gate to control the transmission of clock pulses by means of a DC logical or control voltage. The output pulses for the NND should be positive. Convert to an electronic stopwatch, using the counter / timer and the front panel switch for start and stop. 555 Clock X Probe SCOPE CH. 4./ Trig. CH.. 5V V Panel Switch V Counter/ Timer Set to Totalize Fig. 9.. Digital clock and stop-watch. The JK Flip-flop. Construct an empirical truth table for the JK from your observations using the LED indicators. Since the output depends upon the previous state,, you will need to tabulate n + for both possible previous states, n = and n =. We suggest that you add a redundant column, n + 2, (see truth table in Fig. 9.5)to get a better feel for the behavior of the flip-flop. Experiment #9 9.3 Fall 999

Set CLR = and J = K =. Now drive the clock input of the JK with KHz pulses from your TIMER circuit. Use the oscilloscope to observe the clock input (positive pulses out of the NND gate), and the output,, of the JK. What happens when J = K =? 5V V 555 Clock Panel Switch Wires from 5V or V } J C K CLR 5V or V SCOPE CH.. CH. 4./ Trig. Fig. 9.. JK test circuit. Experiment #9 9.4 Fall 999