Planar interdigitated electrolyte-conductivity sensors on an insulating substrate covered with Ta 2 O 5



Similar documents
Silicon-On-Glass MEMS. Design. Handbook

Development of New Inkjet Head Applying MEMS Technology and Thin Film Actuator

1.Introduction. Introduction. Most of slides come from Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda.

Observation of Long Transients in the Electrical Characterization of Thin Film BST Capacitors

OPTIMIZING OF THERMAL EVAPORATION PROCESS COMPARED TO MAGNETRON SPUTTERING FOR FABRICATION OF TITANIA QUANTUM DOTS

Fabrication of Complex Circuit Using Electrochemical Micromachining on Printed Circuit Board (PCB)

Advanced VLSI Design CMOS Processing Technology

AC coupled pitch adapters for silicon strip detectors

A Remote Plasma Sputter Process for High Rate Web Coating of Low Temperature Plastic Film with High Quality Thin Film Metals and Insulators

Solar Photovoltaic (PV) Cells

Winbond W2E512/W27E257 EEPROM

Lecture 030 DSM CMOS Technology (3/24/10) Page 030-1

Planar Inter Digital Capacitors on Printed Circuit Board

Microstockage d énergie Les dernières avancées. S. Martin (CEA-LITEN / LCMS Grenoble)

Evaluating Surface Roughness of Si Following Selected Lapping and Polishing Processes

4 SENSORS. Example. A force of 1 N is exerted on a PZT5A disc of diameter 10 mm and thickness 1 mm. The resulting mechanical stress is:

Conductivity of silicon can be changed several orders of magnitude by introducing impurity atoms in silicon crystal lattice.

Chapter 1 Introduction to The Semiconductor Industry 2005 VLSI TECH. 1

Coating Technology: Evaporation Vs Sputtering

Exploring the deposition of oxides on silicon for photovoltaic cells by pulsed laser deposition

Lapping and Polishing Basics

Application Note: PCB Design By: Wei-Lung Ho

Micro-Power Generation

Simulation and Design of Printed Circuit Boards Utilizing Novel Embedded Capacitance Material

Coating Thickness and Composition Analysis by Micro-EDXRF

Electrical tests on PCB insulation materials and investigation of influence of solder fillets geometry on partial discharge

High Rate Oxide Deposition onto Web by Reactive Sputtering from Rotatable Magnetrons

MSFET MICROSENS Miniature ph Sensor Module

Introduction to VLSI Fabrication Technologies. Emanuele Baravelli

State of the art in reactive magnetron sputtering

Implementation Of High-k/Metal Gates In High-Volume Manufacturing

Miniaturizing Flexible Circuits for use in Medical Electronics. Nate Kreutter 3M

Photolithography. Class: Figure Various ways in which dust particles can interfere with photomask patterns.

FEATURE ARTICLE. Figure 1: Current vs. Forward Voltage Curves for Silicon Schottky Diodes with High, Medium, Low and ZBD Barrier Heights

Applications and Benefits of Multi-Walled Carbon Nanotubes (MWCNT)

Silicon Wafer Solar Cells

CIRCUITS AND SYSTEMS- Assembly and Printed Circuit Board (PCB) Package Mohammad S. Sharawi ASSEMBLY AND PRINTED CIRCUIT BOARD (PCB) PACKAGE

Nanotechnologies for the Integrated Circuits

Ultra Low Profile Silicon Capacitors (down to 80 µm) applied to Decoupling Applications. Results on ESR/ESL.

Development of Ultra-Multilayer. printed circuit board

Damage-free, All-dry Via Etch Resist and Residue Removal Processes

Sputtered AlN Thin Films on Si and Electrodes for MEMS Resonators: Relationship Between Surface Quality Microstructure and Film Properties

Thin Is In, But Not Too Thin!

Modification of Pd-H 2 and Pd-D 2 thin films processed by He-Ne laser

Microstockage d énergie Les dernières avancées. S. Martin (CEA-LITEN / Grenoble)

Copyright 1996 IEEE. Reprinted from IEEE MTT-S International Microwave Symposium 1996

Lezioni di Tecnologie e Materiali per l Elettronica

Wipe Analysis to Determine Metal Contamination on Critical Surfaces

Sandia Agile MEMS Prototyping, Layout Tools, Education and Services Program

Supporting information

Etching Etch Definitions Isotropic Etching: same in all direction Anisotropic Etching: direction sensitive Selectivity: etch rate difference between

Development of High-Speed High-Precision Cooling Plate

Through-mask Electro-etching for Fabrication of Metal Bipolar Plate Gas Flow Field Channels

Supercapacitors. Advantages Power density Recycle ability Environmentally friendly Safe Light weight

Good Boards = Results

Low-cost Printed Electronic Nose Gas Sensors for Distributed Environmental Monitoring

Barrier Coatings: Conversion and Production Status

How to measure absolute pressure using piezoresistive sensing elements

Improved Contact Formation for Large Area Solar Cells Using the Alternative Seed Layer (ASL) Process

Micro Power Generators. Sung Park Kelvin Yuk ECS 203

Demonstration of sub-4 nm nanoimprint lithography using a template fabricated by helium ion beam lithography

MICROPOSIT LOL 1000 AND 2000 LIFTOFF LAYERS For Microlithography Applications

MOS (metal-oxidesemiconductor) 李 2003/12/19

Automotive Electronics Council Component Technical Committee

ELEC 3908, Physical Electronics, Lecture 15. BJT Structure and Fabrication

LUXEON LEDs. Circuit Design and Layout Practices to Minimize Electrical Stress. Introduction. Scope LED PORTFOLIO

PIEZOELECTRIC TRANSDUCERS MODELING AND CHARACTERIZATION

Reactive Sputtering Using a Dual-Anode Magnetron System

Vertical Probe Alternative for Cantilever Pad Probing

Polymer Termination. Mechanical Cracking 2. The reason for polymer termination. What is Polymer Termination? 3

Module 7 : I/O PADs Lecture 33 : I/O PADs

Focused Ion beam nanopatterning: potential application in photovoltaics

Contamination. Cleanroom. Cleanroom for micro and nano fabrication. Particle Contamination and Yield in Semiconductors.

DESIGN, FABRICATION AND ELETRICAL CHARACTERIZATION OF SOI FINFET TRANSISTORS

Use of Carbon Nanoparticles for the Flexible Circuits Industry

Dry Etching and Reactive Ion Etching (RIE)

Electron Beam and Sputter Deposition Choosing Process Parameters

Power Dissipation Considerations in High Precision Vishay Sfernice Thin Film Chips Resistors and Arrays (P, PRA etc.) (High Temperature Applications)

High power picosecond lasers enable higher efficiency solar cells.

Low loss fiber to chip connection system for telecommunication devices

Impedance Matching and Matching Networks. Valentin Todorow, December, 2009

AN900 APPLICATION NOTE

METHODS FOR THE CALIBRATION OF ELECTROSTATIC MEASURING INSTRUMENTS

ECP Embedded Component Packaging Technology

RF Energy Harvesting Circuits

Mylar polyester film. Electrical Properties. Product Information. Dielectric Strength. Electrode Size. Film Thickness

Laboratory #3 Guide: Optical and Electrical Properties of Transparent Conductors -- September 23, 2014

Chip-on-board Technology

Innovative Wafer and Interconnect Technologies - Enabling High Volume Low Cost RFID Solutions

Design and Simulation of MEMS Vibration Sensor for Launch Vehicles

European bespoke wafer processing & development solutions for : Grinding, CMP, Edge Treatment, Wafer Bonding, Dicing and Cleaning

Ion Beam Sputtering: Practical Applications to Electron Microscopy

Chapter 7-1. Definition of ALD

Connectivity in a Wireless World. Cables Connectors A Special Supplement to

Amorphous Silicon Backplane with Polymer MEMS Structures for Electrophoretic Displays

AT11805: Capacitive Touch Long Slider Design with PTC. Introduction. Features. Touch Solutions APPLICATION NOTE

Dry Film Photoresist & Material Solutions for 3D/TSV

Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications

Embedded Integrated Inductors With A Single Layer Magnetic Core: A Realistic Option

Transcription:

Sensors and Actuators B 43 (1997) 211 216 Planar interdigitated electrolyte-conductivity sensors on an insulating substrate covered with Ta 2 O 5 W. Olthuis a, *, A.J. Sprenkels b, J.G. Bomer a, P. Bergveld a a MESA Research Institute, Uni ersity of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlands b SC, Gondel 17-39, 8243 BV Lelystad, The Netherlands Accepted 30 April 1997 Abstract Interdigitated electrolyte-conductivity sensors with an added top layer of insulating Ta 2 O 5 have been realized. The electrodesubstrate structure under the Ta 2 O 5 film has been planarized in order to obtain a totally flat top surface. In addition, the electrodes have been applied on a totally insulating substrate, thus reducing the parasitic sensor capacitance by a factor of ten. 1997 Elsevier Science S.A. Keywords: Electrolyte-conductivity sensors; electrode-substrate structure; Ta 2 O 5 1. Introduction The measurement of electrolyte conductivity (EC) is common practice in analytical chemistry as well as in process industry. Good maintenance and non-continuous use of an EC sensor in a laboratory environment may prolong its useful life, whereas fouling of the sensor during continuous use in a process-line can shorten its life time considerably. EC determination in small sample volumes and in some in-line processes requires small dimensions of the sensor, which makes the effect of the non-ideal electrode-solution interfacial impedance increasingly problematic [1]. The problem of fouling as well as the effect of the electrode impedance play a less dominant role in the sensor behaviour, when the metal electrodes of the sensor are provided with a thin Ta 2 O 5 insulating film [2]. Fouling of this smooth, mechanically hard and chemically resistant surface is far less probable than fouling of a conventional rough, platinized electrode surface and, in addition, mechanical and chemical cleaning is facilitated. Moreover, the specific nature of the Ta 2 O 5 solution interface provides the electrode with a stable and relatively low oxide solution impedance, allowing sensor miniaturization. The desirability of * Corresponding author. miniaturization as well as a monolithic sensor structure led to the interdigitated electrode structure as shown in Fig. 1(a) and (b) [3]. The cross-sectional view of the original design (Fig. 1(b)) shows that the Pt electrodes are applied on top of the SiO 2 layer on the Si substrate over which the insulating Ta 2 O 5 film is applied. This fabrication process has two consequences: first, the minimal thickness of the Ta 2 O 5 film is related to the thickness of the Pt electrodes in order to prevent cracks due to a bad step coverage at the Pt SiO 2 step, and secondly, the Ta 2 O 5 top layer contains steps, comparable to that of the Pt electrodes. These consequences are disadvantageous: the resulting relatively thick Ta 2 O 5 film causes a sub- Fig. 1. (a) Impression of an interdigitated electrode pair showing the electrode width W, their length L and the interelectrode spacing S. (b) Cross-section of the previous device: an Si substrate with 1.3 m SiO 2 on top of which the 20 nm Ti+75 nm thick Pt electrodes are evaporated. The total device is covered with a 120 nm thick insulating Ta 2 O 5 film [3]. 0925-4005/97/$17.00 1997 Elsevier Science S.A. All rights reserved. PII S092 5-4005(97)00157-3

212 W. Olthuis et al. / Sensors and Actuators B 43 (1997) 211 216 Fig. 2. (a) Cross section of the sensor with measurand R el and relevant parasitic components. (b) Equivalent circuit of the conductivity sensor. Note: C p =2C p. Fig. 3. Two methods to planarize the conductivity sensor: (a) by shallow etching in the substrate and (b) by deposition of filler material between the Pt electrodes. optimal capacitive coupling to the solution and any subsequent modification of the top layer with an additional thin membrane (for biosensor applications) is difficult due to the steps in the Ta 2 O 5 surface. An additional disadvantage of the former design is the parasitic capacitive coupling between the Pt electrodes and the conducting Si substrate via the 1.3 m thick SiO 2 film. The resulting parasitic capacitance, being parallel to the sensor impedance, causes a loss in sensitivity. In this paper we propose a new method of sensor fabrication. In this method, the insulating substrate layer and the Pt electrodes form one planar surface on which a layer of Ta 2 O 5 is applied, which can be very thin as no steps have to be covered. Of course, the layer itself is now also without steps. Additionally, in the proposed method, the sensor structure is fabricated on a totally insulating substrate, thus greatly reducing the parasitic capacitance via the conducting substrate of the previous design. The effect of the two proposed changes in the sensor fabrication can best be illustrated by an equivalent circuit of the original sensor, shown in Fig. 2(a) and (b). In Fig. 2, the double layer impedance is not included, on one hand because of the presence of C ox,on the other hand because of the specific nature of the Ta 2 O 5 solution interface [2,3]. The effect of other remaining parasitic components is neglected. The introduction of an insulating substrate will greatly reduce the parasitic capacitor C p and the use of a very thin Ta 2 O 5 layer on a flat sensor structure will noticeably increase the value of capacitor C ox. Both proposed modifications result in a more accurate and easy detection of the electrolyte resistance R el, which is the variable of interest. The fabrication of the sensor will be treated and the effect of both the planarization and the absence of a conducting substrate will be shown. 2. Experimental 2.1. De ice preparation Several options, available for the choice of a nonconducting substrate have been evaluated: 2.1.1. Si wafer with a ery thick layer of SiO 2 Because of the quadratic increase in oxidation time with the obtained thickness of the oxide, only a layer of maximally 3 m is realistic. This would reduce the capacitance C p of Fig. 2 only marginally and, therefore, this option was discarded. 2.1.2. Alumina wafers It appeared that circular 3 in alumina wafers are not readily available. Moreover, the surface structure of alumina is rough, making this material unsuitable for the proposed planarized sensor. 2.1.3. Quartz wafers Quartz wafers are rather expensive and do not offer any particular advantage over glass for the application as substrate material, as pointed out in the next option.

W. Olthuis et al. / Sensors and Actuators B 43 (1997) 211 216 213 Fig. 4. (a h) Process scheme of the planar EC sensor. (f) depicts the final sensor structure itself, (g) and (h) show the subsequent steps necessary for the contact holes. The process conditions are given in Table 1. 2.1.4. Glass wafers We decided to use glass wafers, which are readily available for anodic bonding purposes. These glass wafers, type Hoya SD2, have a very smooth top surface. The specific resistivity is 4 110 16 cm 1 and the dielectric constant is 6, both values at 20 C. Cheaper glass wafers are also available, but the many enclosed impurities might contaminate both the sensor and the process equipment during the high processing temperature of Ta 2 O 5 formation (about 500 C). Various technologies for planarization are already developed for integrated circuit processing. However, in those applications the preservation of electrical properties is the main issue, resulting in rather complicated processes [4]. For this reason, we developed our own technology to obtain a planar substrate Pt electrode top layer. Principally, a planarized sensor can be obtained during processing in two different methods, depicted in Fig. 3(a) and (b). The electrodes can be applied on a flat substrate and the space between the electrodes can be filled with an insulating material to get a flat structure on top of which the Ta 2 O 5 film can be applied, as shown in Fig. 3(a). Another option is the etching of shallow channels in the substrate in which the electrodes are deposited. Subsequently, the Ta 2 O 5 film can be applied on the flat structure, as shown in Fig. 3(b). In this paper, a process based on the latter planarization method (Fig. 3(b)) is implemented. The proposed fabrication process is based on the previous one [3] and does not require new, complicated process steps. The new process is self-aligning, in that possible alignment problems of photo-masks on already etched structures do not occur. The consecutive steps of this process are schematically shown in Fig. 4(a h). Using the process depicted in Fig. 4 and described in more detail in Table 1, ten different designs of the EC sensor are produced on one wafer. The number of electrode fingers ranges from N=8 100, the finger width W=10 170 m, their length L=500 1600 m and the spacing between the fingers S=10 170 m. Thus we obtained EC sensors with cell constants ranging from 0.14 4.44 cm 1 [3]. A number of these sensors were sawn from the wafer and the 3 4 mm 2 chips were glued on an 8 100 mm 2 printed circuit board (PCB) carrier and the Pt electrodes were connected to the copper strips on the PCB with standard wire bonding. The copper strips, the bonding wires and the edges of the chip were covered with epoxy for insulation and protection.

214 W. Olthuis et al. / Sensors and Actuators B 43 (1997) 211 216 Table 1 Details of the process steps as shown in Fig. 4 Step number What? How? Fig. 4(a) Photolithography Fig. 4(b) Glass etching HF:H 2 O=1:50; 1 min @ 20 C; channel depth 90 nm Fig. 4(c) d.c. sputtering Ti: 2 min and 40 s @ 200 W; layer 18 nm Pt: 3 min and 15 s @ 200 W; layer 75 nm Fig. 4(d) Lift-off 5 min in Aceton, then 30 s ul- Fig. 4(e) e-beam evapotrasonic in Aceton Ta: 32 s, 8 kv @ 5Å s 1 ; layer ration 16 nm Fig. 4(f) Oxidizing Ta:3h@500 C in O 2 ; layer 38 nm Ta 2 O 5 Fig. 4(g) Photolithogra- Fig. 4(h) phy Reactive ion Through Ta 2 O 5 ; 1 min, 50 etching mtorr @ 50 W; 30 sccm SF 6 and 5 sccm O 2 2.2. Measurement set-up The measurements in this paper are focused on the novel steps in the sensor preparation, i.e. the planarization and the use of an insulating substrate. The effect of the planarization was analyzed with a Sloan Dektak 3030 stylus surface profiler. Electrical characterization to determine the reduction of the parasitic capacitance with respect to the original design of Fig. 1 was performed with an HP 4194A impedance/gain-phase analyzer. 3. Results and discussion The electrical characterization is restricted to measurements in air. The results of the measurements are given in Table 2 and suffice to show the effect of the introduction of an insulating substrate. As expected in air, any resistive part in the measured results is absent and the sensor+probe leads behave like a pure capacitor. The probe leads themselves introduce a substantial part of the measured capacitance as can be seen from the results of Table 2. The capacitances of the leads can be cancelled out in practice by active shielding techniques. What is left then, as shown Fig. 5. Simulation results showing the relation between [KCl] and the corresponding specific resistivity ( ). Continuous line: theoretical relation; + markers: C p =12.9 pf; markers: C p =1.2 pf. Other component values: C ox =600 pf, C el =0.1 pf. Measurement frequency: 200 khz [3]. in the last column of Table 2, is the capacitance of the sensor only, which is in the case of the glass-based sensor is a factor of 10 smaller than that of the Si-based sensor. This improvement can be translated either into a wider measurement range at equal accuracy or in a better accuracy at equal measurement range. This effect can be illustrated using the equivalent circuit of the sensor, shown in the introduction of this paper, Fig. 2(b). The relation between the KCl concentration and its corresponding specific resistivity is well known and is shown in Fig. 5 as a continuous line. Subsequently, measurements in KCl were simulated, using the circuit of Fig. 2(b) and Maple V (Waterloo Maple Software) to determine the specific resistivity,, at a certain KCl concentration from the calculated sensor impedance, including its parasitic components. Using realistic component values found by measurements, shown in Table 2 and in the caption of Fig. 5; simulation results are shown in Fig. 5 both for the Si-substrate based sensor (markers: +) and for the glass-substrate based sensors (markers: ). This figure clearly shows that the glass-substrate based sensor can successfully be used at low concentrations, without the need for any correction on the measured data and without loss in sensitivity. The results of measurements showing the effect of the planarization are depicted in Fig. 6(a) and (b). In Fig. 6(a), the result of a surface scan over the unplanar sensor top layer is shown. Clearly, the height Table 2 Results of the electrical characterization in air of a Si- and glass-based EC sensor Probe leads (measured, pf) Probe+sensor (measured, pf) Sensor only (calculated, pf) Si substrate 4.6 17.5 12.9 Glass substrate 4.6 5.8 1.2

W. Olthuis et al. / Sensors and Actuators B 43 (1997) 211 216 215 Fig. 6. Surface scan over an interdigitated EC sensor fabricated (a) according to the previous process (Fig. 1(b)), and (b) according to the new planar process of Fig. 4. of the ridges in the Ta 2 O 5 top layer reflects the height of the Ti+Pt layer of 95 nm on top of the SiO 2 substrate layer (see Fig. 1(b)). In Fig. 6(b), almost unnoticeable ridges of only a few nm remain, indicating the successful result of the new planar process of fabrication shown in Fig. 4. Subsequent measurements showing the benefits of this planar top layer, a better capacitive coupling to the solution via a thinner Ta 2 O 5 film and the feasibility to modify the EC sensor with (selective) membranes, are in progress. 4. Conclusions Interdigitated electrolyte-conductivity sensors have been realized with an added Ta 2 O 5 top layer, making fouling less likely and cleaning easy. By a planar process of fabrication, the Ta 2 O 5 top layer of the EC sensor is totally flat within a few nanometers. Realization of the sensor on a insulating glass substrate has reduced the parasitic sensor capacitance by a factor of ten, from 12 down to 1.2 pf. The beneficial effect of the reduction of this parasite on the sensor performance has been shown by simulations. References [1] P. Jacobs, A. Varlan, W. Sansen, Design optimisation of planar electrolytic conductivity sensors, Med. Biol. Eng. Comput. 33 (1995) 802 810. [2] W. Olthuis, A. Volanschi, J.G. Bomer, P. Bergveld, A new probe for measuring electrolytic conductance, Sensors and Actuators B 13/14 (1993) 230 233. [3] W. Olthuis, W. Streekstra, P. Bergveld, Theoretical and experimental determination of cell constants of planar-interdigitated electrolyte conductivity sensors, Sensors and Actuators B 24/25 (1995) 252 256. [4] Y. Hazuki, T. Moriya, A damage-free perfect planarization method using bias-sputtered SiO 2, IEEE Trans. Electr. Devices 34 (1987) 628 632. Biographies Wouter Olthuis was born in Apeldoorn, the Netherlands, on October 23, 1960. He received the MS degree in electrical engineering from the University of Twente, Enschede, the Netherlands in 1986, and a PhD degree from the Biomedical Engineering Division of the Faculty of Electrical Engineering, University of Twente, in 1990. The subject of his dissertation was the use of Iridium oxide in ISFET-based coulometric sensor-actuator devices. Currently he is working as an Assistant Professor in the Biosensor Technology Group, part of the MESA Research Institute, of the University of Twente. Ad Sprenkels received his MS and PhD degrees in electrical engineering from the University of Twente, Enschede, The Netherlands, in 1983 and 1988, respectively. During his PhD research his work was focused on silicon acoustic sensors with the necessary dedicated electronics. From 1988 until 1990 he has been working as a sensor engineer with 3T. In 1990 he joined the R&D department of Microtel and was involved in the development of various hearing aid transducers. Since 1994 he has worked as a consultant on micro system technology and analog electronics. Johan Bomer was born in Eibergen, The Netherlands, on September 6, 1958. He received the BS degree in applied physics from the Hoger Technische School, Enschede, The Netherlands, in 1981. From 1983 until 1986 he worked as technologist in the Semiconductor Physics Group of the University of Groningen. Since 1986 he has worked as a technologist in the Biosensor Technology Group, part of the MESA Research Institute, of the University of Twente. Piet Berg eld was born in Oosterwolde, The Netherlands, on January 26, 1940. He received the MS degree

216 W. Olthuis et al. / Sensors and Actuators B 43 (1997) 211 216 in electrical engineering from the University of Eindhoven, the Netherlands, in 1965 and a PhD degree from the University of Twente, the Netherlands, in 1973. The subject of his dissertation was the development of IS- FETs and related devices, the actual invention of the ISFET, since also investigated by many international research groups of Universities, as well as industry. Since 1965 he has been a member of the Biomedical Engineering Division of the Faculty of Electrical Engineering (University of Twente) and was in 1984 appointed as Full Professor in Biosensor Technology. He is one of the project leaders in the MESA Research Institute. His research subjects still concern the further development of ISFETs and biosensors based on IS- FET technology as well as physical sensors for biomedical and environmental applications, resulting up to now in more than 250 papers..