Design and analysis of flip flops for low power clocking system

Design and analysis of flip flops for low power clocking system Gabariyala sabadini.c PG Scholar, VLSI design, Department of ECE,PSNA college of Engg and Tech, Dindigul,India. Jeya priyanka.p PG Scholar, VLSI design, Department of ECE,PSNA college of Engg and Tech, Dindigul, India. Abstract The register element (flip-flop) is a basic building block to design and clocking system, which consists of the clock distribution network and register element. A large portion of the on chip power is consumed by the clocking system. The total power consumption of the clocking system depends on both clocking distribution network and also the register elements (flip flops). The power consumption of register element is higher than that of the clocking distribution network. The objective is to reduce the power consumption by the register elements(flip-flop). A method of Conditional Data Mapping Flip flop(cdmff) was proposed earlier. The drawbacks of CDMFF are, it uses more number of transistors and it has a floating node on its critical path. Moreover it cannot be used in noise intensive environment. So one new design of register element Double edge triggered flip-flop (PDETFF) is proposed. In this method, the number of transistor is reduced by sharing the clocked pair transistors. The floating node problem is also avoided by using Pseudo nmos technology. The design can be implemented in DSCH and MICROWIND 3.1 CMOS layout tool. The performance is analysed in terms of total number of transistors (N) Area (A), Power (P). analysis of the performance parameters shows the performance of PDETFF is superior compared to the conventional flip flop. Overall power is reduced in PDETFF when compared to the existing flip-flop and 14 to 21% reduction of power can be achieved. In addition due to the absence of floating node problem low swing can be easily incorporated in to the register element (flip-flop) to build clocking system. Keywords: flip-flops, low power consumption, register element, double edge triggering. I. INTRODUCTION A System on a Chip or System On Chip(SoC or SOC) is an Integrated Circuit (IC) that integrates all components of a computer or other electronic system in to a single chip. It may contain digital, analog, mixed signal and often radio frequency functions - all on a single chip substrate. SoCs are very common in the mobile electronics market because of their low power consumption. Low power electronics are electronics that have been designed to use less electric power. On comparing the results, power consumption being the bottle neck in achieving high performance and it is listed as one of the top 3 challenges in ITRS 2008. The clocking system, which consists of the clock distribution network and sequential elements (flip-flops and latches),is one of the most power consuming in a VLSI system [2],[5]. It accounts for 30% to 60% of the total power dissipation in a system [2]. Flip-flop is one of the most power consumption components. As the power budget of today s portable digital circuit is severely limited it s important to reduce the power dissipation in both clock distribution networks and flip-flops. The power delay of the flip-flops should be minimized for efficient implementation. While using positive edge triggered D flip-flop, if clock period raise goes from 0 to 1 and input D=0,this makes Q=0 while using negative edge triggered D flip-flop if clock period raises goes from 0 to 1 and input D=1 this makes Q=1, during this power, the clocking delay is increased inorder to overcome this problem we are moving to double edge triggering which consume less clocking delay and power consumption. ISSN: 2348 8549 www.internationaljournalssrg.org Page 61

II. TECHNIQUES FOR FLIP-FLOPS FOR LOW POWER CLOCKING SYSTEM As transistor counts and clock frequencies have increased,power consumption how is a primary design constraint compared to area and speed. Instantaneous power P(t) drawn from the power supply is proportional to supply voltage Vdd and supply current idd(t) is P(t)=idd(t)*Vdd Power consumption is determined by several factors including frequency f,supply voltage V, data activity P total =P static +P dynamic +P short circuit In the above equation, dynamic power consumption is expressed as, P dynamic = cv 2 f P short circuit is the short circuit power which is caused by the finite rise and fall time of input signals, resulting in both pull up network and pull down network to be ON for a short while. P short circuit =I short circuit *Vdd P leakage is a leakage power. The sub-threshold leakage current occurs when the supply voltage is scaling down then the threshold voltage also decreases to maintain the performance. Sub-threshold transistors. leakage is the dominant now, P leakage =I leakage *Vdd Based on these factors. There are different ways to lower the power consumption shown as follows. 1) Reducing Capacity of Clock load: One effective way of low power design for clocking system is to reduce clock capacity load by minimizing the clocked transistor because clocked transistor consume more power. This local clock load reduction will also decrease the global power consumption. This method will reduce the power by decreasing the clocked transistors. 2) low swing voltage on clock distribution: Since power is a quadratic function of voltage we can use low swing voltage on the clock distribution network for reducing the clocking power consumption. For using a low swing voltage the flip-flop should be a low swing flip-flop (for example, low swing double-edge flip-flop (LSDFF) [7] is a low swing flip-flop because the low swing clock may leads to performance degradation. The low swing method reduces the power consumption by decreasing voltage in equation. 3) Two ways to reduce the switching activity: Conditional operation (eliminate redundant data switching: conditional discharge flip-flop (CDFF) [8], conditional capture flip-flop (CCFF) [3]) or gating. A. Clock gating: When a certain block is ideal, we can disable the clock signal to that block to save power. Gated master slave flip-flop was proposed in [4]. By this method we can reduce the clock gating by reducing the switching activity this is the one method to save the power. B. Conditional operation: It eliminates redundant data transition. When input stays at logic one the internal node kept charging and discharging without performing any useful computation. It is referred as redundant data transition. The conditional operation technique is needed to control the redundant transition this reduces the power consumption by decreasing data activity ( ) in the power equation. 4) Reducing short current power: By splitting the path it will reduce the short current power since n-mos and p-mos are driven by separate signals. 5) Double edge triggering: Using half frequency on the clock distribution network will save approximately half of the power consumption on the clock distribution network. Double clock edge triggering method reduces the power by decreasing the frequency f in equation [6],[10]. We will elaborate more in this paper. III. ANALYSIS OF FLIP-FLOP ARCHITECTURE 1.Conitional Data Mapping Flip-flop(CDMFF): A large part of the on chip power is consumed by clock drivers [1].The conditional data mapping flip-flop (CDMFF) shown in fig:1 is one of the most efficient method for reducing the redundant data transitions. CDMFF is a single edge triggered flip-flop consists of 22 number of transistors. It uses 7 clocked transistors and 15 un clocked transistors [9]. The first stage consists of 2.5,6,14 transistors. The second stage consists of 2.5,14,20 transistors. Data D input as given in first stage. The Q and QB output are obtained in the second stage. The CDMFF has a floating node on critical path because its first stage is dynamic. When clock signal CLK transistor from 0 to 1,CLKB will stay 1 for a short mean while time. It produces an implicit pulse window for evaluation. It uses an output feedback structure which is used to eliminate the unwanted transitions when a redundant even t is predicted. CDMFF is not used in ISSN: 2348 8549 www.internationaljournalssrg.org Page 62

noise environment. CDMFF is difficult to apply low power techniques. 2.Cross Charge Controlled Flip-flop(XCFF): The major sources of power dissipation in the conventional semi-dynamic designs are the redundant data transitions and large pre-charge capacitance. The CDMFF method is used for reducing the redundant data transition in the flip-flops fig:1. The large pre-chargecapacitance in a variety of designs results from the fact that both the pull-up and pull-down transistors are driven by this pre-charge node. These transistors being driving large output loads contribute to most of the capacitance at this node. This common drawback of many conventional designs was considered in the design of XCFF (fig:2). By splitting the dynamic node in to two, it reduces the power dissipation,each one separately driving the pull-up and pull-down transistors. During one CLK cycle any one of the two dynamic node X1 and X2 is switched ON. Without any degradation in speed the total power consumption is reduced. One major drawback of this design is the redundant precharge at node X1 and X2 for data patterns containing more 0s and 1s, respectively. This effect of charge sharing becomes uncontrollably large when complex functions are embedded in to the design. 3.Dual Dynamic node hybrid Flip-flop(DDFF) : Kalarikkal Absel et.al.[11] introduces a new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on (DDFF). Node X1 is pseudo-dynamic, with a weaker inverter acting as a keeper, whereas, compared to the XCFF, in the new architecture node X2 is purely dynamic. The operation of the flip-flop can be divided in to two phases: 1) the evaluation phase, when CLK is high, and 2)the pre-charge phase, when CLK is low. This method results in a larger pre-charge node capacitance and hence higher power consumption. Fig:1Conditional Data Mapping Flip-flop (CDMFF) total of 22 transistors including 7 clocked transistors. 1. Fig:2 Cross Charge Controlled Flipflop(XCFF) total of 21 transistors including 4 clocked transistors. Fig:3 Dual Dynamic node hybrid Flip-flop(DDFF) total of 18 transistors including 6 clocked transistors. IV. PROPOSED DOUBLE EDGE TRIGGERED FLIP-FLOP(PDETFF) The PDETFF is a double edge triggered flip-flops. It uses less number of transistors. It consists of 14 transistors. Among 14 trnsistors there are 8 clocked transistors.the pmos, PM1 is always on and is used to charge the internal node X1. The internal node X1 is connected to Vdd by an always on PM1, so X1 is floating, resulting in enhancement of noise robustness of node X1. This will solve the floating point problem. The ISSN: 2348 8549 www.internationaljournalssrg.org Page 63

always ON PM1 is a weak pmos transistor. This scheme combines pseudo nmos with a conditional mapping technique where a feedback signal, y, controls nmos NM1. When input D stays 1, Q1=1,Nm3 is ON, NM1 will shut off to avoid the redundant switching activity at node X1 as well as any short circuit current. Pmos PM2 should pull Q up when D transistor to 1. The second NMOS branch (NM2) is responsible for pulling down the output of Q1 if D=0 and X2=1 when the clock pulse arrives pmos in PM2 should turn on nmos NM2 when D=0.Although PM1 is always ON, short circuit only occurs one time when D makes a transition of 0 to 1, and the discharge path is disconnected after two gates delay by Y (turning of NM1). After that,if D remains at 1,the discharge path is already disconnected by NM1 there would be no short circuit. An inverter is placed after Q1, providing protection from direct noise coupling. When CLK rises, CLKB will stay high for a short interval of time equal to one inverter delay. During this period, the clocked branch (NM6 and NM4) turns ON which is denoted as branch A in the fig and the flip-flop will be in the evaluation period. Note that the other clocked branch B (NM5 and NM7) is disconnected. When CLK falls, will CLKB rises, and CLKB-delay will stay HIGH for one inverter delay period during which the transistors NM5 and NM7 are both ON, and the flip-flop is in the evaluation mode. In summary, the clock-sharing scheme reduces the number of clocked transistors. The reduction of the number of clocked transistor reduces the switching activity, decreasing the power usage. Fig:4 proposed double edge triggered flip-flop (PDETFF) total of 14 transistors including 8 clocked transistors. V. SIMULATION RESULTS AND DISCUSSIONS: The simulation results were obtained from DSCH & MICROWIND3.1 simulations in 0.12 m CMOS technology at room temperature. V dd is 1.8 V. A clock frequency of 250 MHz is used. Each design is simulated using the circuit at the layout level. Performance parameters such as Area and Power are obtained from layout simulation. The TABLE I:shows a comparison of the flipflop characteristics in terms of power and area. Fig 5:shows the schematic diagram of proposed double edge triggered flip-flop. Fig 6:shows the layout of our proposed double edge triggered flip-flop. The results of the simulation is obtained by four ways which is represented in fig 7,fig 8,fig 9, fig 10. The operation 1 is (fig 7) when D=0 and CLK=0 then the respective output is also 0. The operation 2 is (fig 8) When D=0 and CLk=1 then the respective output is 0. The 3 rd operation is (fig 9) When D=1 and CLK=0 then the respective output is 1. The 4 th operation is(fig 10) When D=1 and CLK=1 then the respective output is 1. Fig 5: schematic diagram of PDETFF ISSN: 2348 8549 www.internationaljournalssrg.org Page 64

Fig 6: layout diagram of PDETFF Fig 9: Operation 3 when D=1 CLK=0 OUT=1 Fig 7: Operation-1 when D=0 CLK=0 OUT=0 Fig 10: Operation 4 when D=1 CLK=1 OUT=1 Fig 8: Operation 2 when D=0 CLK=1 OUT=0 Fig11:output waveform of PDETFF power=11.325µw ISSN: 2348 8549 www.internationaljournalssrg.org Page 65

Fig 12:Comparison of total no. of transistors. Fig 15:Comparison of power consumption TABLE I : Comparison of simulation results Fig 13:comparison total no. of clocked transistors Flipflop No of transistor Clocked transisto rs Area (µw 2 ) Powe r (µw) CDMFF 22 7 462 13.30 6 XCFF 21 4 312 14.33 8 DDFF 18 6 276 13.89 6 PDETF F 14 8 228 11.32 5 VI. CONCLUSION: In this paper several design techniques for register elements are reviewed. One effective method, double edge triggered is elaborated. Following this approach, double edge triggering flip-flop is proposed, which reduces power about 14 to 21% and area about 17 to 50%. The performance analysis is carried out on the register element. In the view of power consumption and area, the proposed PDETFF out performs prior arts in register element design. ACKNOWLEDGEMENT Fig 14: Comparison of Area The authors would like to thank Mr.P.Nagarajan M.E.,(Ph.D)., Assistant Professor, Department of ECE, PSNA College of Engg and Tech, Dindigul, India, for his helpful suggestions. ISSN: 2348 8549 www.internationaljournalssrg.org Page 66

REFERENCES [1] T. Sakurai, Low power CMOS design through Vth control and low swing Circuits, in Proc. ISLPED, 1997, pp. 1 6 [2] H. Kawaguchi and T. Sakurai, A reduced clock-swing flipflop(rcsff) for 63% power reduction, IEEE J. Solid-State Circuits, vol.33, no. 5, pp. 807 811, May 1998. [3] B. Kong, S. Kim, and Y. Jun, Conditional-capture flip-flop for statistical power reduction, IEEE J. Solid-State Circuits, vol. 36, no. 8, pp.1263 1271, Aug. 2001. [4] D. Markovic, B. Nikolic, and R. Brodersen, Analysis and design of low-energy flip-flops, in Proc. Int. Symp. Low Power Electron. Des., Huntington Beach, CA, Aug. 2001, pp. 52 55. [5] A. Chandrakasan, W. Bowhill, and F. Fox, Design of High- Performance Microprocessor Circuits, 1st ed. Piscataway, NJ: IEEEPress,2001. [6] C. L. Kim and S. Kang, A low-swing clock double edge-triggered flip-flop, IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 648 652,May2002. [7] Peiyi Zhao,Pradeep Golconda, Magdy A.Bayoumi, Robert A.Barcenas, and Weidong Kuang, Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop, IEEE Trans. Very Large Scale. Mar-2003. [8] P. Zhao, T. Darwish, and M. Bayoumi, High-performance and low power conditional discharge flip-flop, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 477 484, May 2004. [9] C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki, Conditional data mapping flip-flops for low-power and high-performance systems, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 12, pp. 1379 1383, Dec. 2006. [10] P. Zhao, J. McNeely, P. Golconda, M. A. Bayoumi, W. D. Kuang, andb. Barcenas, Low power clock branch sharing double-edge triggeredflip-flop, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 15,no. 3, pp. 338 345, Mar. 2007. [11] Kalarikkal Absel,Lijo Manuel, and R.k.Kavitha, Low-power Dual Dynamic Node Pulsed Hybrid flip-flop Featuring Efficient Embedded Logic, IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol.21, No.9,pp. 1693-1704,2013. ISSN: 2348 8549 www.internationaljournalssrg.org Page 67