An Ultra-low low energy asynchronous processor for Wireless Sensor Networks

Transcription

1 An Ultra-low low energy asynchronous processor for Wireless Sensor Networks.Necchi,.avagno, D.Pandini,.Vanzago Politecnico di Torino ST Microelectronics

2 Wireless Sensor Networks - Ad-hoc wireless networks - Sensing - Computation - Actuation Application areas: Monitoring Building automation Health care, Medical Emergency response Automotive Async 06 - March

3 3 Key WSN Requirements Flexibility (general purpose design) High energy efficiency (battery powered) Extremely wide voltage supply range Exhausted battery or energy scavenging Fast and inexpensive wake-up event driven power management (not predictable) Sporadic high computational load Encryption (security) Aggregation, distributed data processing

4 Sensor node architecture Main components of a WSN node: Microcontroller Atmel AVR TI Memory MSP430 Radio Sensors / Actuators Power supply Battery (energy storage) Power scavenging Async 06 - March

5 5 Circuit-level Power Management Management Clock Gating Power Gating Dynamic Voltage Scaling Adaptive Body Biasing Save energy while Idle X X Active X X Scenario Idle Time ong Deadlines DVS can be obtained by: Off-line pre-computed voltage/frequency tables High delay margins Evaluated on-line: PowerWise,, Razor, Asynchronous, De-synchronization

6 Closed-loop loop DVS technique PowerWise: Samples, with a high frequency clock, the output of a digital delay line, and arrange voltage supply to deliver required performance Razor: Detects timing errors comparing values stored in duplicated slave latches, in which the second is clocked half clock cycle later, restarts the pipeline and arranges voltage supply accordingly Asynchronous with Dual-Rail encoding: (Quasi) delay insensitive implementation, that guarantees correctness for (almost) every voltage supply and process variation Asynchronous with Bundled Data encoding: A digital delay line output is directly used to generate a local clock signal, resulting in a direct dependence between voltage supply and delay period Async 06 - March

7 7 De-synchronization Synchronous Desynchronize Asynchronous CK CK

8 8 Design Flow HD RT Synthesis & Optimization Obtain asynchronous implementation from synchronous specification: ibrary Netlist De-synchronization Netlist Physical Design ayout Think synchronously Design synchronously De-synchronize (automatically) Test synchronously Run asynchronously

9 Synchronous circuit MS flip-flop CK 0 0 Async 06 - March

10 De-synchronization C C C C C 0 C 0 Async 06 - March

11 11 De-synchronization Distributed micropipeline-style controllers substitute the clock network C C C C C C The data path remains intact!

12 12 Flow equivalence [Guernic, Talpin, ann, 2003] A B

13 13 Flow equivalence [Guernic, Talpin, ann, 2003] K A B Synchronous behavior A B De-synchronized behavior

14 Flow equivalence [Guernic, Talpin, ann, 2003] K A B Synchronous behavior A B De-synchronized behavior Theorem: The de-synchronization model preserves flow-equivalence Async 06 - March

15 15 Flow equivalence [Guernic, Talpin, ann, 2003]

16 De-synchronization Benefits For the end user: Reduced electromagnetic emission Process Variation tolerance Enables partial average case design, Async 06 - March wrt process & environment variation (not wrt data-dependent dependent delay) The resulting circuit will be: Ready for frequency and voltage scaling Inherently more robust to delay variations Virtually no performance or area overhead wrt synchronous For the designer Conventional EDA Tools and design flow imited design time and effort, fully automated Re-use legacy designs 16

17 17 Asynchronous advantages not offered by de-synchronization Fine-grained power management The desynchronized circuit inherits the synchronous clock gating Fine-grained pipelining The pipeline structure is not changed Data-dependent delays Could be exploited by using a datapath with completion detection (work in progress) Robustness with respect to uncorrelated local variability Would require completion detection

18 18 Synchronous ogic Interfacing C C C FAST C C C OGIC Data path (not modified) Handshaking line

19 19 Synchronous ogic Interfacing C C C SOW C C C OGIC Synchronized with an external slower clock -Just low EMI External CK

20 20 Synchronous ogic Interfacing C C C C C 0 1 C SEF TIMED OGIC Example: SRAM with Completion Detection

21 21 Sensor node architecture Main components of a WSN node: Microcontroller Memory Radio Sensors / Actuators Power supply Battery (energy storage) Power scavenging Atmel AVR

22 Our Case Study Application independent 8 Bit CPU architecture: Atmel AVR Instruction Set (like MICA2 - MICAZ) from OpenCores.org,, implemented with a 130nm technology Toolchain and lots of software are ready to use nesc, TinyOS, TinyDB,, Surge, Tossim Aggressive Energy management enabled by de-synchronization, using: Dynamic Voltage Scaling zero wake-up time (No CK, no wait for P to restart) 22

23 23 Typical AVR architecture INSTR. Memory DATA Memory Instruction FETCH 0 1 MEM Instruction Access DECODE AU Execution Data Path (8 bit) External CK Address bus Clk distribution

24 24 Design Choices Main target is energy efficiency (vs( speed) arge delay margins (100%) to increase robustness at low voltage supply AVR core is really small (~4500 gates), hence we used a Single controller Reduced area overhead No electro magnetic emission reduction

25 25 De-synchronized AVR INSTR. Memory DATA Memory Instruction FETCH 0 1 MEM Instruction Access DECODE AU Execution C Data Path Address bus Handshake signal distribution Delay chain

26 26 ogic and Delay ine Matching

27 Energy Efficiency Energy per Instruction Power Consumption Async 06 - March eakage per instruction Voltage Supply [V] ogic Delay 27

28 28 Energy Efficiency

29 29 Some Past Work Comparison Philips 80c51 (H. van Gageldonk., 1998) Asynchronous bundled-data data implementation of the 8051 ISA, general purpose. utonium (A. Martin et al., 2003) Asynchronous QDI implementation of the 8051 ISA. Snap/le (V. Ekanayake et al., 2004) Asynchronous QDI processor specifically designed for WSN. Razor (D. Ernst et al., 2004) Synchronous processor that estimated the best Vdd by dynamically monitoring the delay of the logic using a redundant latching schema.

30 30 CONCUSIONS Aggressive Energy management using DVS V (170 MIPS) V ( 48 MIPS) Minimal overhead wrt synchronous counterpart +6% area (due to FF->latch conversion) -20% speed (could be improved by reducing margins) Future work: Analysis with other SPICE-like simulators (Hsim( Hsim) Statistical simulations to check robustness wrt process variability (Monte Carlo) Fabrication (?)