Electronic Devices and Circuit Theory

Transcription

1 Instructor s Resource Manual to accompany Electronic Devices and Circuit Theory Tenth Edition Robert L. Boylestad Louis Nashelsky Upper Saddle River, New Jersey Columbus, Ohio

2 Copyright 2009 by Pearson Education, Inc., Upper Saddle River, New Jersey Pearson Prentice Hall. All rights reserved. Printed in the United States of America. This publication is protected by Copyright and permission should be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or likewise. For information regarding permission(s), write to: Rights and Permissions Department. Pearson Prentice Hall is a trademark of Pearson Education, Inc. Pearson is a registered trademark of Pearson plc Prentice Hall is a registered trademark of Pearson Education, Inc. Instructors of classes using Boylestad/Nashelsky, Electronic Devices and Circuit Theory, 10 th edition, may reproduce material from the instructor s text solutions manual for classroom use ISBN-13: ISBN-10:

3 Contents Solutions to Problems in Text 1 Solutions for Laboratory Manual 185 iii

4 Chapter 1 1. Copper has 20 orbiting electrons with only one electron in the outermost shell. The fact that the outermost shell with its 29 th electron is incomplete (subshell can contain 2 electrons) and distant from the nucleus reveals that this electron is loosely bound to its parent atom. The application of an external electric field of the correct polarity can easily draw this loosely bound electron from its atomic structure for conduction. Both intrinsic silicon and germanium have complete outer shells due to the sharing (covalent bonding) of electrons between atoms. Electrons that are part of a complete shell structure require increased levels of applied attractive forces to be removed from their parent atom. 2. Intrinsic material: an intrinsic semiconductor is one that has been refined to be as pure as physically possible. That is, one with the fewest possible number of impurities. 3. Negative temperature coefficient: materials with negative temperature coefficients have decreasing resistance levels as the temperature increases. Covalent bonding: covalent bonding is the sharing of electrons between neighboring atoms to form complete outermost shells and a more stable lattice structure. 4. W QV (6 C)(3 V) 18 J ev 48( J) J Q W 19 V J C 12 V C is the charge associated with 4 electrons. 6. GaP Gallium Phosphide E g 2.24 ev ZnS Zinc Sulfide E g 3.67 ev 7. An n-type semiconductor material has an excess of electrons for conduction established by doping an intrinsic material with donor atoms having more valence electrons than needed to establish the covalent bonding. The majority carrier is the electron while the minority carrier is the hole. A p-type semiconductor material is formed by doping an intrinsic material with acceptor atoms having an insufficient number of electrons in the valence shell to complete the covalent bonding thereby creating a hole in the covalent structure. The majority carrier is the hole while the minority carrier is the electron. 8. A donor atom has five electrons in its outermost valence shell while an acceptor atom has only 3 electrons in the valence shell. 9. Majority carriers are those carriers of a material that far exceed the number of any other carriers in the material. Minority carriers are those carriers of a material that are less in number than any other carrier of the material. 1

5 10. Same basic appearance as Fig. 1.7 since arsenic also has 5 valence electrons (pentavalent). 11. Same basic appearance as Fig. 1.9 since boron also has 3 valence electrons (trivalent) For forward bias, the positive potential is applied to the p-type material and the negative potential to the n-type material. 15. T K k 11,600/n 11,600/2 (low value of V D ) 5800 (5800)(0.6) kvd TK I D I s e e (e ) ma 16. k 11,600/n 11,600/ (n 2 for V D 0.6 V) T K T C (5800)(0.6 V) kv / T K e e e I I e 5 μa( ) ma / ( kv T K s 1) 17. (a) T K k 11,600/n 11,600/ kvd (5800)( 10 V) T K 293 I D I s e 1 0.1μA e (e ) ( ) μA I D I s 0.1 μa (b) The result is expected since the diode current under reverse-bias conditions should equal the saturation value. 18. (a) x y e x (b) y e 0 1 (c) For V 0 V, e 0 1 and I I s (1 1) 0 ma 2

6 19. T 20 C: I s 0.1 μa T 30 C: I s 2(0.1 μa) 0.2 μa (Doubles every 10 C rise in temperature) T 40 C: I s 2(0.2 μa) 0.4 μa T 50 C: I s 2(0.4 μa) 0.8 μa T 60 C: I s 2(0.8 μa) 1.6 μa 1.6 μa: 0.1 μa 16:1 increase due to rise in temperature of 40 C. 20. For most applications the silicon diode is the device of choice due to its higher temperature capability. Ge typically has a working limit of about 85 degrees centigrade while Si can be used at temperatures approaching 200 degrees centigrade. Silicon diodes also have a higher current handling capability. Germanium diodes are the better device for some RF small signal applications, where the smaller threshold voltage may prove advantageous. 21. From 1.19: V 10 ma I s 75 C 25 C 125 C 1.1 V 0.85 V 0.6 V 0.01 pa 1 pa 1.05 μa V F decreased with increase in temperature 1.1 V: 0.6 V 1.83:1 I s increased with increase in temperature 1.05 μa: 0.01 pa :1 22. An ideal device or system is one that has the characteristics we would prefer to have when using a device or system in a practical application. Usually, however, technology only permits a close replica of the desired characteristics. The ideal characteristics provide an excellent basis for comparison with the actual device characteristics permitting an estimate of how well the device or system will perform. On occasion, the ideal device or system can be assumed to obtain a good estimate of the overall response of the design. When assuming an ideal device or system there is no regard for component or manufacturing tolerances or any variation from device to device of a particular lot. 23. In the forward-bias region the 0 V drop across the diode at any level of current results in a resistance level of zero ohms the on state conduction is established. In the reverse-bias region the zero current level at any reverse-bias voltage assures a very high resistance level the open circuit or off state conduction is interrupted. 24. The most important difference between the characteristics of a diode and a simple switch is that the switch, being mechanical, is capable of conducting current in either direction while the diode only allows charge to flow through the element in one direction (specifically the direction defined by the arrow of the symbol using conventional current flow). 25. V D 0.66 V, I D 2 ma VD 0.65 V R DC 325 Ω I 2 ma D 3

7 26. At I D 15 ma, V D 0.82 V VD 0.82 V R DC Ω I D 15 ma As the forward diode current increases, the static resistance decreases. 27. V D 10 V, I D I s 0.1 μa VD 10 V R DC I D 0.1 μa 100 MΩ V D 30 V, I D I s 0.1 μa VD 30 V R DC 300 MΩ I 0.1μA D As the reverse voltage increases, the reverse resistance increases directly (since the diode leakage current remains constant). 28. (a) r d (b) r d ΔV ΔI d d 0.79 V 0.76 V 0.03 V 15 ma 5 ma 10 ma 26 mv 26 mv 2.6 Ω 10 ma I D 3 Ω (c) quite close 29. I D 10 ma, V D 0.76 V VD 0.76 V R DC 76 Ω I 10 ma r d ΔV ΔI D d d R DC >> r d 0.79 V 0.76 V 0.03 V 15 ma 5 ma 10 ma 3 Ω 30. I D 1 ma, r d I D 15 ma, r d ΔV ΔI d d ΔV ΔI 0.72 V 0.61 V 55 Ω 2 ma 0 ma d d 0.8 V 0.78 V 2 Ω 20 ma 10 ma 26 mv 31. I D 1 ma, r d 2 2(26 Ω) 52 Ω vs 55 Ω (#30) I D 26 mv 26 mv I D 15 ma, r d 1.73 Ω vs 2 Ω (#30) 15 ma I D 32. r av ΔV ΔI d d 0.9 V 0.6 V 24.4 Ω 13.5 ma 1.2 ma 4

8 33. r d ΔV ΔI d d 0.8 V 0.7 V 0.09 V 22.5 Ω 7 ma 3 ma 4 ma (relatively close to average value of 24.4 Ω (#32)) 34. r av ΔV ΔI d d 0.9 V 0.7 V 0.2 V 14 ma 0 ma 14 ma Ω 35. Using the best approximation to the curve beyond V D 0.7 V: ΔVd 0.8 V 0.7 V 0.1 V r av 4 Ω ΔI 25 ma 0 ma 25 ma d 36. (a) V R 25 V: C T 0.75 pf V R 10 V: C T 1.25 pf ΔC ΔV T R 1.25 pf 0.75 pf 0.5 pf 10 V 25 V 15 V pf/v (b) V R 10 V: C T 1.25 pf V R 1 V: C T 3 pf ΔC ΔV T R 1.25 pf 3 pf 1.75 pf 10 V 1 V 9 V pf/v (c) pf/v: pf/v 5.88:1 6:1 Increased sensitivity near V D 0 V 37. From Fig V D 0 V, C D 3.3 pf V D 0.25 V, C D 9 pf 38. The transition capacitance is due to the depletion region acting like a dielectric in the reversebias region, while the diffusion capacitance is determined by the rate of charge injection into the region just outside the depletion boundaries of a forward-biased device. Both capacitances are present in both the reverse- and forward-bias directions, but the transition capacitance is the dominant effect for reverse-biased diodes and the diffusion capacitance is the dominant effect for forward-biased conditions. 5

9 39. V D 0.2 V, C D 7.3 pf 1 1 X C 3.64 kω 2π fc 2 π(6 MHz)(7.3 pf) V D 20 V, C T 0.9 pf 1 1 X C kω 2π fc 2 π(6 MHz)(0.9 pf) 40. I f 10 V 10 kω 1 ma t s + t t t rr 9 ns t s + 2t s 9 ns t s 3 ns t t 2t s 6 ns As the magnitude of the reverse-bias potential increases, the capacitance drops rapidly from a level of about 5 pf with no bias. For reverse-bias potentials in excess of 10 V the capacitance levels off at about 1.5 pf. 43. At V D 25 V, I D 0.2 na and at V D 100 V, I D 0.45 na. Although the change in I R is more than 100%, the level of I R and the resulting change is relatively small for most applications. 44. Log scale: T A 25 C, I R 0.5 na T A 100 C, I R 60 na The change is significant. 60 na: 0.5 na 120:1 Yes, at 95 C I R would increase to 64 na starting with 0.5 na (at 25 C) (and double the level every 10 C). 6

10 45. I F 0.1 ma: r d 700 Ω I F 1.5 ma: r d 70 Ω I F 20 ma: r d 6 Ω The results support the fact that the dynamic or ac resistance decreases rapidly with increasing current levels. 46. T 25 C: P max 500 mw T 100 C: P max 260 mw P max V F I F Pmax 500 mw I F ma V F 0.7 V Pmax 260 mw I F ma V 0.7 V F ma: ma 1.92:1 2:1 47. Using the bottom right graph of Fig. 1.37: I F 500 T 25 C At I F 250 ma, T 104 C 48. ΔVZ 49. T C % 100% VZ ( T1 T0) 0.75 V V( T1 25) T T T T C ΔVZ 100% V ( T T ) Z 1 0 (5 V 4.8 V) 100% 0.053%/ C 5 V( ) 7

11 51. (20 V 6.8 V) 100% 77% (24 V 6.8 V) The 20 V Zener is therefore 77% of the distance between 6.8 V and 24 V measured from the 6.8 V characteristic. At I Z 0.1 ma, T C 0.06%/ C (5 V 3.6 V) 100% 44% (6.8 V 3.6 V) The 5 V Zener is therefore 44% of the distance between 3.6 V and 6.8 V measured from the 3.6 V characteristic. At I Z 0.1 ma, T C 0.025%/ C V Zener: 0.2 ma: 400 Ω 1 ma: 95 Ω 10 ma: 13 Ω The steeper the curve (higher di/dv) the less the dynamic resistance. 54. V T 2.0 V, which is considerably higher than germanium ( 0.3 V) or silicon ( 0.7 V). For germanium it is a 6.7:1 ratio, and for silicon a 2.86:1 ratio. 55. Fig (f) I F 13 ma Fig (e) V F 2.3 V 56. (a) Relative 5 ma 10 ma % 24.4% increase 0.82 ratio: (b) Relative 30 ma 35 ma % 2.9% increase 1.38 ratio: (c) For currents greater than about 30 ma the percent increase is significantly less than for increasing currents of lesser magnitude. 8

12 57. (a) From Fig (i) 75 (b) For the high-efficiency red unit of Fig. 1.53: 0.2 ma 20 ma C x 20 ma x 100 C 0.2 ma/ C 9

13 Chapter 2 1. The load line will intersect at I D E 8 V R 330 Ω ma and V D 8 V. (a) (b) (c) V D Q 0.92 V I D Q 21.5 ma V R E V D Q 8 V 0.92 V 7.08 V V D Q 0.7 V I D Q 22.2 ma V R E V D Q 8 V 0.7 V 7.3 V V D Q 0 V I D Q ma V R E V D Q 8 V 0 V 8 V For (a) and (b), levels of V D Q and I D Q are quite close. Levels of part (c) are reasonably close but as expected due to level of applied voltage E. E 5 V 2. (a) I D R 2.27 ma 2.2 kω The load line extends from I D 2.27 ma to V D 5 V. V 0.7 V, I 2 ma D Q D Q E 5 V (b) I D R ma 0.47 kω The load line extends from I D ma to V D 5 V. V 0.8 V, I 9 ma D Q D Q E 5 V (c) I D R ma 0.18 kω The load line extends from I D ma to V D 5 V. V 0.93 V, I 22.5 ma D Q D Q The resulting values of 3. Load line through ma. I D ma with R V D Q are quite close, while I D Q extends from 2 ma to 22.5 ma. I D Q 10 ma of characteristics and V D 7 V will intersect I D axis as E 7 V R R 7 V ma 0.62 kω 10

14 E V 30 V 0.7 V 4. (a) I D I R D ma R 2.2 kω V D 0.7 V, V R E V D 30 V 0.7 V 29.3 V E V 30 V 0 V (b) I D D R 2.2 kω V D 0 V, V R 30 V ma Yes, since E V T the levels of I D and V R are quite close. 5. (a) I 0 ma; diode reverse-biased. (b) V 20Ω 20 V 0.7 V 19.3 V (Kirchhoff s voltage law) I 19.3 V 20 Ω A (c) I 10 V 1 A; center branch open 10 Ω 6. (a) Diode forward-biased, Kirchhoff s voltage law (CW): 5 V V V o 0 V o 4.3 V V 4.3 V I R I D o R ma 2.2 kω (b) Diode forward-biased, 8 V 0.7 V I D 1.24 ma 1.2 kω+ 4.7 kω V o V 4.7 kω + V D (1.24 ma)(4.7 kω) V 6.53 V 7. (a) V o 2 k Ω(20 V 0.7 V 0.3V) 2 kω+ 2 kω 1 2 (20 V 1 V) 1 (19 V) 9.5 V 2 10 V + 2V 0.7 V) 11.3 V (b) I ma 1.2 kω+ 4.7 kω 5.9 kω V IR (1.915 ma)(4.7 kω) 9 V V o V 2 V 9 V 2 V 7 V 11

15 8. (a) Determine the Thevenin equivalent circuit for the 10 ma source and 2.2 kω resistor. E Th IR (10 ma)(2.2 kω) 22 V R Th 2. 2kΩ (b) Diode forward-biased I D 20 V + 5 V 0.7 V 2.65 ma 6.8 kω Kirchhoff s voltage law (CW): +V o 0.7 V + 5 V 0 V o 4.3 V Diode forward-biased 22 V 0.7 V I D 6.26 ma 2.2 kω kω V o I D (1.2 kω) (6.26 ma)(1.2 kω) 7.51 V 9. (a) (b) I V o 1 12 V 0.7 V 11.3 V V o V V o 1 10 V V V 9 V 10 V 0.7 V 0.3 V 9 V 1.2 kω+ 3.3 kω 4.5 kω 2 ma, V o (2 ma)(3.3 kω) 6.6 V (a) Both diodes forward-biased I R 20 V 0.7 V ma 4.7 kω Assuming identical diodes: I ma I D R 2.05 ma 2 2 V o 20 V 0.7 V 19.3 V (b) Right diode forward-biased: I D 15 V + 5 V 0.7 V 8.77 ma 2.2 kω V o 15 V 0.7 V 14.3 V 11. (a) Ge diode on preventing Si diode from turning on : 10 V 0.3 V 9.7 V I 9.7 ma 1 kω 1 kω 16 V 0.7 V 0.7 V 12 V 2.6 V (b) I ma 4.7 kω 4.7 kω V o 12 V + (0.553 ma)(4.7 kω) 14.6 V 12

16 12. Both diodes forward-biased: V 0.7 V, V 0.3 V o 1 o 2 20 V 0.7 V I 1 kω 19.3 V 19.3 ma 1 kω 1 kω I 0.47 kω 0.7 V 0.3 V ma 0.47 kω I(Si diode) I 1 kω I 0.47 kω 19.3 ma ma ma 13. For the parallel Si 2 kω branches a Thevenin equivalent will result (for on diodes) in a single series branch of 0.7 V and 1 kω resistor as shown below: I 2 kω 6.2 V 3.1 ma 2 kω I2 k 3.1 ma I D Ω 1.55 ma Both diodes off. The threshold voltage of 0.7 V is unavailable for either diode. V o 0 V 15. Both diodes on, V o 10 V 0.7 V 9.3 V 16. Both diodes on. V o 0.7 V 17. Both diodes off, V o 10 V 18. The Si diode with 5 V at the cathode is on while the other is off. The result is V o 5 V V 4.3 V V at one terminal is more positive than 5 V at the other input terminal. Therefore assume lower diode on and upper diode off. The result: V o 0 V 0.7 V 0.7 V The result supports the above assumptions. 20. Since all the system terminals are at 10 V the required difference of 0.7 V across either diode cannot be established. Therefore, both diodes are off and V o +10 V as established by 10 V supply connected to 1 kω resistor. 13

17 21. The Si diode requires more terminal voltage than the Ge diode to turn on. Therefore, with 5 V at both input terminals, assume Si diode off and Ge diode on. The result: V o 5 V 0.3 V 4.7 V The result supports the above assumptions. Vdc 2 V 22. V dc V m V m 6.28 V I m V m 6.28 V R 2.2 kω 2.85 ma 23. Using V dc 0.318(V m V T ) 2 V 0.318(V m 0.7 V) Solving: V m 6.98 V 10:1 for V m :V T Vdc 2 V 24. V m 6.28 V I L max 6.28 V 6.8 kω ma 14

18 I max (2.2 kω) 6.28 V ma 2.2 kω I I + I max (2.2 kω) ma ma 3.78 ma Dmax Lmax 25. V m 2 (110 V) V V dc 0.318V m 0.318( V) V 26. Diode will conduct when v o 0.7 V; that is, 10 k Ω( v ) v o 0.7 V i 10 kω+ 1 kω Solving: v i 0.77 V For v i 0.77 V Si diode is on and v o 0.7 V. For v i < 0.77 V Si diode is open and level of v o is determined by voltage divider rule: 10 k Ω( v ) v o i 10 kω+ 1 kω v i For v i 10 V: v o 0.909( 10 V) 9.09 V When v o 0.7 V, vr v max i 0.7 V max 10 V 0.7 V 9.3 V 9.3 V I R 9.3 ma max 1 kω 10 V I max (reverse) ma 1 kω+ 10 kω 15

19 27. (a) P max 14 mw (0.7 V)I D 14 mw I D 20 ma 0.7 V (b) 4.7 kω 56 kω 4.34 kω V R 160 V 0.7 V V I max V ma 4.34 kω Imax ma (c) I diode ma 2 2 (d) Yes, I D 20 ma > ma (e) I diode ma I max 20 ma 28. (a) V m 2 (120 V) V V L m V i m 2V D V 2(0.7 V) V 1.4 V V V dc 0.636(168.3 V) V (b) PIV V m (load) + V D V V 169 V (c) I D (max) VL m V R 1 kω L ma (d) P max V D I D (0.7 V)I max (0.7 V)(168.3 ma) mw

20 30. Positive half-cycle of v i : Voltage-divider rule: 2.2 k Ω( V i ) max V o max 2.2 kω+ 2.2 kω 1 ( V imax ) 2 1 (100 V) 2 50 V 31. Positive pulse of v i : Top left diode off, bottom left diode on 2.2 kω 2.2 kω 1.1 kω 1.1 k Ω(170 V) V o peak 1.1 kω kω V Negative pulse of v i : Top left diode on, bottom left diode off 1.1 k Ω(170 V) V o peak 1.1 kω kω V V dc 0.636(56.67 V) V V dc 0.636V m (50 V) 31.8 V 32. (a) Si diode open for positive pulse of v i and v o 0 V For 20 V < v i 0.7 V diode on and v o v i V. For v i 20 V, v o 20 V V 19.3 V For v i 0.7 V, v o 0.7 V V 0 V Polarity of v o across the 2.2 kω resistor acting as a load is the same. Voltage-divider rule: 2.2 k Ω( V i ) max V o max 2.2 kω+ 2.2 kω 1 ( V imax ) 2 1 (100 V) 2 50 V 17

21 (b) For v i 5 V the 5 V battery will ensure the diode is forward-biased and v o v i 5 V. At v i 5 V v o 5 V 5 V 0 V At v i 20 V v o 20 V 5 V 25 V For v i > 5 V the diode is reverse-biased and v o 0 V. 33. (a) Positive pulse of v i : 1.2 k Ω(10 V 0.7 V) V o 1.2 kω+ 2.2 kω Negative pulse of v i : diode open, v o 0 V 3.28 V (b) Positive pulse of v i : V o 10 V 0.7 V + 5 V 14.3 V Negative pulse of v i : diode open, v o 0 V 34. (a) For v i 20 V the diode is reverse-biased and v o 0 V. For v i 5 V, v i overpowers the 2 V battery and the diode is on. Applying Kirchhoff s voltage law in the clockwise direction: 5 V + 2 V v o 0 v o 3 V (b) For v i 20 V the 20 V level overpowers the 5 V supply and the diode is on. Using the short-circuit equivalent for the diode we find v o v i 20 V. For v i 5 V, both v i and the 5 V supply reverse-bias the diode and separate v i from v o. However, v o is connected directly through the 2.2 kω resistor to the 5 V supply and v o 5 V. 18

22 35. (a) Diode on for v i 4.7 V For v i > 4.7 V, V o 4 V V 4.7 V For v i < 4.7 V, diode off and v o v i (b) Again, diode on for v i 4.7 V but v o now defined as the voltage across the diode For v i 4.7 V, v o 0.7 V For v i < 4.7 V, diode off, I D I R 0 ma and V 2.2 kω IR (0 ma)r 0 V Therefore, v o v i 4 V At v i 0 V, v o 4 V v i 8 V, v o 8 V 4 V 12 V 36. For the positive region of v i : The right Si diode is reverse-biased. The left Si diode is on for levels of v i greater than 5.3 V V 6 V. In fact, v o 6 V for v i 6 V. For v i < 6 V both diodes are reverse-biased and v o v i. For the negative region of v i : The left Si diode is reverse-biased. The right Si diode is on for levels of v i more negative than 7.3 V V 8 V. In fact, v o 8 V for v i 8 V. For v i > 8 V both diodes are reverse-biased and v o v i. i R : For 8 V < v i < 6 V there is no conduction through the 10 kω resistor due to the lack of a complete circuit. Therefore, i R 0 ma. For v i 6 V v R v i v o v i 6 V For v i 10 V, v R 10 V 6 V 4 V and i R 4 V 10 kω 0.4 ma For v i 8 V v R v i v o v i + 8 V 19

23 For v i 10 V v R 10 V + 8 V 2 V 2V and i R 0.2 ma 10 kω 37. (a) Starting with v i 20 V, the diode is in the on state and the capacitor quickly charges to 20 V+. During this interval of time v o is across the on diode (short-current equivalent) and v o 0 V. When v i switches to the +20 V level the diode enters the off state (open-circuit equivalent) and v o v i + v C 20 V + 20 V +40 V (b) Starting with v i 20 V, the diode is in the on state and the capacitor quickly charges up to 15 V+. Note that v i +20 V and the 5 V supply are additive across the capacitor. During this time interval v o is across on diode and 5 V supply and v o 5 V. When v i switches to the +20 V level the diode enters the off state and v o v i + v C 20 V + 15 V 35 V. 20

24 38. (a) For negative half cycle capacitor charges to peak value of 120 V 0.7 V V with polarity. The output v o is directly across the on diode resulting in v o 0.7 V as a negative peak value. For next positive half cycle v o v i V with peak value of v o 120 V V V. (b) For positive half cycle capacitor charges to peak value of 120 V 20 V 0.7 V 99.3 V with polarity. The output v o 20 V V 20.7 V For next negative half cycle v o v i 99.3 V with negative peak value of v o 120 V 99.3 V V. Using the ideal diode approximation the vertical shift of part (a) would be 120 V rather than V and 100 V rather than 99.3 V for part (b). Using the ideal diode approximation would certainly be appropriate in this case. 39. (a) τ RC (56 kω)(0.1 μf) 5.6 ms 5τ 28 ms (b) 5τ 28 ms 2 T 1 ms ms, 56:1 (c) Positive pulse of v i : Diode on and v o 2 V V 1.3 V Capacitor charges to 10 V + 2 V 0.7 V 11.3 V Negative pulse of v i : Diode off and v o 10 V 11.3 V 21.3 V 21

25 40. Solution is network of Fig (b) using a 10 V supply in place of the 5 V source. 41. Network of Fig with 2 V battery reversed. 42. (a) In the absence of the Zener diode 180 Ω(20 V) V L 180 Ω+ 220 Ω 9 V V L 9 V < V Z 10 V and diode non-conducting 20 V Therefore, I L I R 220 Ω+ 180 Ω with I Z 0 ma and V L 9 V 50 ma (b) In the absence of the Zener diode 470 Ω(20 V) V L 470 Ω+ 220 Ω V V L V > V Z 10 V and Zener diode on Therefore, V L 10 V and V R s 10 V I V / R 10 V/220 Ω ma Rs Rs s I L V L /R L 10 V/470 Ω ma and I Z I I L ma ma ma R s (c) P Z max 400 mw V Z I Z (10 V)(I Z ) 400 mw I Z 40 ma 10 V I L min IR I s Z ma 40 ma 5.45 ma max VL 10 V R L 1, Ω I 5.45 ma Lmin Large R L reduces I L and forces more of I R s to pass through Zener diode. (d) In the absence of the Zener diode RL (20 V) V L 10 V R L Ω 10R L R L 10R L 2200 R L 220 Ω 22

26 VL 12 V 43. (a) V Z 12 V, R L 60 Ω I L 200 ma RV L i 60 Ω(16 V) V L V Z 12 V RL + Rs 60 Ω+ Rs R s R s 240 R s 20 Ω (b) P Z max V Z I Zmax (12 V)(200 ma) 2.4 W VL VZ 44. Since I L is fixed in magnitude the maximum value of RL RL maximum. The maximum level of of V i. PZ 400 mw max IZ 50 ma max VZ 8 V VL VZ 8 V I L ma RL RL 220 Ω I R s I Z + I L 50 ma ma ma Vi VZ I R s Rs or V i IR R s s + V Z (86.36 ma)(91 Ω) + 8 V 7.86 V + 8 V V I R s will occur when I Z is a I R s will in turn determine the maximum permissible level Any value of v i that exceeds V will result in a current I Z that will exceed the maximum value. 45. At 30 V we have to be sure Zener diode is on. RV L i 1 k Ω(30 V) V L 20 V RL + Rs 1 kω+ Rs Solving, R s 0.5 kω At 50 V, I ZM I RS 50 V 20 V 0.5 kω 60 ma, I L 20 V 1 kω I R S I L 60 ma 20 ma 40 ma 20 ma 46. For v i +50 V: Z 1 forward-biased at 0.7 V Z 2 reverse-biased at the Zener potential and V Z 2 10 V. Therefore, V o V + V 0.7 V + 10 V 10.7 V Z1 Z2 23

27 For v i 50 V: Z 1 reverse-biased at the Zener potential and V Z 1 10 V. Z 2 forward-biased at 0.7 V. Therefore, V o V + V 10.7 V Z1 Z2 For a 5 V square wave neither Zener diode will reach its Zener potential. In fact, for either polarity of v i one Zener diode will be in an open-circuit state resulting in v o v i. 47. V m 1.414(120 V) V 2V m 2( V) V 48. The PIV for each diode is 2V m PIV 2(1.414)(V rms ) 24

28 Chapter A bipolar transistor utilizes holes and electrons in the injection or charge flow process, while unipolar devices utilize either electrons or holes, but not both, in the charge flow process. 3. Forward- and reverse-biased. 4. The leakage current I CO is the minority carrier current in the collector I E the largest I B the smallest I C I E 1 9. I B 100 I I C C 100I B I E I C + I B 100I B + I B 101I B I 8 ma I B E μa I C 100I B 100(79.21 μa) ma I E 5 ma, V CB 1 V: V BE 800 mv V CB 10 V: V BE 770 mv V CB 20 V: V BE 750 mv The change in V CB is 20 V:1 V 20:1 The resulting change in V BE is 800 mv:750 mv 1.07:1 (very slight) ΔV 0.9 V 0.7 V 12. (a) r av 25 Ω ΔI 8 ma 0 (b) Yes, since 25 Ω is often negligible compared to the other resistance levels of the network. 13. (a) I C I E 4.5 ma (b) I C I E 4.5 ma (c) negligible: change cannot be detected on this set of characteristics. (d) I C I E 25

29 14. (a) Using Fig. 3.7 first, I E 7 ma Then Fig. 3.8 results in I C 7 ma (b) Using Fig. 3.8 first, I E 5 ma Then Fig. 3.7 results in V BE 0.78 V (c) Using Fig. 3.10(b) I E 5 ma results in V BE 0.81 V (d) Using Fig. 3.10(c) I E 5 ma results in V BE 0.7 V (e) Yes, the difference in levels of V BE can be ignored for most applications if voltages of several volts are present in the network. 15. (a) I C α I E (0.998)(4 ma) ma 16. (b) I E I C + I B I C I E I B 2.8 ma 0.02 ma 2.78 ma IC 2.78 ma α dc I 2.8 ma E α 0.98 (c) I C βi B I B (40 μa) 1.96 ma 1 α I 1.96 ma I E C α ma 17. I i V i /R i 500 mv/20 Ω 25 ma I L I i 25 ma V L I L R L (25 ma)(1 kω) 25 V Vo 25 V A v V 0.5 V 50 i Vi 200 mv 200 mv 18. I i Ri + R s 20 Ω+ 100 Ω 120 Ω I L I i 1.67 ma V L I L R (1.67 ma)(5 kω) 8.35 V Vo 8.35 V A v V 0.2 V i 1.67 ma (a) Fig. 3.14(b): I B 35μA Fig. 3.14(a): I C 3.6 ma (b) Fig. 3.14(a): V CE 2.5 V Fig. 3.14(b): V BE 0.72 V 26

30 IC 2 ma 21. (a) β I B 17 μa β (b) α β (c) I CEO 0.3 ma (d) I CBO (1 α)i CEO ( )(0.3 ma) 2.4 μa 22. (a) Fig. 3.14(a): I CEO 0.3 ma (b) Fig. 3.14(a): I C 1.35 ma IC 1.35 ma β dc I 10 μa 135 B (c) α β 135 β I CBO (1 α)i CEO ( )(0.3 ma) 2.2 μa IC 6.7 ma 23. (a) β dc I B 80 μa IC 0.85 ma (b) β dc 170 I B 5 μa IC 3.4 ma (c) β dc I B 30 μa (d) β dc does change from pt. to pt. on the characteristics. Low I B, high V CE higher betas High I B, low V CE lower betas 24. (a) β ac (b) β ac ΔI ΔI ΔI ΔI C B C B V V CE CE 5 V 7.3 ma 6 ma 1.3 ma μa 70 μa 20 μa 1.4 ma 0.3 ma 1.1 ma V 10 μa 0 μa 10 μa ΔIC 4.25 ma 2.35 ma 1.9 ma (c) β ac 95 ΔI B VCE 10 V 40 μa 20 μa 20 μa (d) β ac does change from point to point on the characteristics. The highest value was obtained at a higher level of V CE and lower level of I C. The separation between I B curves is the greatest in this region. 27

31 (e) V CE I B β dc β ac I C β dc /β ac 5 V 80 μa ma V 30 μa ma V 5 μa ma 1.55 As I C decreased, the level of β dc and β ac increased. Note that the level of β dc and β ac in the center of the active region is close to the average value of the levels obtained. In each case β dc is larger than β ac, with the least difference occurring in the center of the active region. IC 2.9 ma 25. β dc 116 I B 25 μa β 116 α β I E I C /α 2.9 ma/ ma α (a) β 1 α β (b) α β I 2 ma (c) I B C μa β 180 I E I C + I B 2 ma μa ma V e V i V be 2 V 0.1 V 1.9 V Vo 1.9 V A v V i 2 V VE 1.9 V I e R 1.9 ma (rms) 1 kω E 29. Output characteristics: Curves are essentially the same with new scales as shown. Input characteristics: Common-emitter input characteristics may be used directly for common-collector calculations. 28

32 30. P C max 30 mw V CE I C PC 30 mw max I C I C max, V CE IC 7 ma 4.29 V max PC 30 mw max V CE V CE max, I C 1.5 ma VCE 20 V max PC 30 mw max V CE 10 V, I C 3 ma VCE 10 V PC 30 mw max I C 4 ma, V CE IC 4 ma 7.5 V PC 30 mw max V CE 15 V, I C 2 ma V 15 V CE 31. I C PC max I C max, V CE I Cmax PC max V CB V CB max, I C V CBmax 30 mw 5 V 6 ma 30 mw 2 ma 15 V PC 30 mw max I C 4 ma, V CB 7.5 V I 4 ma C PC 30 mw max V CB 10 V, I C 3 ma V 10 V CB 29

33 32. The operating temperature range is 55 C T J 150 C F 9 C ( 55 C) F 5 F 9 (150 C) F 5 67 F T J 302 F 33. I C max 200 ma, V CE max 30 V, P P D max 625 mw D 625 mw max I C I C max, V CE IC 200 ma V max PD 625 mw max V CE V CE max, I C ma VCE 30 V max PD 625 mw max I C 100 ma, V CE 6.25 V IC 100 ma PD 625 mw max V CE 20 V, I C ma V 20 V CE 34. From Fig (a) I CBO 50 na max βmin + βmax β avg I CEO βi CBO (100)(50 na) 5 μa 30

34 35. h FE (β dc ) with V CE 1 V, T 25 C I C 0.1 ma, h FE 0.43(100) 43 I C 10 ma, h FE 0.98(100) 98 h fe (β ac ) with V CE 10 V, T 25 C I C 0.1 ma, h fe 72 I C 10 ma, h fe 160 For both h FE and h fe the same increase in collector current resulted in a similar increase (relatively speaking) in the gain parameter. The levels are higher for h fe but note that V CE is higher also. 36. As the reverse-bias potential increases in magnitude the input capacitance C ibo decreases (Fig. 3.23(b)). Increasing reverse-bias potentials causes the width of the depletion region to A increase, thereby reducing the capacitance C d. 37. (a) At I C 1 ma, h fe 120 At I C 10 ma, h fe 160 (b) The results confirm the conclusions of problems 23 and 24 that beta tends to increase with increasing collector current. 39. (a) β ac ΔI ΔI C B V CE 3 V 16 ma 12.2 ma 3.8 ma 80 μa 60 μa 20 μa 190 (b) β dc I I C B 12 ma μa (c) β ac 4 ma 2 ma 2 ma 18 μa 8 μa 10 μa 200 (d) β dc I I C B 3 ma μa (e) In both cases β dc is slightly higher than β ac ( 10%) (f)(g) In general β dc and β ac increase with increasing I C for fixed V CE and both decrease for decreasing levels of V CE for a fixed I E. However, if I C increases while V CE decreases when moving between two points on the characteristics, chances are the level of β dc or β ac may not change significantly. In other words, the expected increase due to an increase in collector current may be offset by a decrease in V CE. The above data reveals that this is a strong possibility since the levels of β are relatively close. 31

35 Chapter 4 1. (a) I BQ VCC VBE 16 V 0.7 V 15.3 V R 470 kω 470 kω B μa (b) I CQ β I (90)(32.55 μa) 2.93 ma BQ (c) V V I R 16 V (2.93 ma)(2.7 kω) 8.09 V CEQ CC CQ C (d) V C V CE Q 8.09 V (e) V B V BE 0.7 V (f) V E 0 V 2. (a) I C βi B 80(40 μa) 3.2 ma (b) R C (c) R B VR V 12 V 6 V 6 V C CC VC kω I I 3.2 ma 3.2 ma C C VR B 12 V 0.7 V 11.3 V kω I 40 μa 40 μa B (d) V CE V C 6 V 3. (a) I C I E I B 4 ma 20 μa 3.98 ma 4 ma (b) V CC V CE + I C R C 7.2 V + (3.98 ma)(2.2 kω) V 16 V (c) β I I C B 3.98 ma μa (d) R B VR V V 0.7 V B CC VBE 763 kω I I 20 μa B B 4. I C sat VCC 16 V R 2.7 kω C 5.93 ma 5. (a) Load line intersects vertical axis at I C 21 V 3 kω 7 ma and horizontal axis at V CE 21 V. VCC VBE 21 V 0.7 V (b) I B 25 μa: R B 812 kω I 25 μa B (c) I C Q 3.4 ma, V CE Q V 32

36 (d) β I I C B 3.4 ma μa (e) α β β (f) I C sat VCC 21 V R 3 kω 7 ma C (g) (h) P D V I (10.75 V)(3.4 ma) mw CEQ CQ (i) (j) 6. (a) P s V CC (I C + I B ) 21 V(3.4 ma + 25 μa) mw P R P s P D mw mw mw I BQ VCC VBE 20 V 0.7 V R + ( β + 1) R 510 k Ω+ (101)1.5 kω 19.3 V kω B μa E (b) I CQ β I (100)(29.18 μa) 2.92 ma BQ (c) V CE Q V CC I C (R C + R E ) 20 V (2.92 ma)(2.4 kω kω) 20 V V 8.61 V (d) V C V CC I C R C 20 V (2.92 ma)(2.4 kω) 20 V V 13 V (e) V B V CC I B R B 20 V (29.18 μa)(510 kω) 20 V V 5.12 V (f) V E V C V CE 13 V 8.61 V 4.39 V 7. (a) R C V CC V I C C 12 V 7.6 V 4.4 V 2.2 kω 2 ma 2 ma (b) I E I C : R E V I E E 2.4 V 1.2 kω 2 ma (c) R B VR V 12 V 0.7 V 2.4 V 8.9 V B CC VBE VE 356 kω I I 2 ma/80 25 μa B B (d) V CE V C V E 7.6 V 2.4 V 5.2 V (e) V B V BE + V E 0.7 V V 3.1 V 33

37 VE 2.1 V 8. (a) I C I E R 3.09 ma E 0.68 kω IC 3.09 ma β I B 20 μa (b) V CC V R C + V CE + V E (3.09 ma)(2.7 kω) V V 8.34 V V V V VR V V 0.7 V 2.1 V B CC VBE VE (c) R B I I 20 μa B V 20 A μ B 747 kω 9. I Csot VCC 20 V 20 V R + R 2.4 kω+ 1.5 kω 3.9 kω C E 5.13 ma 10. (a) VCC 24 V I C sat 6.8 ma RC + RE RC kω 24 V R C kω kω 6.8 ma R C 2.33 kω (b) β I I C B 4 ma μa VR V 24 V 0.7 V (4 ma)(1.2 k ) B CC VBE VE Ω (c) R B I I 30 μa B 18.5 V 30 A μ B kω (d) P D VCE I Q CQ (10 V)(4 ma) 40 mw 2 (e) P ICR C (4 ma) 2 (2.33 kω) mw 11. (a) Problem 1: I C Q 2.93 ma, V CE Q 8.09 V (b) I B Q μa (the same) IC β I Q B (135)(32.55 μa) 4.39 ma Q V V I R 16 V (4.39 ma)(2.7 kω) 4.15 V CEQ CC CQ C 34

38 4.39 ma 2.93 ma (c) %ΔI C 100% 49.83% 2.93 ma %ΔV CE 4.15 V 8.09 V 100% 48.70% 8.09 V Less than 50% due to level of accuracy carried through calculations. (d) Problem 6: I C Q 2.92 ma, V 8.61 V ( I μa) CE Q (e) VCC VBE 20 V 0.7 V I B Q RB + ( β + 1) RE 510 k Ω+ ( )(1.5 k Ω ) μa IC β I Q B (150)(26.21 μa) 3.93 ma Q V CE Q V CC I C (R C + R E ) 20 V (3.93 ma)(2.4 kω kω) 4.67 V 3.93 ma 2.92 ma (f) %ΔI C 2.92 ma 100% 34.59% %ΔV CE 4.67 V 8.61 V 8.61 V 100% 46.76% (g) For both I C and V CE the % change is less for the emitter-stabilized.? 12. βr E 10R 2 (80)(0.68 kω) 10(9.1 kω) 54.4 kω 91 kω (No!) (a) Use exact approach: R Th R 1 R 2 62 kω 9.1 kω 7.94 kω RV 2 E Th CC (9.1 k Ω)(16 V) R2 + R1 9.1 kω+ 62 kω 2.05 V ETh VBE 2.05 V 0.7 V I B Q RTh + ( β + 1) RE 7.94 k Ω+ (81)(0.68 k Ω) μa (b) I β I (80)(21.42 μa) 1.71 ma CQ BQ B Q (c) V CE Q V CC I C Q (R C + R E ) 16 V (1.71 ma)(3.9 kω kω) 8.17 V (d) V C V CC I C R C 16 V (1.71 ma)(3.9 kω) 9.33 V (e) V E I E R E I C R E (1.71 ma)(0.68 kω) 1.16 V (f) V B V E + V BE 1.16 V V 1.86 V 35

39 13. (a) I C V CC V R C C 18 V 12 V 4.7 kω 1.28 ma (b) V E I E R E I C R E (1.28 ma)(1.2 kω) 1.54 V (c) V B V BE + V E 0.7 V V 2.24 V VR 1 (d) R 1 : VR 1 R 1 I R1 I R1 R1 V V CC V B 18 V 2.24 V V I R 1 I R V 0.4 ma VB 2.24 V 0.4 ma R 5.6 kω kω 14. (a) I C βi B (100)(20 μa) 2 ma (b) I E I C + I B 2 ma + 20 μa 2.02 ma V E I E R E (2.02 ma)(1.2 kω) 2.42 V (c) V CC V C + I C R C 10.6 V + (2 ma)(2.7 kω) 10.6 V V 16 V (d) V CE V C V E 10.6 V 2.42 V 8.18 V (e) V B V E + V BE 2.42 V V 3.12 V (f) I I + I R1 R2 B 3.12 V 8.2 kω VCC VB R 1 I R μa μa + 20 μa μa 16 V 3.12 V kω μa 15. I C sat VCC 16 V R + R 3.9 kω kω 16 V 3.49 ma 4.58 kω C E 36

40 16. (a) βr E 10R 2 (120)(1 kω) 10(8.2 kω) 120 kω 82 kω (checks) RV 2 V B CC (8.2 k Ω)(18 V) R1 + R2 39 kω+ 8.2 kω 3.13 V V E V B V BE 3.13 V 0.7 V 2.43 V VE 2.43 V I C I E R 2.43 ma 1 kω E (b) V CE V CC I C (R C + R E ) 18 V (2.43 ma)(3.3 kω + 1 kω) 7.55 V (c) I B I C 2.43 ma β μa (d) V E I E R E I C R E (2.43 ma)(1 kω) 2.43 V (e) V B 3.13 V 17. (a) R Th R 1 R 2 39 kω 8.2 kω 6.78 kω RV C CC 8.2 k Ω(18 V) E Th R1 + R2 39 kω+ 8.2 kω 3.13 V ETh VBE 3.13 V 0.7 V I B R + ( β + 1) R 6.78 k Ω+ (121)(1 k Ω) Th E 2.43 V μa kω I C βi B (120)(19.02 μa) 2.28 ma (vs ma #16) (b) V CE V CC I C (R C + R E ) 18 V (2.28 ma)(3.3 kω + 1 kω) 18 V 9.8 V 8.2 V (vs V #16) (c) μa (vs μa #16) (d) V E I E R E I C R E (2.28 ma)(1 kω) 2.28 V (vs V #16) (e) V B V BE + V E 0.7 V V 2.98 V (vs V #16) The results suggest that the approximate approach is valid if Eq is satisfied. R2 9.1 k Ω(16 V) 18. (a) V B VCC R1 + R2 62 kω+ 9.1 kω 2.05 V V E V B V BE 2.05 V 0.7 V 1.35 V VE 1.35 V I E R 1.99 ma E 0.68 kω I I E 1.99 ma C Q 37

41 V CE Q V CC I C (R C + R E ) 16 V (1.99 ma)(3.9 kω kω) 16 V 9.11 V 6.89 V I B Q I CQ 1.99 ma μa β 80 (b) From Problem 12: I 1.71 ma, V 8.17 V, C Q CE Q I B Q μa (c) The differences of about 14% suggest that the exact approach should be employed when appropriate. 19. (a) I Csat VCC 24 V 24 V 7.5 ma RC + RE 3RE + RE 4RE 24 V 24 V R E 0.8 kω 4(7.5 ma) 30 ma R C 3R E 3(0.8 kω) 2.4 kω (b) V E I E R E I C R E (5 ma)(0.8 kω) 4 V (c) V B V E + V BE 4 V V 4.7 V RV 2 (d) V B CC R2 (24 V), 4.7 V R + R R + 24 kω (e) β dc I I 2 1 C B R kω 5 ma 38.5 μa (f) βr E 10R 2 (129.8)(0.8 kω) 10(5.84 kω) kω 58.4 kω (checks) 20. (a) From problem 12b, I C 1.71 ma From problem 12c, V CE 8.17 V (b) β changed to 120: From problem 12a, E Th 2.05 V, R Th 7.94 kω ETh VBE 2.05 V 0.7 V I B RTh + ( β + 1) RE 7.94 k Ω + (121)(0.68 k Ω) μa I C βi B (120)(14.96 μa) 1.8 ma V CE V CC I C (R C + R E ) 16 V (1.8 ma)(3.9 kω kω) 7.76 V 38

42 (c) 1.8 ma 1.71 ma % Δ I C 100% 5.26% 1.71 ma 7.76 V 8.17 V % Δ V CE 100% 5.02% 8.17 V (d) 11c 11f 20c %ΔI C 49.83% 34.59% 5.26% %ΔV CE 48.70% 46.76% 5.02% Fixed-bias Emitter feedback Voltagedivider (e) Quite obviously, the voltage-divider configuration is the least sensitive to changes in β. 21. I.(a) Problem 16: Approximation approach: Problem 17: Exact analysis: I C Q 2.28 ma, I C Q 2.43 ma, V CE Q 7.55 V V CE Q 8.2 V The exact solution will be employed to demonstrate the effect of the change of β. Using the approximate approach would result in %ΔI C 0% and %ΔV CE 0%. (b) Problem 17: E Th 3.13 V, R Th 6.78 kω ETH VBE 3.13 V 0.7 V 2.43 V I B R + ( β + 1) R 6.78 k Ω+ ( )1 kω kω Th E μa I C βi B (180)(12.94 μa) 2.33 ma V CE V CC I C (R C + R E ) 18 V (2.33 ma)(3.3 kω + 1 kω) 7.98 V 2.33 ma 2.28 ma (c) %ΔI C 100% 2.19% 2.28 ma %ΔV CE 7.98 V 8.2 V 100% 2.68% 8.2 V For situations where βr E > 10R 2 the change in I C and/or V CE due to significant change in β will be relatively small. (d) %ΔI C 2.19% vs % for problem 11. %ΔV CE 2.68% vs % for problem 11. (e) Voltage-divider configuration considerably less sensitive. II. The resulting %ΔI C and %ΔV CE will be quite small. 39

43 VCC VBE 16 V 0.7 V 22. (a) I B RB + β ( RC + RE) 470 k Ω + (120)(3.6 kω k Ω) μa (b) I C βi B (120)(15.88 μa) 1.91 ma (c) V C V CC I C R C 16 V (1.91 ma)(3.6 kω) 9.12 V 23. (a) I B VCC VBE 30 V 0.7 V R + β ( R + R ) 6.90 kω+ 100(6.2 kω+ 1.5 k Ω ) B C E μa I C βi B (100)(20.07 μa) 2.01 ma (b) V C V CC I C R C 30 V (2.01 ma)(6.2 kω) 30 V V V (c) V E I E R E I C R E (2.01 ma)(1.5 kω) 3.02 V (d) V CE V CC I C (R C + R E ) 30 V (2.01 ma)(6.2 kω kω) V VCC VBE 22 V 0.7 V 24. (a) I B RB + β ( RC + RE) 470 k Ω+ (90)(9.1 kω+ 9.1 k Ω) μa I C βi B (90)(10.09 μa) 0.91 ma V CE V CC I C (R C + R E ) 22 V (0.91 ma)(9.1 kω kω) 5.44 V VCC VBE 22 V 0.7 V (b) β 135, I B RB + β ( RC + RE) 470 k Ω+ (135)(9.1 kω+ 9.1 k Ω) 7.28 μa I C βi B (135)(7.28 μa) ma V CE V CC I C (R C + R E ) 22 V (0.983 ma)(9.1 kω kω) 4.11 V (c) ma 0.91 ma % Δ I C 100% 8.02% 0.91 ma 4.11 V 5.44 V % Δ V CE 100% 24.45% 5.44 V (d) The results for the collector feedback configuration are closer to the voltage-divider configuration than to the other two. However, the voltage-divider configuration continues to have the least sensitivities to change in β. 40

44 25. 1 MΩ 0 Ω, R B 150 kω VCC VBE 12 V 0.7 V I B RB + β ( RC + RE) 150 k Ω+ (180)(4.7 kω+ 3.3 k Ω) 7.11 μa I C βi B (180)(7.11 μa) 1.28 ma V C V CC I C R C 12 V (1.28 ma)(4.7 kω) 5.98 V Full 1 MΩ: R B 1,000 kω kω 1,150 kω 1.15 MΩ VCC VBE 12 V 0.7 V I B R + β ( R + R ) 1.15 M Ω+ (180)(4.7 kω+ 3.3 k Ω) B C E 4.36 μa I C βi B (180)(4.36 μa) ma V C V CC I C R C 12 V (0.785 ma)(4.7 kω) 8.31 V V C ranges from 5.98 V to 8.31 V 26. (a) V E V B V BE 4 V 0.7 V 3.3 V VE 3.3 V (b) I C I E R 2.75 ma E 1.2 kω (c) V C V CC I C R C 18 V (2.75 ma)(2.2 kω) V (d) V CE V C V E V 3.3 V 8.65 V VR V V 4 V B C VB (e) I B μa RB RB 330 kω IC 2.75 ma (f) β I μa B VCC + VEE VBE 6 V + 6 V 0.7 V 27. (a) I B RB + ( β + 1) RE 330 k Ω+ (121)(1.2 k Ω) μa I E (β + 1)I B (121)(23.78 μa) 2.88 ma V EE + I E R E V E 0 V E V EE + I E R E 6 V + (2.88 ma)(1.2 kω) 2.54 V VEE VBE 12 V 0.7 V 28. (a) I B RB + ( β + 1) RE 9.1 k Ω+ ( )15 kω 6.2 μa (b) I C βi B (120)(6.2 μa) ma (c) V CE V CC + V EE I C (R C + R E ) 16 V + 12 V (0.744 ma)(27 kω) 7.91 V (d) V C V CC I C R C 16 V (0.744 ma)(12 kω) 7.07 V 41

45 29. (a) I E 8 V 0.7 V 7.3 V 2.2 kω 2.2 kω 3.32 ma (b) V C 10 V (3.32 ma)(1.8 kω) 10 V V (c) V CE 10 V + 8 V (3.32 ma)(2.2 kω kω) 18 V V 4.72 V 30. (a) βr E > 10R 2 not satisfied Use exact approach: Network redrawn to determine the Thevenin equivalent: (b) I C βi B (130)(13.95 μa) 1.81 ma R Th 510 k Ω 255 kω 2 18 V + 18 V I μa 510 kω kω E Th 18 V + (35.29 μa)(510 kω) 0 V 18 V 0.7 V I B 255 k Ω + ( )(7.5 k Ω) μa (c) V E 18 V + (1.81 ma)(7.5 kω) 18 V V 4.42 V (d) V CE 18 V + 18 V (1.81 ma)(9.1 kω kω) 36 V V 5.95 V 31. (a) I B VR V 8 V 0.7 V B C VBE R R 560 kω B B μa VCC V (b) I C R C C 18 V 8 V 10 V 3.9 kω 3.9 kω 2.56 ma (c) β I I C B 2.56 ma μa (d) V CE V C 8 V 42

46 I 2.5 ma 32. I B C β μa VR V 12 V 0.7 V B CC VBE R B kω IB IB μa VR V 12 V 6 V 6 V C CC V VCC V C CEQ R C I I I 2.5 ma 2.5 ma C C CQ 2.4 kω Standard values: R B 360 kω R C 2.4 kω 33. VCC I C sat R + R C 20 V R + R 4 E E E 10 ma 10 ma 20 V 5R E 10 ma 5R E 20 V 10 ma 2 kω R E 2 k 5Ω 400 Ω R C 4R E 1.6 kω I 5 ma I B C β μa 20 V 0.7 V 5 ma(0.4 k Ω) V R B V RB /I B μa μa kω Standard values: R E 390 Ω, R C 1.6 kω, R B 430 kω VE VE 3 V 34. R E 0.75 kω IE IC 4 ma V ( ) R V C CC V VCC V C CE + V Q E R C IC IC IC 24 V (8 V + 3 V) 24 V 11 V 13 V 3.25 kω 4 ma 4 ma 4 ma V B V E + V BE 3 V V 3.7 V RV 2 CC R2 (24 V) V B 3.7 V 2 unknowns! R2 + R1 R2 + R1 use βr E 10R 2 for increased stability (110)(0.75 kω) 10R 2 R kω Choose R kω 43

47 Substituting in the above equation: 7.5 k Ω(24 V) 3.7 V 7.5 kω+ R1 R kω Standard values: R E 0.75 kω, R C 3.3 kω, R kω, R 1 43 kω 35. V E 1 V 1 (28 V) 5.6 V 5 CC 5 VE 5.6 V R E 1.12 kω (use 1.1 kω) I E 5 ma VCC 28 V V C + VE V 14 V V 19.6 V 2 2 V R C V CC V C 28 V 19.6 V 8.4 V VR 8.4 V R C C 1.68 kω (use 1.6 kω) IC 5 ma V B V BE + V E 0.7 V V 6.3 V RV 2 V B CC R2 (28 V) 6.3 V (2 unknowns) R2 + R1 R2 + R1 IC 5 ma β I B 37 μa βr E 10R 2 (135.14)(1.12 kω) 10(R 2 ) R kω (use 15 kω) (15.14 k Ω)(28 V) Substituting: 6.3 V kω+ R1 Solving, R kω (use 51 kω) Standard values: R E 1.1 kω R C 1.6 kω R 1 51 kω R 2 15 kω 36. I 2 kω 18 V 0.7 V 2 kω 8.65 ma I 37. For current mirror: I(3 kω) I(2.4 kω) I 2 ma 38. I DQ I 6 ma DSS 44

48 4.3 kω 39. V B ( 18 V) 9 V 4.3 kω+ 4.3 kω V E 9 V 0.7 V 9.7 V 18 V ( 9.7 V) I E 4.6 ma I 1.8 kω 40. I E V Z V R E BE 5.1 V 0.7 V 1.2 kω 3.67 ma 41. VCC 10 V IC ma sat RC 2.4 kω From characteristics I B max 31 μa Vi VBE 10 V 0.7 V I B μa R 180 kω B μa 31 μa, well saturated V o 10 V (0.1 ma)(2.4 kω) 10 V 0.24 V 9.76 V 42. I C sat 8 ma 5 V RC 5 V R C kω 8 ma I C 8 ma sat I B max 80 μa β 100 Use 1.2 (80 μa) 96 μa R B 5 V 0.7 V kω 96 μa Standard values: R B 43 kω R C 0.62 kω 45

49 43. (a) From Fig. 3.23c: I C 2 ma: t f 38 ns, t r 48 ns, t d 120 ns, t s 110 ns t on t r + t d 48 ns ns 168 ns t off t s + t f 110 ns + 38 ns 148 ns (b) I C 10 ma: t f 12 ns, t r 15 ns, t d 22 ns, t s 120 ns t on t r + t d 15 ns + 22 ns 37 ns t off t s + t f 120 ns + 12 ns 132 ns The turn-on time has dropped dramatically 168 ns:37 ns 4.54:1 while the turn-off time is only slightly smaller 148 ns:132 ns 1.12:1 44. (a) Open-circuit in the base circuit Bad connection of emitter terminal Damaged transistor (b) Shorted base-emitter junction Open at collector terminal (c) Open-circuit in base circuit Open transistor 45. (a) The base voltage of 9.4 V reveals that the 18 kω resistor is not making contact with the base terminal of the transistor. If operating properly: V B 18 k Ω(16 V) 18 kω+ 91 kω 2.64 V vs. 9.4 V As an emitter feedback bias circuit: VCC VBE 16 V 0.7 V I B R1 + ( β + 1) RE 91 k Ω+ ( )1.2 kω 72.1 μa V B V CC I B (R 1 ) 16 V (72.1 μa)(91 kω) 9.4 V 46

50 (b) Since V E > V B the transistor should be off 18 k Ω(16 V) With I B 0 μa, V B 18 kω + 91 kω 2.64 V Assume base circuit open The 4 V at the emitter is the voltage that would exist if the transistor were shorted collector to emitter. 1.2 k Ω(16 V) V E 1.2 kω+ 3.6 kω 4 V 46. (a) R B, I B, I C, V C (b) β, I C (c) Unchanged, I C sat not a function of β (d) V CC, I B, I C (e) β, I C, V, R C VR E, V CE ETh VBE ETh VBE 47. (a) I B RTh + ( β + 1) RE RTh + βre ETh V BE ETh VBE I C βi B β R R Th + β RE Th + RE β RTh As β, β, I C, V C V CC and V C V R C VR C (b) R 2 open, I B, I C V CE V CC I C (R C + R E ) and V CE (c) V CC, V B, V E, I E, I C (d) I B 0 μa, I C I CEO and I C (R C + R E ) negligible with V CE V CC 20 V (e) Base-emitter junction short I B but transistor action lost and I C 0 ma with V CE V CC 20 V 48. (a) R B open, I B 0 μa, I C I CEO 0 ma and V C V CC 18 V (b) β, I C, V, V, V CE R C R E (c) R C, I B, I C, V E (d) Drop to a relatively low voltage 0.06 V (e) Open in the base circuit 47

51 V 49. I B CC V R B BE 12 V 0.7 V 11.3 V μa 510 kω 510 kω I C βi B (100)(22.16 μa) ma V C V CC + I C R C 12 V + (2.216 ma)(3.3 kω) 4.69 V V CE V C 4.69 V 50. βr E 10R 2 (220)(0.75 kω) 10(16 kω) 165 kω 160 kω (checks) Use approximate approach: 16 k Ω ( 22 V) V B 16 k Ω + 82 kω 3.59 V V E V B V 3.59 V V 2.89 V I C I E V E /R E 2.89/0.75 kω 3.85 ma I 3.85 ma I B C 17.5 μa β 220 V C V CC + I C R C 22 V + (3.85 ma)(2.2 kω) V V V 51. I E R E BE 8 V 0.7 V 7.3 V ma 3.3 kω 3.3 kω V C V CC + I C R C 12 V + (2.212 ma)(3.9 kω) 3.37 V 52. (a) S(I CO ) β (b) S(V BE ) I C β kω S R B 2.93 ma 1 (c) S(β) β A 1 (d) ΔI C S(I CO )ΔI CO + S(V BE )ΔV BE + S(β)Δβ (91)(10 μa 0.2 μa) + ( S)(0.5 V 0.7 V) + ( A)( ) (91)(9.8 μa) + ( S)(0.2 V) + ( A)(22.5) A A A A 1.66 ma 48

52 53. For the emitter-bias: (1 + RB / RE) ( k Ω/1.5 k Ω) (a) S(I CO ) (β + 1) ( ) ( β + 1) + RB / RE ( ) k Ω/1.5 kω 78.1 (b) S(V BE ) R B β ( β + 1) R 510 k Ω+ ( )1.5 kω E S IC (1 + R / ) 2.92 ma( ) 1 B RE (c) S(β) β (1 + β + R / R ) 100( ) 1 2 B A E (d) ΔI C S(I CO )ΔI CO + S(V BE )ΔV BE + S(β)Δβ (78.1)(9.8 μa) + ( S)( 0.2 V) + ( A)(25) ma ma ma 1.33 ma 54. (a) R Th 62 kω 9.1 kω 7.94 kω 1 + RTh / RE ( k Ω/ 0.68 k Ω) S(I CO ) (β + 1) (80 + 1) ( β + 1) + RTh / RE (80+ 1) k Ω/0.68 kω (81)( ) β 80 (b) S(V BE ) RTh + ( β + 1) RE 7.94 k Ω+ (81)(0.68 k Ω) kω kω S IC (1 + R / ) 1.71 ma( k / 0.68 k ) 1 Th RE Ω Ω (c) S(β) β (1 + β + R / R ) 80( k Ω/ 0.68 k Ω) 1 2 Th 1.71 ma(12.68) 80(112.68) E A (d) ΔI C S(I CO )ΔI CO + S(V BE ) ΔV BE + S(β)Δβ (11.08)(10 μa 0.2 μa) + ( S)(0.5 V 0.7 V) + ( A)(100 80) (11.08)(9.8 μa) + ( S)( 0.2 V) + ( A)(20) A A A A ma 49

53 55. For collector-feedback bias: (1 + RB / RC) ( k Ω/3.9 k Ω) (a) S(I CO ) (β + 1) ( ) ( β + 1) + RB / RC ( ) k Ω/3.9 kω (197.32) ( ) (b) S(V BE ) R B β ( β + 1) R 560 k Ω+ ( )3.9 kω C S IC ( R ) 2.56 ma(560 k 3.9 k ) 1 B + RC Ω+ Ω (c) S(β) β ( R + R ( β + 1)) (560 kω+ 3.9 k Ω ( )) 1 B C A (d) ΔI C S(I CO )ΔI CO + S(V BE ) ΔV BE + S(β)Δβ (83.69)(9.8 μa) + ( S)( 0.2 V) + ( A)(49.1) A A A A ma 56. Type S(I CO ) S(V BE ) S(β) Collector feedback S A Emitter-bias S A Voltage-divider S A Fixed-bias S A S(I CO ): Considerably less for the voltage-divider configuration compared to the other three. S(V BE ): The voltage-divider configuration is more sensitive than the other three (which have similar levels of sensitivity). S(β): The voltage-divider configuration is the least sensitive with the fixed-bias configuration very sensitive. In general, the voltage-divider configuration is the least sensitive with the fixed-bias the most sensitive. 57. (a) Fixed-bias: S(I CO ) 91, ΔI C ma S(V BE ) S, ΔI C ma S(β) A, ΔI C ma (b) Voltage-divider bias: S(I CO ) 11.08, ΔI C ma S(V BE ) S, ΔI C ma S(β) A, ΔI C ma 50

54 (c) For the fixed-bias configuration there is a strong sensitivity to changes in I CO and β and less to changes in V BE. For the voltage-divider configuration the opposite occurs with a high sensitivity to changes in V BE and less to changes in I CO and β. In total the voltage-divider configuration is considerably more stable than the fixed-bias configuration. 51

55 Chapter 5 1. (a) If the dc power supply is set to zero volts, the amplification will be zero. 2. (b) Too low a dc level will result in a clipped output waveform. (c) P o I 2 R (5 ma) kω 55 mw P i V CC I (18 V)(3.8 ma) 68.4 mw Po (ac) 55 mw η % P (dc) 68.4 mw i x C Ω 2π fc 2 π(1 khz)(10μf) f 100 khz: x C Ω Yes, better at 100 khz 4. Vi 10 mv 5. (a) Z i I i 0.5 ma 20 Ω (r e ) (b) V o I c R L αi c R L (0.98)(0.5 ma)(1.2 kω) V Vo (c) A v V i 58.8 (d) Z o Ω V 10 mv Io (e) A i I i α I I e e α 0.98 (f) I b I e I c 0.5 ma 0.49 ma 10 μa 52

56 6. (a) r e Vi I i 48 mv 15 Ω 3.2 ma (b) Z i r e 15 Ω (c) I C αi e (0.99)(3.2 ma) ma (d) V o I C R L (3.168 ma)(2.2 kω) 6.97 V (e) A v Vo 6.97 V V 48 mv i (f) I b (1 α)i e (1 0.99)I e (0.01)(3.2 ma) 32 μa 7. (a) r e (b) I b 26 mv 26 mv 13 Ω I E (dc) 2 ma Z i βr e (80)(13 Ω) 1.04 kω IC α I β e Ie Ie β β β + 1 β β ma μa Io I L (c) A i Ii Ib ro( β Ib) I L ro + RL ro β Ib ro + RL ro A i β I r + R (d) A v b o L 40 kω (80) 40 kω+ 1.2 kω RL ro 1.2 kω 40 kω r 13 Ω kω 13 Ω 89.6 e 53

57 8. (a) Z i βr e (140)r e 1200 r e Ω Vi 30 mv (b) I b Z 25 μa 1.2 kω i (c) I c βi b (140)(25 μa) 3.5 ma (d) I L A i ri o c (50 k Ω)(3.5 ma) r + R 50 kω+ 2.7 kω o I I L i L ma 25 μa ma Vo AR i L (e) A v V Z i i (2.7 k Ω) (132.84) 1.2 k Ω VCC VBE 12 V 0.7 V 9. (a) r e : I B μa RB 220 kω I E (β + 1)I B (60 + 1)(51.36 μa) 3.13 ma 26 mv 26 mv r e 8.31 Ω 3.13 ma I E Z i R B βr e 220 kω (60)(8.31 Ω) 220 kω Ω Ω r o 10R C Z o R C 2.2 kω (b) A v RC 2.2 kω r 8.31 Ω e (c) Z i Ω (the same) Z o r o R C 20 kω 2.2 kω 1.98 kω (d) A v RC ro 1.98 kω r 8.31 Ω e A i A v Z i /R C ( )( Ω)/2.2 kω

58 RC 10. A v r e r r e V 11. (a) I B e RC 4.7 kω 23.5 Ω A ( 200) v 26 mv 26 mv 26 mv I E ma I E r e 23.5 Ω I ma I B E μa β VCC VBE I B V CC I B R B + V BE RB (12.15 μa)(1 MΩ) V V V V CC V R B BE 10 V 0.7 V μa 390 kω I E (β + 1)I B (101)(23.85 μa) 2.41 ma 26 mv 26 mv r e Ω I E 2.41 ma I C βi B (100)(23.85 μa) 2.38 ma (b) Z i R B βr e 390 kω (100)(10.79 Ω) 390 kω 1.08 kω 1.08 kω r o 10R C Z o R C 4.3 kω (c) A v (d) A v RC 4.3 kω r Ω e RC ro (4.3 k Ω) (30 k Ω) 3.76 kω r Ω Ω e 12. (a) Test βr E 10R 2? (100)(1.2 kω) 10(4.7 kω) 120 kω > 47 kω (satisfied) Use approximate approach: RV k (16 V) V B CC Ω R + R 39 kω+ 4.7 kω V 1 2 V E V B V BE V 0.7 V V VE V I E R ma 1.2 kω r e E 26 mv 26 mv Ω ma I E 55

59 (b) Z i R 1 R 2 β r e 4.7 kω 39 kω (100)(30.56 Ω) kω r o 10R C Z o R C 3.9 kω (c) A v RC 3.9 kω r Ω e (d) r o 25 kω (b) Z i (unchanged) kω Z o R C r o 3.9 kω 25 kω 3.37 kω (c) A v ( RC ro) (3.9 k Ω) (25 k Ω) 3.37 kω r Ω Ω e (vs )? 13. βr E 10R 2 (100)(1 kω) 10(5.6 kω) 100 kω > 56 kω (checks!) & r o 10R C Use approximate approach: RC RC 3.3 kω A v re Ω r A 160 e v 26 mv 26 mv 26 mv r e I E ma IE re Ω VE I E R V E I E R E (1.261 ma)(1 kω) V E V B V BE + V E 0.7 V V V 5.6 kω V V B CC 5.6 kω+ 82 kω V 5.6 kω V CC (1.961 V)(87.6 kω) V CC V 14. Test βr E 10R 2? (180)(2.2 kω) 10(56 kω) 396 kω < 560 kω (not satisfied) Use exact analysis: (a) R Th 56 kω 220 kω kω 56 k Ω(20 V) E Th 220 kω + 56 kω V ETh VBE V 0.7 V I B R + ( β + 1) R k Ω+ (181)(2.2 k Ω) Th E 56

60 7.58 μa I E (β + 1)I B (181)(7.58 μa) ma 26 mv 26 mv r e Ω ma I E (b) V E I E R E (1.372 ma)(2.2 kω) 3.02 V V B V E + V BE 3.02 V V 3.72 V V C V CC I C R C 20 V βi B R C 20 V (180)(7.58 μa)(6.8 kω) V (c) Z i R 1 R 2 βr e 56 kω 220 kω (180)(18.95 kω) kω 3.41 kω 3.17 kω RC ro r o < 10R C A v re (6.8 k Ω) (50 k Ω) Ω VCC VBE 20 V 0.7 V 15. (a) I B RB + ( β + 1) RE 390 k Ω+ (141)(1.2 k Ω) 19.3 V μa kω I E (β + 1)I B ( )(34.51 μa) ma 26 mv 26 mv r e 5.34 Ω ma I E (b) Z b βr e + (β + 1)R E (140)(5.34 kω) + ( )(1.2 kω) Ω kω kω Z i R B Z b 390 kω kω kω Z o R C 2.2 kω (c) A v β R Z C b (140)(2.2 k Ω) kω 1.81 (d) Z b βr e + ( β + 1) + RC / ro 1 + ( R + R )/ r C E o R (141) k Ω/ 20 kω Ω 1 + (3.4 k Ω)/ 20 kω 1.2 kω E 57

61 747.6 Ω kω kω Z i R B Z b 390 kω kω kω Z o R C 2.2 kω (any level of r o ) β R C r e RC V Z o b ro ro A v V R i C 1+ r o (140)(2.2 k Ω) 5.34 Ω 2.2 kω kω 20 k 20 k Ω Ω 2.2 kω kω Even though the condition r o 10R C is not met it is sufficiently close to permit the use of the approximate approach. β RC β RC RC A v 10 Zb β RE RE RC 8.2 kω R E 0.82 kω mv 26 mv I E ma 3.8 Ω r e V E I E R E (6.842 ma)(0.82 kω) 5.61 V V B V E + V BE 5.61 V V 6.31 V I ma I B E μa ( β + 1) 121 VR V 20 V 6.31 V B CC VB and R B kω I I μa B 17. (a) dc analysis the same r e 5.34 Ω (as in #15) B (b) Z i R B Z b R B βr e 390 kω (140)(5.34 Ω) Ω vs kω in #15 Z o R C 2.2 kω (as in #15) (c) A v RC 2.2 kω r 5.34 Ω e vs 1.81 in #15 (d) Z i Ω vs kω for #15 Z o R C r o 2.2 kω 20 kω 1.98 kω vs. 2.2 kω in #15 58

62 18. (a) I B RC ro 1.98 kω A v vs in #15 re 5.34 Ω Significant difference in the results for A v. VCC VBE R + ( β + 1) R B E 22 V 0.7 V 21.3 V 330 k Ω+ (81)(1.2 kω k Ω) kω μa I E (β + 1)I B (81)(45.78 μa) 3.71 ma 26 mv 26 mv r e 7 Ω 3.71 ma I E (b) r o < 10(R C + R E ) ( β + 1) + RC / ro Z b βr e ( R + R )/ r C E o R E (80)(7 Ω) + (81) k Ω/ 40 kω k Ω/ 40 kω 1.2 kω 560 Ω kω (note that (β + 1) 81 R C /r o 0.14) 560 Ω + [81.14 /1.17]1.2 kω 560 Ω kω kω Z i R B Z b 330 kω kω kω β R C r e RC 1+ + Zb ro ro A v RC 1+ ro (80)(5.6 k Ω) 7 Ω 5.6 kω kω 40 kω 40 kω k Ω/40 kω (5.35) (a) I B VCC VBE 16 V 0.7 V 15.3 V R + ( β + 1) R 270 k Ω+ (111)(2.7 k Ω) kω B E 59

63 26.86 μa I E (β + 1)I B ( )(26.86 μa) 2.98 ma 26 mv 26 mv r e 8.72 Ω I E 2.98 ma βr e (110)(8.72 Ω) Ω (b) Z b βr e + (β + 1)R E Ω + (111)(2.7 kω) kω Z i R B Z b 270 kω kω kω Z o R E r e 2.7 kω 8.72 Ω 8.69 Ω (c) A v RE 2.7 kω R + r 2.7 kω Ω E e 20. (a) I B VCE VBE 8 V 0.7 V R + ( β + 1) R 390 k Ω+ (121)5.6 kω B E I E (β + 1)I B (121)(6.84 μa) ma 26 mv 26 mv r e 31.4 Ω I E ma r o < 10R E : Z b βr e + ( β + 1) RE 1 + RE / ro (121)(5.6 k Ω) (120)(31.4 Ω) k Ω/40 kω 3.77 kω kω kω Z i R B Z b 390 kω kω kω Z o R E r e 5.6 kω 31.4 Ω 31.2 Ω 6.84 μa (b) A v ( β + 1) R / E Z 1 + R / r E o (121)(5.6 k Ω) / kω k Ω/ 40 kω V0 (c) A v V i b V o A v V i (0.994)(1 mv) mv 60

64 21. (a)? Test βr E 10R 2 (200)(2 kω) 10(8.2 kω) 400 kω 82 kω (checks)! Use approximate approach: 8.2 k Ω(20 V) V B 8.2 kω+ 56 kω V V E V B V BE V 0.7 V V VE V I E R ma E 2 kω I ma I B E 4.61 μa ( β + 1) ( ) I C βi B (200)(4.61 μa) ma (b) r e 26 mv 26 mv Ω ma I E (c) Z b βr e + (β + 1)R E (200)(28.05 Ω) + ( )2 kω 5.61 kω kω kω Z i 56 kω 8.2 kω kω 7.15 kω kω 7.03 kω Z o R E r e 2 kω Ω Ω (d) A v 22. (a) I E r e RE 2 kω R + r 2 kω Ω V E EE E e V R BE 6 V 0.7 V ma 6.8 kω 26 mv 26 mv Ω ma I E (b) Z i R E r e 6.8 kω Ω Ω Z o R C 4.7 kω α RC (0.998)(4.7 k Ω) (c) A v re Ω α β β

65 VEE VBE 5 V 0.7 V 4.3 V I E 1.1 ma RE 3.9 kω 3.9 kω 26 mv 26 mv r e Ω I E 1.1 ma RC (0.9868)(3.9 k Ω) A v α r Ω e VCC VBE 12 V 0.7 V 24. (a) I B RF + β RC 220 kω+ 120(3.9 k Ω) μa I E (β + 1)I B ( )(16.42 μa) ma r e 26 mv 26 mv Ω ma I E (b) Z i βr e R A F v Need A v! RC 3.9 kω A v re Ω 298 Z i (120)(13.08 Ω) 220 k Ω kω 738 Ω Ω Z o R C R F 3.9 kω 220 kω 3.83 kω (c) From above, A v 298 RC 25. A v r e 160 R C 160(r e ) 160(10 Ω) 1.6 kω A i β RF R + β R F C RF R + 200(1.6 k Ω) F 19R F R C 200R F R F 3800 R C 3800(1.6 k Ω) kω VCC VBE I B R + β R F I B (R F + βr C ) V CC V BE C 62

66 and V CC V BE + I B (R F + βr C ) 26 mv 26 mv with I E 2.6 ma r e 10 Ω I 2.6 ma I B E μa β V CC V BE + I B (R F + βr C ) 0.7 V + (12.94 μa)(33.59 kω + (200)(1.6 kω)) 5.28 V 26. (a) A v : V i I b βr e + (β + 1)I b R E I o + I I C βi b but I i I + I b and I I i I b Substituting, I o + (I i I b ) βi b and I o (β + 1)I b I i Assuming (β + 1)I b I i I o (β + 1)I b and V o I o R C (β + 1)I b R C Vo ( β + 1) IbRC Therefore, V I βr + ( β + 1) I R β IR b C β Ir b e+ β IR b E Vo RC RC and A v V r + R R (b) V i βi b (r e + R E ) For r e R E V i βi b R E i b e b E i e E E Now I i I + I b V V R i o F + I b 63

67 Since V o V i Vo I i + I R Vo or I b I i + RF and V i βi b R E Vo V i βr E I i + β R E RF but V o A v V i β AVR v i E and V i βr E I i + R Avβ REVi or V i R F F b F βr E I i Avβ R E V i 1 [ β RE ] Ii RF Vi β RE β RERF so Z i I Avβ RE 1 R + β ( A ) R R Vi Z i I with Z i Z i Z o : Set V i 0 i F v E i F x y where x βr E and y R F / A v x y ( β RE )( RF / Av ) x + y β R + R / A β RERF β R A + R E v F E F v V i I b βr e + (β + 1)I b R E V i βi b (r e + R E ) 0 since β, r e + R E 0 I b 0 and βi b 0 64

68 Vo V 1 1 o I o + Vo + RC RF RC RF Vo 1 RCRF and Z o I R + R R R o C F C F R C R F RC 2.2 kω (c) A v RE 1.2 kω 1.83 β RR E F (90)(1.2 k Ω)(120 k Ω) Z i β R A + R (90)(1.2 k Ω )(1.83) kω E v F 40.8 kω Z o R C R F 2.2 kω 120 kω 2.16 kω VCC VBE 9 V 0.7 V 27. (a) I B RF + β RC (39 kω+ 22 k Ω ) + (80)(1.8 k Ω) 8.3 V 8.3 V μa 61 kω+ 144 kω 205 kω I E (β + 1)I B (80 + 1)(40.49 μa) 3.28 ma 26 mv 26 mv r e 7.93 Ω I E 3.28 ma Z i R F 1 β re 39 kω (80)(7.93 Ω) 39 kω Ω 0.62 kω Z o R C R 1.8 kω 22 kω 1.66 kω F 2 R RC RF 1.8 kω 22 kω 2 (b) A v r r 7.93 Ω 28. A i β A i β 100 e e kω 7.93 Ω A i A v Z i /R C ( 127.6)(1.768 kω)/3.9 kω (c) A i β RB (140)(390 k Ω) R + Z 390 kω kω B b (d) A i Z i Av ( )( Ω)/2.2 kω R C

69 32. A i A v Z i /R E (0.986)(7.03 kω)/2 kω 3.47 Io α Ie 33. A i α I I i e 34. A i A v Z i /R C ( 298)( Ω)/3.9 kω A i Zi ( )(0.62 k Ω) Av R 1.8 kω C VCC VBE 18 V 0.7 V 36. (a) I B μa RB 680 kω I E (β + 1)I B ( )(25.44 μa) 2.57 ma 26 mv r e 2.57 ma Ω RC 3.3 kω Av NL r Ω (b) e Z i R B βr e 680 kω (100)( Ω) 680 kω 1,011.6 Ω 1.01 kω Z o R C 3.3 kω (c) (d) (e) A v L RL 4.7 kω Av NL R + R 4.7 kω+ 3.3 kω ( ) L o Zi (1.01 k Ω) A i L Av ( ) L R L 4.7 kω A v L V β Ib( RC R ) o L 100(1.939 k Ω) V I ( β r ) 100( Ω) i b e Z i R B βr e 1.01 kω RC( β Ib) I L 41.25I b RC + RL RBIi I b I i RB + βre Io IL IL Ib A i L (41.25)(0.9985) Ii Ii Ib Ii Z o R C 3.3 kω 66

70 37. (a) A v NL RL A v L Av R + R L R L 4.7 kω: R L 2.2 kω: R L 0.5 kω: As R L, o NL A v L A v L A v L Av L 4.7 kω ( ) 4.7 kω kω 2.2 kω ( ) 2.2 kω+ 3.3 kω 0.5 kω ( ) 0.5 kω+ 2.3 kω (b) No change for Z i, Z o, and A v NL! VCC VBE 12 V 0.7 V 38. (a) I B 11.3 μa RB 1 MΩ I E (β + 1)I B (181)(11.3 μa) ma 26 mv 26 mv r e Ω I E ma RC 3 kω A V NL r Ω 236 (b) e Z i R B βr e 1 MΩ (180)(12.71 Ω) 1 MΩ kω kω Z o R C 3 kω (c) No-load: A v A v NL 236 (d) A vs Zi k Ω ( 236) Av NL Z + R kω+ 0.6 kω i s (e) V o I o R C βi b R C V i I b βr e Vo β IbRC RC 3 kω A v Vi β Ibre re Ω 236 Vo Vo Vi Av s Vs Vi Vs (1 M Ω β re) Vs k Ω( Vs ) V i (1 M Ω β re) + Rs kω+ 0.6 kω V s A v s ( 236)(0.792) (same results) 67

71 (f) (g) No change! A vs R s, Zi k Ω ( 236) ( Av ) NL Z + R kω+ 1 kω i A v s s (h) No change! VCC VBE 24 V 0.7 V 39. (a) I B μa RB 500 kω I E (β + 1)I B (80 + 1)(41.61 μa) 3.37 ma 26 mv 26 mv r e Ω I E 3.37 ma RL 4.3 kω A v NL re Ω Z i R B βr e 560 kω (80)(7.715 Ω) 560 kω Ω Ω Z o R C 4.3 kω (b) (c) A v L Vo RL 2.7 k Ω ( ) Av NL V R + R 2.7 kω+ 4.3 kω i L o Vo Vo Vi Av s Vs Vi Vs ZV i s Ω Vs V i Zi + Rs Ω+ 1 kω V s A v s ( )(0.381) (d) A is Rs + Z i 1 kω Ω Av ( 81.91) s RL 2.7 kω (e) A v L Vo RL 5.6 k Ω ( ) Av NL V R + R 5.6 kω+ 4.3 kω i L o Vi the same Vs Vo Vi A vs V i V ( )(0.381) s As R L, A v s 68

72 (f) A v L the same Vi Zi Ω Vs Zi + Rs Ω+ 0.5 kω Vo Vi A vs V i V ( )(0.552) s As R s, A v s (g) No change! 40. (a) Exact analysis: R2 16 k Ω(16 V) E Th VCC R + R 68 kω+ 16 kω V (b) 1 2 R Th R 1 R 2 68 kω 16 kω kω I B ETh VBE V 0.7 V R + ( β + 1) R k Ω+ (101)(0.75 k Ω) Th μa I E (β + 1)I B (101)(26.47 μa) ma 26 mv 26 mv r e Ω I E ma RC 2.2 kω Av NL re Ω Z i 68 kω 16 kω βr e kω (100)(9.726 Ω) kω Ω Ω Z o R C 2.2 kω E (c) (d) A v L A i L RL 5.6 k Ω ( 226.2) ( Av ) NL R + Z 5.6 kω+ 2.2 kω L A vl Z R o i L ( 162.4) ( Ω ) 5.6 kω

73 (e) A v L RC Re 2.2 kω 5.6 kω r Ω e Z i 68 kω 16 kω Ω 41. (a) Ω Zi A i L Av L R L βr e ( 162.4)( Ω ) 5.6 kω Z o R C 2.2 kω Same results! A v L RL R + Z L R L 4.7 kω: R L 2.2 kω: R L 0.5 kω: R L, Av L o A vnl A v L A v L A v L 4.7 kω ( 226.4) 4.7 kω+ 2.2 kω 2.2 kω ( 226.4) 2.2 kω+ 2.2 kω 0.5 kω ( 226.4) 0.5 kω+ 2.2 kω (b) Unaffected! VCC VBE 18 V 0.7 V 42. (a) I B RB + ( β + 1) RE 680 k Ω+ (111)(0.82 k Ω) μa I E (β + 1)I B ( )(22.44 μa) 2.49 ma 26 mv 26 mv r e Ω I E 2.49 ma RC 3 kω Av NL re + RE Ω kω 3.61 Z i R B Z b 680 kω (βr e + (β + 1)R E ) 680 kω (610)(10.44 Ω) + ( )(0.82 kω) 680 kω kω kω Z o R C 3 kω (b) 70

74 (c) A v L Vo RL 4.7 k Ω( 3.61) Av NL V R + R 4.7 kω+ 3 kω i L o 2.2 Vo Vo Vi Av s Vs Vi Vs ZV i s k Ω ( Vs) V i Zi + Rs kω+ 0.6 kω V s A v s ( 2.2)(0.992) 2.18 (d) None! (e) A v L none! Vi Zi kω Vs Zi + Rs kω+ 1 kω A v s ( 2.2)(0.988) 2.17 R s, Av s, (but only slightly for moderate changes in R s since Z i is typically much larger than R s ) 43. Using the exact approach: ETh VBE I B RTh + ( β + 1) RE 2.33 V 0.7 V 10.6 k Ω+ (121)(1.2 k Ω) R2 E Th V R + R 1 2 CC 12 kω (20 V) 2.33 V 91 kω+ 12 kω μa R Th R 1 R 2 91 kω 12 kω 10.6 kω I E (β + 1)I B (121)(10.46 μa) ma 26 mv 26 mv r e Ω ma I E (a) A vnl RE 1.2 kω r + R Ω+ 1.2 kω e E Z i R 1 R 2 (βr e + (β +1)R E ) 91 kω 12 kω ((120)(20.54 Ω) + ( )(1.2 kω)) 10.6 kω (2.46 kω kω) 10.6 kω kω 9.89 kω Z o R E r e 1.2 kω Ω Ω 71

75 (b) (c) (d) RL 2.7 k Ω(0.983) A v L Av NL RL + Zo 2.7 kω Ω Zi 9.89 k Ω(0.976) Av A s v L Zi + Rs 9.89 kω+ 0.6 kω 0.92 A v L (unaffected by change in R s ) Zi 9.89 k Ω(0.976) Av A s v L Zi + Rs 9.89 kω+ 1 kω (vs with R s 0.6 kω) As R s, A v s (e) Changing R s will have no effect on A v NL, Z i, or Z o. (f) A L ( A ) v v L R 5.6 k Ω(0.983) NL R + Z 5.6 kω Ω L o (vs with R L 2.7 kω) Zi 9.89 k Ω(0.979) Av ( A ) s v L Z + R 9.89 kω+ 0.6 kω i s (vs with R L 2.7 kω) As R L, A, A v L v s VEE VBE 6 V 0.7 V 44. (a) I E RE 2.2 kω 2.41 ma 26 mv 26 mv r e Ω I E 2.41 ma RC 4.7 kω A v NL r Ω (b) e Z i R E r e 2.2 kω Ω Ω Z o R C 4.7 kω (c) RL 5.6 k Ω(435.59) A v L Av NL RL + Ro 5.6 kω+ 4.7 kω Zi Ω ( Vs) V i Vs Zi + Rs Ω+ 100 Ω V s Vo Vi A vs V i V (236.83)(0.097) s

76 (d) V i I e r e V o I o R L 4.7 k Ω( I ) I o e 4.7 kω+ 5.6 kω I e Vo A v L V + ( Ie) RL (5.6 k Ω) i Ie re Ω (vs for part c) A v s : 2.2 kω Ω Ω Zi Ω ( Vs) V i Vs Zi + Rs Ω+ 100 Ω V s Vo Vi A vs V i V (236.82)(0.097) s (same results) (e) RL 2.2 kω A v L Av (435.59) NL RL + Ro 2.2 kω+ 4.7 kω V0 Vi Vi Zi Ω Av, s Vi Vs Vs Zi + Rs Ω+ 500 Ω A (138.88)(0.021) 2.92 v s A v s very sensitive to increase in R s due to relatively small Z i ; R s, A v L sensitive to R L ; R L, Av L Av s (f) Z o R C 4.7 kω unaffected by value of R s! (g) Z i R E r e Ω unaffected by value of R L! 45. (a) (b) A A v1 v2 A v L A vs RA L v NL 1 k Ω ( 420) RL + Ro 1 kω+ 3.3 kω RA L v NL 2.7 k Ω ( 420) R + R 2.7 kω+ 3.3 kω 189 A L o A ( 97.67)( 189) v1 v2 V V V V V V V V o o o1 i1 s i2 i1 s V i V i Av A 2 v1 V s ZV i s 1 k Ω( Vs) Z + R 1 kω+ 0.6 kω i A v s ( 189)( 97.67)(0.625) s 73

77 (c) (d) AZ v i ( 97.67)(1 k Ω) Ai R 1 kω A i2 L L AZ v i ( 189)(1 k Ω) 70 R 2.7 kω A A A (97.67)(70) il i1 i2 (e) No effect! (f) No effect! (g) In phase 46. (a) Zi 1.2 kω 2 Av A (1) 1 v 1NL Zi + Z 1.2 k 20 2 o Ω+ Ω RL 2.2 kω A v 2 Av ( 640) 2 NL RL + Zo 2.2 kω+ 4.6 kω (b) A A A (0.984)( ) A vl v1 v2 vs Zi Av Z + R i s L 50 kω ( ) 50 kω+ 1 kω Zi 1 (c) Ai A 1 v1 Z i2 (50 k Ω) (0.984) 1.2 k Ω 41 Zi 2 Ai A 2 v2 R L (1.2 k Ω) ( ) 2.2 k Ω Zi 1 (d) Ai A L vl R L ( ) (50 k Ω ) 2.2 kω

78 (e) A load on an emitter-follower configuration will contribute to the emitter resistance (in fact, lower the value) and therefore affect Z i (reduce its magnitude). (f) The fact that the second stage is a CE amplifier will isolate Z o from the first stage and R s. (g) The emitter-follower has zero phase shift while the common-emitter amplifier has a 180 phase shift. The system, therefore, has a total phase shift of 180 as noted by the negative sign in front of the gain for A in part b. 47. For each stage: 6.2 kω V B (15 V) 3.08 V 24 kω+ 6.2 kω V E V B 0.7 V 3.08 V 0.7 V 2.38 V VE 2.38 V I E I C R 1.59 ma 1.5 kω 48. r e E V C V CC I C R C 15 V (1.59 ma)(5.1 kω) 6.89 V 26 mv 26 mv Ω 1.59 ma I E R i 2 R 1 R 2 βr e 6.2 kω 24 kω (150)(16.35 Ω) 1.64 kω RC Ri 5.1 k Ω 1.64 kω 2 Av re Ω RC 5.1 kω Av 2 re Ω A v A A ( 75.8)( 311.9) 23,642 v1 v2 v T 49. V B 1 V B 2 V I 3.9 kω (20 V) 4.4 V 3.9 kω+ 6.2 kω+ 7.5 kω 6.2 kω+ 3.9 kω (20 V) V 3.9 kω+ 6.2 kω+ 7.5 kω V 0.7 V 4.4 V 0.7 V 3.7 V E1 B1 VE 3.7 V 1 I R 1 kω 3.7 ma IE I 2 C2 C1 E1 E V V CC I C R C 20 V (3.7 ma)(1.5 kω) C V 75

79 26 mv 26 mv 50. r e 7 Ω I E 3.7 ma re Av 1 1 re RE 1.5 kω Av 2 r 7 Ω 214 e Av A T v A 1 v ( 1)(214) V o AV ( 214)(10 mv) 2.14 V vt i 51. R o R D 1.5 kω (V o (from problem 50) 2.14 V) RL 10 kω V o (load) ( Vo ) ( 2.14 V) R + R 10 kω+ 1.5 kω 52. I B o L 1.86 V VCC VBE (16 V 1.6 V) β R + R (6000)(510 Ω ) MΩ D E B 14.4 V 2.64 μa 5.46 MΩ I C I E β D I B 6000(2.64 μa) 15.8 ma V E I E R E (15.8 ma)(510 Ω) 8.06 V 53. From problem 69, I E 15.8 ma r e V 1.65 Ω I E 15.8 ma RE 510 Ω A v r + R 1.65 Ω+ 510 Ω e E 54. dc: I I r B VCC VBE 16 V 1.6 V R + β R 2.4 M Ω+ (6000)(510 Ω ) B D E β I (6000)(2.64 μa) ma C D B e2 26 mv 26 mv 1.64 Ω I ma E μa ac: Z β r (6000)(1.64 Ω ) 9.84 kω i D e2 Vi I b kω V i Vo ( βdib )( R ) (6000) (200 ) 1 C Ω 9.84 kω Vi and A V o v Vi 76

80 VCC VEB 16 V 0.7 V I B R + ββ R 1.5 M Ω+ (160)(200)(100 Ω) B 1 2 E μa I C β 1 β 2 I B (160)(200)(3.255μA) ma V C 2 V CC I C R C 16 V (104.2 ma)(100 Ω) 5.58 V V B 1 I B R B (3.255 μa)(1.5 MΩ) 4.48 V 56. From problem 55: I E ma 26 mv 26 mv re 49.9 Ω 1 I E (ma) ma Ri β r 1 e 160(49.9 Ω) 7.98 kω i β1β2rc (160)(200)(100 Ω) A v ββ R + R (160)(200)(100 Ω ) kω 57. r e C i V o A v V i (120 mv) mv 26 mv 26 mv Ω 1.2 ma I E (dc) βr e (120)(21.67 Ω) 2.6 kω Vo 62. (a) A v V i 160 V o 160 V i Vi hrevo Vi hreav v i Vi(1 hreav) (b) I b hie hie hie 4 V i ( 1 (2 10 )(160)) 1 kω I b V i (c) I b 1 k i V Ω V i 77

81 1 10 Vi (d) % Difference Vi 3.2 % 3 4 V i 100% (e) Valid first approximation 63. % difference in total load R R 1/ h L L oe 2.2 k Ω (2.2 kω 50 k Ω) 100% 2.2 kω 2.2 kω kω 100% 2.2 kω 4.2 % R L 100% In this case the effect of 1/h oe can be ignored. 64. (a) V o 180V i (h ie 4 kω, h re ) 4 Vi ( )(180 Vi) (b) I b 4 kω V i (c) I b Vi Vi h 4 kω V i ie (d) % Difference V i Vi V i 100% 7.2% (e) Yes, less than 10% 65. From Fig min max h oe : 1 μs 30 μs Avg (1 + 30) μ S μs 66. (a) h fe β 120 h ie βr e (120)(4.5 Ω) 540 Ω h oe 1 1 r 25 μs 40 kω h ie o 1 kω (b) r e Ω β 90 β h fe r o 20 μs hoe 50 kω 78

82 67. (a) r e 8.31 Ω (from problem 9) (b) h fe β 60 h ie βr e (60)(8.31 Ω) Ω (c) Z i R B h ie 220 kω Ω Ω Z o R C 2.2 kω (d) A v hferc (60)(2.2 k Ω) h Ω ie A i h fe (e) Z i Ω (the same) 1 Z o r o R C, r o 40 kω 25 μ S 40 kω 2.2 kω 2.09 kω hfe( ro RC ) (60)(2.085 k Ω) (f) A v h Ω ie A i A v Z i /R C ( )( Ω)/2.2 kω (a) 68 kω 12 kω 10.2 kω Z i 10.2 kω h ie 10.2 kω 2.75 kω kω Z o R C r o 2.2 kω 40 kω kω (b) A v hfer C R C R C r o kω hie (180)(2.085 k Ω) kω Io Io I i A i I I I i i i hf 10.2 k e Ω 1+ hoer L 10.2 kω kω 180 (0.792) 1 + (25 μs)(2.2 k Ω)

83 69. (a) Z i R E h ib 1.2 kω 9.45 Ω 9.38 Ω 1 Z o R C 2.7 kω h ob 1 A V 2.7 kω 1 MΩ 2.7 kω hfb ( RC 1/ hob ) ( 0.992)( 2.7 k Ω) (b) A v hib 9.45 Ω A i 1 (c) α h fb ( 0.992) α β 1 α r e h ib 9.45 Ω 1 1 r o 1 MΩ 1 μa/v hob 70. (a) (b) (c) 4 hfehrerl (180)(2 10 )(2.2 k ) Z Ω i hie 2.75 kω 1 + hoerl (1+ 25μS)(2.2 k Ω) 2.68 kω Z i 10.2 kω Z i 2.12 kω 1 1 Z o 4 hoe ( hfehre / hie) 25 μs (180)(2 10 ) / 2.75 kω kω Z o 2.2 kω kω 2.14 kω hferl (180)(2.2 k Ω) Av h + ( h h h h ) R 2.75 k Ω + (2.75 k Ω)(25μS) (180)(2 10 ) 2.2 kω ie ie oe fe re L hfe (180) A i h R 1 + (25μS)(2.2 k Ω) A i oe L Io Io I i 10.2 kω (170.62) Ii I I i i 10.2 k Ω k Ω ( ) 80

84 hfehrerl 71. (a) Z i h ie 1 + h R oe L 4 (140)( )(2.2 k Ω) 0.86 kω 1 + (25 μs)(2.2 k Ω) 0.86 kω Ω Ω Z i R B Z i 470 kω Ω Ω hferl (b) A v hie + ( hie hoe hfehre) RL (140)(2.2 k Ω) k Ω+ ((0.86 k Ω)(25 μs) (140)( ))2.2 kω I h o fe 140 (c) A i Ii 1+ hoerl 1 + (25 μs)(2.2 k Ω) I o I o I i A 470 k Ω I i i I i I I i i I i 470 kω kω (132.70)(0.998) Ii I i (d) Z o 1 ( /( )) h h h h + R oe fe re ie s 1 25 μs (140)( ) /(0.86 kω+ 1 k Ω) μs 4 ( ) 72.9 kω 72. (a) (b) hfbhrbrl Z Ω i hib 9.45 Ω 1+ hobrl 1 + (0.5μA/V)(2.2 k Ω) 9.67 Ω Z i 1.2 kω Z i 1.2 kω 9.67 Ω 9.59 Ω 4 ( 0.997)(1 10 )(2.2 k ) hfb A i h R 1 + (0.5 μa/v)(2.2 k Ω) ob L Io I i 1.2 kω Ai ( 0.996) I I i i 1.2 k Ω k Ω

85 (c) (d) hfbrl Av hib + ( hibhob hfbhrb ) RL ( 0.997)(2.2 k Ω) Ω+ ((9.45 Ω)(0.5 μa/v) ( 0.997)(1 10 ))(2.2 k Ω) Z o hob hfbhrb / h ib μa/v ( 0.997)(1 10 ) /9.45 Ω 90.5 kω Z o 2.2 kω Z o 2.15 kω (a) h fe (0.2 ma) 0.6 (normalized) h fe (1 ma) 1.0 % change h fe (0.2 ma) h (1mA) h fe fe (0.2 ma) % % 100% (b) h fe (1 ma) 1.0 h fe (5 ma) 1.5 hfe (1 ma) hfe (5 ma) % change h (1 ma) % fe 100% 100% 75. Log-log scale! (a) I c 0.2 ma, h ie 4 (normalized) I c 1 ma, h ie 1(normalized) % change % 75% 4 (b) I e 5 ma, h ie 0.3 (normalized) % change % 70% 1 82

86 76. (a) h oe 20 1 ma I c 0.2 ma, h oe 0.2(h 1 ma) 0.2(20 μs) 4 μs (b) r o kω 6.8 kω 4 μs hoe Ignore 1/h oe 77. (a) I c 10 ma, h oe 10(20 μs) 200 μs 1 1 (b) r o 5 kω vs. 8.6 kω hoe 200μS Not a good approximation 78. (a) h re (0.1 ma) 4(h re (1 ma)) 4( ) (b) h re V ce h re A v V i ( )(210)V i V i In this case h re V ce is too large a factor to be ignored. 79. (a) h fe (b) h oe (c) h oe 30 (normalized) to h oe 0.1 (normalized) at low levels of I c (d) mid-region 80. (a) h ie is the most temperature-sensitive parameter of Fig (b) h oe exhibited the smallest change. (c) Normalized: h fe(max) 1.5, h fe(min) 0.5 For h fe 100 the range would extend from 50 to 150 certainly significant. (d) On a normalized basis r e increased from 0.3 at 65 C to 3 at 200 C a significant change. (e) The parameters show the least change in the region C. 83

87 81. (a) Test: βr E 10R 2 70(1.5 kω) 10(39 kω)? 105 kω 390 kω No! R Th 39 kω 150 kω kω 39 k Ω(14 V) E Th 39 kω+ 150 kω 2.89 V ETh VBE 2.89 V 0.7 V I B R + ( β + 1) R k Ω+ (71)(1.5 k Ω) Th μa V B E Th I B R Th 2.89 V (15.93 μa)(30.95 kω) V E V E V 0.7 V V VE V and I E R 1.13 ma 1.5 kω E V CE V CC I C (R C + R E ) 14 V 1.13 ma(2.2 kω kω) V Biasing OK (b) R 2 not connected at base: VCC 0 14 V 0.7 V I B μa R + ( β + 1) R 150 k Ω + (71)(1.5 k Ω ) B E V B V CC I B R B 14 V (51.85 μa)(150 kω) 6.22 V as noted in Fig

88 Chapter From Fig. 6.11: V GS 0 V, I D 8 ma V GS 1 V, I D 4.5 ma V GS 1.5 V, I D 3.25 ma V GS 1.8 V, I D 2.5 ma V GS 4 V, I D 0 ma V GS 6 V, I D 0 ma 3. (a) V DS 1.4 V (b) r d V 1.4 V I 6 ma Ω (c) V DS 1.6 V (d) r d V 1.6 V I 3 ma Ω (e) V DS 1.4 V (f) r d V 1.4 V I 1.5 ma Ω (g) r o Ω r Ω Ω o r d [ 1 V V ] [ 1 ( 1 V) ( 4 V) ] GS Ω P Ω Ω 1 ( 2V) ( 4V) 0.25 (h) r d [ ] Ω (i) Ω vs Ω Ω vs Ω Eq. (6.1) is valid! 4. (a) V GS 0 V, I D 8 ma (for V DS > V P ) V GS 1 V, I D 4.5 ma ΔI D 3.5 ma (b) V GS 1 V, I D 4.5 ma V GS 2 V, I D 2 ma ΔI D 2.5 ma 85

89 (c) V GS 2 V, I D 2 ma V GS 3 V, I D 0.5 ma ΔI D 1.5 ma (d) V GS 3 V, I D 0.5 ma V GS 4 V, I D 0 ma ΔI D 0.5 ma (e) As V GS becomes more negative, the change in I D gets progressively smaller for the same change in V GS. (f) Non-linear. Even though the change in V GS is fixed at 1 V, the change in I D drops from a maximum of 3.5 ma to a minimum of 0.5 ma a 7:1 change in ΔI D. 5. The collector characteristics of a BJT transistor are a plot of output current versus the output voltage for different levels of input current. The drain characteristics of a JFET transistor are a plot of the output current versus input voltage. For the BJT transistor increasing levels of input current result in increasing levels of output current. For JFETs, increasing magnitudes of input voltage result in lower levels of output current. The spacing between curves for a BJT are sufficiently similar to permit the use of a single beta (on an approximate basis) to represent the device for the dc and ac analysis. For JFETs, however, the spacing between the curves changes quite dramatically with increasing levels of input voltage requiring the use of Shockley s equation to define the relationship between I D and V GS. VC sat and V P define the region of nonlinearity for each device. 6. (a) The input current I G for a JFET is effectively zero since the JFET gate-source junction is reverse-biased for linear operation, and a reverse-biased junction has a very high resistance. (b) The input impedance of the JFET is high due to the reverse-biased junction between the gate and source. (c) The terminology is appropriate since it is the electric field established by the applied gate to source voltage that controls the level of drain current. The term field is appropriate due to the absence of a conductive path between gate and source (or drain). 7. V GS 0 V, I D I DSS 12 ma V GS V P 6 V, I D 0 ma Shockley s equation: V GS 1 V, I D 8.33 ma; V GS 2 V, I D 5.33 ma; V GS 3 V, I D 3 ma; V GS 4 V, I D 1.33 ma; V GS 5 V, I D ma. 8. For a p-channel JFET, all the voltage polarities in the network are reversed as compared to an n-channel device. In addition, the drain current has reversed direction. 86

90 9. (b) I DSS 10 ma, V P 6 V 10. V GS 0 V, I D I DSS 12 ma V GS V P 4 V, I D 0 ma V P I V GS 2 V, ID DSS 3 ma 2 4 V GS 0.3V P 1.2 V, I D 6 ma V GS 3 V, I D 0.75 ma (Shockley s equation) 11. (a) I D I DSS 9 ma (b) I D I DSS (1 V GS /V P ) 2 9 ma(1 ( 2 V)/( 3.5 V)) ma (c) V GS V P 3.5 V, I D 0 ma (d) V GS < V P 3.5 V, I D 0 ma 12. V GS 0 V, I D 16 ma V GS 0.3V P 0.3( 5 V) 1.5 V, I D I DSS /2 8 ma V GS 0.5V P 0.5( 5 V) 2.5 V, I D I DSS /4 4 ma V GS V P 5 V, I D 0 ma 13. V GS 0 V, I D I DSS 7.5 ma V GS 0.3V P (0.3)(4 V) 1.2 V, I D I DSS /2 7.5 ma/ ma V GS 0.5V P (0.5)(4 V) 2 V, I D I DSS /4 7.5 ma/ ma V GS V P 4 V, I D 0 ma 14. (a) I D I DSS (1 V GS /V P ) 2 6 ma(1 ( 2 V)/( 4.5 V)) ma I D I DSS (1 V GS /V P ) 2 6 ma(1 ( 3.6 V)/( 4.5 V)) ma I 3 ma D (b) V GS VP 1 ( 4.5 V) 1 I DSS 6 ma V I 5.5 ma D V GS VP 1 ( 4.5 V) 1 I DSS 6 ma V 15. I D I DSS (1 V GS /V P ) 2 3 ma I DSS (1 ( 3 V)/( 6 V)) 2 3 ma I DSS (0.25) I DSS 12 ma 87

91 16. From Fig. 6.22: 0.5 V < V P < 6 V 1 ma < I DSS < 5 ma For I DSS 5 ma and V P 6 V: V GS 0 V, I D 5 ma V GS 0.3V P 1.8 V, I D 2.5 ma V GS V P /2 3 V, I D 1.25 ma V GS V P 6 V, I D 0 ma For I DSS 1 ma and V P 0.5 V: V GS 0 V, I D 1 ma V GS 0.3V P 0.15 V, I D 0.5 ma V GS V P / V, I D 0.25 ma V GS V P 0.5 V, I D 0 ma PD max 17. V DS V DS max 25 V, I D V DSmax 120 mw 4.8 ma 25 V PD 120 mw max I D I DSS 10 ma, V DS 12 V I 10 ma DSS PD 120 mw max I D 7 ma, V DS V I 7 ma D 88

92 18. V GS 0.5 V, I D 6.5 ma 2.5 ma V GS 1 V, I D 4 ma Determine ΔI D above 4 ma line: 2.5 ma x x 1.5 ma 0.5 V 0.3 V I D 4 ma ma 5.5 ma corresponding with values determined from a purely graphical approach. 19. Yes, all knees of V GS curves at or below V P 3 V. 20. From Fig 6.25, I DSS 9 ma At V GS 1 V, I D 4 ma I D I DSS (1 V GS /V P ) 2 I D 1 V GS /V P I DSS VGS V 1 I D P I DSS VGS 1 V V P I D 4 ma 1 1 I 9 ma DSS 3 V (an exact match) 21. I D I DSS (1 V GS /V P ) 2 9 ma(1 ( 1 V)/( 3 V)) 2 4 ma, which compares very well with the level obtained using Fig (a) V DS 0.7 I D 4 ma (for V GS 0 V) ΔVDS 0.7 V 0 V r 175 Ω ΔI 4 ma 0 ma 23. D (b) For V GS 0.5 I D 3 ma, V DS 0.7 V r 0.7 V 3 ma 233 Ω ro 175 Ω (c) r d 2 2 (1 VGS / VP ) (1 ( 0.5 V)/( 3 V) 252 Ω vs. 233 Ω from part (b) 24. The construction of a depletion-type MOSFET and an enchancement-type MOSFET are identical except for the doping in the channel region. In the depletion MOSFET the channel is established by the doping process and exists with no gate-to-source voltage applied. As the gate-to-source voltage increases in magnitude the channel decreases in size until pinch-off occurs. The enhancement MOSFET does not have a channel established by the doping sequence but relies on the gate-to-source voltage to create a channel. The larger the magnitude of the applied gate-to-source voltage, the larger the available channel. 89

93 At V GS 0 V, I D 6 ma At V GS 1 V, I D 6 ma(1 ( 1 V)/( 3 V)) ma At V GS +1 V, I D 6 ma(1 (+1 V)/( 3 V)) 2 6 ma(1.333) ma At V GS +2 V, I D 6 ma(1 (+2 V)/( 3 V)) 2 6 ma(1.667) ma V GS I D 1 V 2.66 ma ma +1 V ma +2 V ma Δ I D Δ I D Δ I D 3.34 ma 4.67 ma 6 ma From 1 V to 0 V, ΔI D 3.34 ma while from +1 V to +2 V, ΔI D 6 ma almost a 2:1 margin. In fact, as V GS becomes more and more positive, I D will increase at a faster and faster rate due to the squared term in Shockley s equation. V P 27. V GS 0 V, I D I DSS 12 ma; V GS 8 V, I D 0 ma; V GS 2 4 V, ID 3 ma; V GS 0.3V P 2.4 V, I D 6 ma; V GS 6 V, I D 0.75 ma 28. From problem 20: VGS V P I 1 I D DSS V + 1 V + 1 V 14 ma ma 4.67 V 29. I D I DSS (1 V GS /V P ) 2 4 ma (1 ( 2 V) ( 5 V)) D I DSS 2 2 ( ) 1 V I GS V P ma 30. From problem 14(b): I 20 ma D V GS VP 1 ( 5 V) 1 I DSS 2.9 ma ( 5 V)( ) ( 5 V)( 1.626) 8.13 V 31. From Fig. 6.34, P D max 200 mw, I D 8 ma P V DS I D Pmax and V DS I D 200 mw 25 V 8 ma 90

94 32. (a) In a depletion-type MOSFET the channel exists in the device and the applied voltage V GS controls the size of the channel. In an enhancement-type MOSFET the channel is not established by the construction pattern but induced by the applied control voltage V GS. (b) (c) Briefly, an applied gate-to-source voltage greater than V T will establish a channel between drain and source for the flow of charge in the output circuit. 33. (a) I D k(v GS V T ) (V GS 3.5) 2 V GS I D 3.5 V 0 4 V 0.1 ma 5 V 0.9 ma 6 V 2.5 ma 7 V 4.9 ma 8 V 8.1 ma (b) I D (V GS 3.5) 2 V GS I D 3.5 V 0 4 V 0.2 ma 5 V 1.8 ma 6 V 5.0 ma 7 V 9.8 ma 8 V 16.2 ma For same levels of V GS, I D attains twice the current level as part (a). Transfer curve has steeper slope. For both curves, I D 0 ma for V GS < 3.5 V. D(on) 34. (a) k ( VGS (on) VT ) I 4mA (6 V 4 V) 2 2 I D k(v GS V T ) (V GS 4 V) 2 1 ma/v 2 (b) V GS I D For V GS < V T 4 V, I D 0 ma 4 V 0 ma 5 V 1 ma 6 V 4 ma 7 V 9 ma 8 V 16 ma (c) V GS I D (V GS < V T ) 2 V 0 ma 5 V 1 ma 10 V 36 ma 91

95 35. From Fig. 6.58, V T 2.0 V At I D 6.5 ma, V GS 5.5 V: I D k(v GS V T ) ma k(5.5 V 2 V) 2 k I D (V GS 2) I D kv ( V) 2 GS (on) and ( V V ) 2 V T V GS (on) GS (on) T I D T k I D VT k D V GS (on) I k 3mA 4 V V V V 4 V 7.5 V 37. I D k(v GS V T ) 2 I D k (V GS V T ) 2 I D V GS V T k V GS V T V I D k 30 ma 5 V Enhancement-type MOSFET: 2 I D kv ( GS VT ) di D d 2 kv ( GS VT ) ( VGS VT ) dvgs dvgs 1 di D 2k(V GS V T ) dv GS 92

96 Depletion-type MOSFET: I D I DSS (1 V GS /V P ) 2 2 di D d V GS I DSS 1 dvgs dvgs VP V GS d V GS IDSS 21 0 VP dvgs VP di dv D GS 1 V P V GS 1 2I DSS 1 VP VP 2I DSS V GS 1 VP VP 2I DSS V P V GS 1 VP VP VP 2I DSS ( VGS VP ) V 2 P di D For both devices k 1 (V GS K 2 ) dvgs revealing that the drain current of each will increase at about the same rate. 39. I D k(v GS V T ) (V GS ( 5 V)) (V GS + 5 V) 2 V GS 5 V, I D 0 ma; V GS 6 V, I D 0.45 ma; V GS 7 V, I D 1.8 ma; V GS 8 V, I D 4.05 ma; V GS 9 V, I D 7.2 ma; V GS 10 V, I D ma (a) 43. V 0.1 V (b) For the on transistor: R 25 ohms I 4 ma V 4.9 V For the off transistor: R I 0.5 μa 9.8 MΩ Absolutely, the high resistance of the off resistance will ensure V o is very close to 5 V. 93

97 Chapter 7 1. (a) V GS 0 V, I D I DSS 12 ma V GS V P 4 V, I D 0 ma V GS V P /2 2 V, I D I DSS /4 3 ma V GS 0.3V P 1.2 V, I D I DSS /2 6 ma (b) (c) (d) I D Q 4.7 ma V DS Q V DD 6.36 V I DQ R 12 V (4.7 ma)(1.2 kω) D I D Q I DSS (1 V GS /V P ) 2 12 ma(1 ( 1.5 V)/( 4 V)) ma V DS Q V DD ID R Q D 12 V (4.69 ma)(1.2 kω) 6.37 V excellent comparison 2. (a) (b) 2 I I DSS (1 V / V ) D Q GS P 10 ma ( 1 ( 3 V) ( 4.5 V) ) 2 10 ma(0.333) 2 I 1.11 ma D Q V GS Q 3 V (c) V DS V DD I D (R D + R S ) 16 V (1.11 ma)(2.2 kω) 16 V V V V D V DS V V G V 3 V GS Q V S 0 V 94

98 3. (a) I DQ VDD VD 14 V 9 V R 1.6 kω D ma (b) V DS V D V S 9 V 0 V 9 V (c) I D I DSS (1 V GS /V P ) 2 I D V GS VP 1 I V GS ( 4 V) V V GG 1.5 V ma 8 ma DSS 4. V GS Q 0 V, I D I DSS 5 ma V D V DD I D R D 20 V (5 ma)(2.2 kω) 20 V 11 V 9 V 5. V GS V P 4 V I D Q 0 ma and V D V DD I 18 V DQ R 18 V (0)(2 kω) 6. (a)(b) V GS 0 V, I D 10 ma V GS V P 4 V, I D 0 ma V P V GS 2 V, ID 2.5 ma 2 D V GS 0.3V P 1.2 V, I D 5 ma V GS I D R S I D 5 ma: V GS (5 ma)(0.75 kω) 3.75 V (c) I D Q 2.7 ma V GS Q 1.9 V (d) V DS V DD I D (R D + R S ) 18 V (2.7 ma)(1.5 kω kω) V V D V DD I D R D 18 V (2.7 ma)(1.5 kω) V V G 0 V V S I S R S I D R S (2.7 ma)(0.75 kω) 2.03 V 95

99 7. I D I DSS (1 V GS /V P ) 2 2I R I DSS 2 IDSS R S 2 2IDSS R S I 1 I I VP VP I R 2 2 D S D S VP VP D D DSS 0 Substituting: I I D D + 10 ma 0 2 b± b 4ac I D ma, 2.60 ma 2a I D Q 2.6 ma (exact match #6) V GS I D R S (2.60 ma)(0.75 kω) 1.95 V vs. 2 V (#6) 8. V GS 0 V, I D I DSS 6 ma V GS V P 6 V, I D 0 ma V P V GS 3 V, ID 1.5 ma 2 V GS 0.3V P 1.8 V, I D 3 ma V GS I D R S I D 2 ma: V GS (2 ma)(1.6 kω) 3.2 V (a) I D Q 1.7 ma V GS Q 2.8 V (b) V DS V DD I D (R D + R S ) 12 V (1.7 ma)(2.2 kω kω) 5.54 V V D V DD I D R D 12 V (1.7 ma)(2.2 kω) 8.26 V V G 0 V V S I S R S I D R S (1.7 ma)(1.6 kω) 2.72 V (vs. 2.8 V from V S ( V GS Q )) 9. (a) I D Q I S VS 1.7 V R 0.51 kω S 3.33 ma (b) V I R (3.33 ma)(0.51 kω) GSQ DQ S 1.7 V 96

100 (c) I D I DSS (1 V GS /V P ) ma I DSS (1 ( 1.7 V)/( 4 V)) ma I DSS (0.331) I DSS ma (d) V D V DD I DQ R D 18 V (3.33 ma)(2 kω) 18 V 6.66 V V (e) V DS V D V S V 1.7 V 9.64 V 10. (a) V GS 0 V I D I DSS 4.5 ma (b) V DS V DD I D (R D + R S ) 20 V (4.5 ma)(2.2 kω kω) 20 V V (c) V D V DD I D R D 20 V (4.5 ma)(2.2 kω) 10.1 V (d) V S I S R S I D R S (4.5 ma)(0.68 kω) 3.06 V 11. Network redrawn: V GS 0 V, I D I DSS 6 ma V GS V P 6 V, I D 0 ma V P V GS 3 V, ID 1.5 ma 2 V GS 0.3V P 1.8 V, I D 3 ma V GS I D R S I D (0.39 kω) For I D 5 ma, V GS 1.95 V 97

101 From graph I D Q 3.55 ma V GS Q 1.4 V V S ( V GSQ ) ( 1.4 V) +1.4 V R2 110 k Ω(20 V) 12. (a) V G VDD R1 + R2 910 kω kω 2.16 V V GS 0 V, I D I DSS 10 ma V GS V P 3.5 V, I D 0 ma V P V GS 1.75 V, ID 2.5 ma 2 V GS 0.3V P 1.05 V, I D 5 ma V GS Q V G I D R S V GS Q 2.16 I D (1.1 kω) I D 0: V GS Q V G 2.16 V V GS Q 0 V, I D 2.16 V 1.96 ma 1.1 kω (b) I D Q 3.3 ma V GS Q 1.5 V (c) V D V DD ID R Q D 20 V (3.3 ma)(2.2 kω) V V S I S R S I D R S (3.3 ma)(1.1 kω) 3.63 V (d) V V DD I ( R + R ) DS Q DQ D S 20 V (3.3 ma)(2.2 k Ω kω) 20 V V 9.11 V 98

102 13. (a) I D I DSS 10 ma, V P 3.5 V V GS 0 V, I D I DSS 10 ma V GS V P 3.5 V, I D 0 ma VP 3.5 V V GS 2 2 V GS 0.3V P 1.05 V, I D 5 ma V G 1.75 V, I D 2.5 ma I D Q 5.8 ma vs. 3.3 ma (#12) V GS Q 0.85 V vs. 1.5 V (#12) 110 k Ω(20 V) 110 kω kω 2.16 V (b) As R S decreases, the intersection on the vertical axis increases. The maximum occurs at I D I DSS 10 ma. VG 2.16 V RS min 216 Ω I 10 ma DSS 14. (a) I D VR V 18 V 9 V 9 V D DD VD R R 2 kω 2 kω D D 4.5 ma (b) V S I S R S I D R S (4.5 ma)(0.68 kω) 3.06 V V DS V DD I D (R D + R S ) 18 V (4.5 ma)(2 kω kω) 18 V V 5.94 V R2 91 k Ω(18 V) (c) V G VDD R + R 750 kω+ 91 kω 1.95 V 1 2 V GS V G V S 1.95 V 3.06 V 1.11 V VGS 1.11 V (d) V P 4.44 V I D 4.5 ma 1 1 I 8 ma DSS 1.48 V 99

103 15. (a) V GS 0 V, I D I DSS 6 ma V GS V P 6 V, I D 0 ma V GS V P /2 3 V, I D 1.5 ma V GS 0.3V P 1.8 V, I D 3 ma V GS V SS I D R S V GS 4 V I D (2.2 kω) 4 V V GS 0 V, I D 2.2 kω I D 0 ma, V GS 4 V ma I D Q 2.7 ma V GS Q 2 V (b) V DS V DD + V SS I D (R D + R S ) 16 V + 4 V (2.7 ma)(4.4 kω) 8.12 V V S V SS + I D R S 4 V + (2.7 ma)(2.2 kω) 1.94 V or V S ( V GSQ ) ( 2 V) +2 V 16. (a) I D V VDD + VSS VDS 12 V+ 3 V 4 V 11 V R R + R 3 kω+ 2 kω 5 kω D S 2.2 ma (b) V D V DD I D R D 12 V (2.2 ma)(3 kω) 5.4 V V S I S R S + V SS I D R S + V SS (2.2 ma)(2 kω) + ( 3 V) 4.4 V 3 V 1.4 V (c) V GS V G V S 0 V 1.4 V 1.4 V 17. (a) I D Q 4 ma (b) V D Q 12 V 4 ma(1.8 k Ω ) 12 V 7.2 V 4.8 V DS Q V 4.8 V (c) P s (12 V)(4 ma) 48 mw P d (4.8 V)(4 ma) 19.2 mw 100

104 18. V GS 0 V, I D I DSS 6 ma V GS V P 4 V, I D 0 ma V GS V P /2 2 V, I D I DSS /4 1.5 ma V GS 0.3V P 1.2 V, I D I DSS /2 3 ma V GS I D R S I D (0.43 kω) I D 4 ma, V GS 1.72 V (b) V DS V DD I D (R D + R S ) 14 V 2.9 ma(1.2 kω kω) 9.27 V V D V DD I D R D 14 V (2.9 ma)(1.2 kω) V 19. (a) V GS 0 V, I D I DSS 8 ma V GS V P 8 V, I D 0 ma V P V GS 4 V, ID 2 ma 2 V GS 0.3V P 2.4 V, I D 4 ma V GS +1 V, I D ma V GS +2 V, I D 12.5 ma V GS V SS I D R S ( 4 V) I D (0.39 kω) V GS 4 I D (0.39 kω) I D 0: V GS +4 V 4 V GS 0: I D ma 0.39 kω I D Q 9 ma V GS Q +0.5 V 101

105 (b) V DS V DD I D (R D + R S ) + V SS 18 V 9 ma(1.2 kω kω) + 4 V 22 V V 7.69 V V S ( V GSQ ) 0.5 V 20. I D k(v GS V T ) 2 D(on) k ( VGS (on) VTh ) I 2 5 ma 5 ma (7 V 4 V) 9 V 2 2 K A/V 2 and I D (V GS 4 V) 2 V DS V DD I D (R D + R S ) VDD V DS 0 V; I D RD + RS 22 V 1.2 kω kω ma I D 0 ma, V DS V DD 22 V (c) V D V DD I D R D 22 V (8.25 ma)(1.2 kω) 12.1 V V S I S R S I D R S (8.25 ma)(0.51 kω) 4.21 V (d) V DS V D V S 12.1 V 4.21 V 7.89 V vs. 7.9 V obtained graphically 102

106 R2 6.8 MΩ 21. (a) V G VDD (24 V) R + R 10 MΩ+ 6.8 MΩ V V GS V G I D R S V GS 9.71 I D (0.75 kω) At I D 0 ma, V GS 9.71 V 9.71 V At V GS 0 V, I D 0.75 kω D(on) k ( VGS (on) VGS ( Th) ) I A/V 2 I D (V GS 3 V) ma 5 ma 5 ma (6 V 3 V) (3 V) V GS I D 3 V 0 ma 4 V ma 5 V 2.22 ma 6 V 5 ma 7 V 8.9 ma I D Q 5 ma V GS Q 6 V 103

107 (b) V D V DD I D R D 24 V (5 ma)(2.2 kω) 13 V V S I S R S I D R S (5 ma)(0.75 kω) 3.75 V R2 18 kω 22. (a) V G VCC (20 V) R1 + R2 91 kω+ 18 kω 3.3 V (b) V GS 0 V, I D I DSS 6 ma V GS V P 6 V, I D 0 ma V P V GS 3 V, ID 1.5 ma 2 V GS V P 1.8 V, I D 3 ma I D Q 3.75 ma V GS Q 1.25 V (c) I E I D 3.75 ma (d) I B I C 3.75 ma μa β 160 (e) V D V E V B V BE V CC I B R B V BE 20 V (23.44 μa)(330 kω) 0.7 V V (f) V C V CC I C R C 20 V (3.75 ma)(1.1 kω) V 23. Testing: βr E 10R 2 (100)(1.2 kω) 10(10 kω) 120 kω > 100 kω (satisfied) RV DD 2 10 k Ω(16 V) (a) V B V G R1 + R2 40 kω+ 10 kω 3.2 V (b) V E V B V BE 3.2 V 0.7 V 2.5 V VE 2.5 V (c) I E R 2.08 ma E 1.2 kω I C I E 2.08 ma I D I C 2.08 ma 104

108 (d) I B I C 2.08 ma 20.8 μa β 100 (e) V C V G V GS I D V GS VP 1 I DSS 2.08 ma ( 6 V) 1 6 ma 2.47 V V C 3.2 ( 2.47 V) 5.67 V V S V C 5.67 V V D V DD I D R D 16 V (2.08 ma)(2.2 kω) V (f) V CE V C V E 5.67 V 2.5 V 3.17 V (g) V DS V D V S V 5.67 V 5.75 V I D 24. V GS VP 1 I 1.75 V DSS V GS I D R S : R S ( 6 V) 1 4 ma 8 ma VGS ( 1.75 V) 0.44 kω I 4 ma R D 3R S 3(0.44 kω) 1.32 kω Standard values: R S 0.43 kω R D 1.3 kω D I D 2.5 ma 25. V GS VP 1 ( 4 V) I 1 DSS 10 ma 2 V V GS V G V S and V S V G V GS 4 V ( 2 V) 6 V VS 6 V R S 2.4 kω (a standard value) I D 2.5 ma R D 2.5R S 2.5(2.4 kω) 6 kω use 6.2 kω RV 2 V G DD R2 (24 V) 4 V 88 MΩ + 4R 2 24R 2 R1 + R2 22 MΩ+R2 20R 2 88 MΩ R MΩ Use R MΩ 105

109 26. I D k(v GS V T ) 2 I D k (V GS V T ) 2 I D V GS V T k D and V GS V T + I 6mA 4 V V 3 2 k A/V VR V 16 V 7.46 V 8.54 V D DD VDS VDD VGS R D ID ID ID 6 ma 6 ma 1.42 kω Standard value: R D 0.75 kω R G 10 MΩ 27. (a) I D I S VS 4 V R 1 kω 4 ma S V DS V DD I D (R D + R S ) 12 V (4 ma)(2 kω + 1 kω) 12 V (4 ma)(3 kω) 12 V 12 V 0 V JFET in saturation! (b) V S 0 V reveals that the JFET is nonconducting and the JFET is either defective or an open-circuit exists in the output circuit. V S is at the same potential as the grounded side of the 1 kω resistor. (c) Typically, the voltage across the 1 MΩ resistor is 0 V. The fact that the voltage across the 1 MΩ resistor is equal to V DD suggests that there is a short-circuit connection from gate to drain with I D 0 ma. Either the JFET is defective or an improper circuit connection was made. 75 k Ω(20 V) 28. V G 3.7 V (seems correct!) 75 kω+ 330 kω V GS 3.7 V 6.25 V 2.55 V (possibly okay) I D I DSS (1 V GS /V P ) 2 10 ma(1 ( 2.55 V)/( 6 V)) ma (reasonable) VS 6.25 V However, I S R 6.25 ma 3.3 ma S 1 kω V R D I D R D I S R D (6.25 ma)(2.2 kω) V and VR + V S R 6.25 V V D 20 V V DD V DS 0 V 1. Possible short-circuit from D-S. 2. Actual I DSS and/or V P may be larger in magnitude than specified. 106

110 VS 6.25 V 29. I D I S R 6.25 ma S 1 kω V DS V DD I D (R D + R S ) 20 V (6.25 ma)(2.2 kω + 1 kω) 20 V 20 V 0 V (saturation condition) RV DD 2 75 k Ω(20 V) V G 3.7 V (as it should be) R1 + R2 330 kω+ 75 kω V GS V G V S 3.7 V 6.25 V 2.55 V 2 V GS I D I DSS 1 10 ma(1 ( 2.55 V)/(6 V)) 2 VP 3.3 ma 6.25 ma In all probability, an open-circuit exists between the voltage divider network and the gate terminal of the JFET with the transistor exhibiting saturation conditions. 30. (a) V GS 0 V, I D I DSS 8 ma V GS V P +4 V, I D 0 ma V P V GS +2 V, ID 2 ma 2 V GS 0.3V P 1.2 V, I D 4 ma V GS I D R S I D 4 ma; V GS (4 ma)(0.51 kω) 2.04 V I 3 ma, V 1.55 V D Q GS Q (b) V DS V DD + I D (R D + R S ) 18 V + (3 ma)(2.71 kω) 9.87 V (c) V D V DD I D R D 18 V (3 ma)(2.2 kω) 11.4 V 107

111 I D (on) 31. k ( V V ) ( 7 V ( 3 V) ) GS (on) GS ( Th) A/V 2 I D (V GS + 3 V) 2 4 ma 4 ma ( 4 V) V GS 3 V 4 V 5 V 6 V 7 V 8 V I D 0 ma 0.25 ma 1 ma 2.25 ma 4 ma 6.25 ma V GS V DS V DD + I D R D At I D 0 ma, V GS V DD 16 V VDD 16 V At V GS 0 V, I D R 2 kω 8 ma D (b) V DS V GS 7.25 V (c) V D V DS 7.25 V or V DS V DD + I D R D 16 V + (4.4 ma)(2 kω) 16 V V V DS 7.2 V V D 32. VGS 1.5 V VP 4 V Find on the horizontal axis. Then move vertically to the I D I DSS (1 V GS /V P ) 2 curve. Finally, move horizontally from the intersection with the curve to the left to the I D /I DSS axis. I D 0.39 IDSS and I D 0.39(12 ma) 4.68 ma vs ma (#1) V V DD I D R D 12 V (4.68 ma)(1.2 kω) DS Q 6.38 V vs V (#1) 108

112 VP 4 V 33. m IDSS R S (10 ma)(0.75 k Ω) VGG 0.533(0) M m V 4 V P 0 Draw a straight line from M 0 through m until it crosses the normalized curve of I D 2 V GS I DSS 1. At the intersection with the curve drop a line down to determine VP VGS V 0.49 P so that V GS Q 0.49V P 0.49(4 V) 1.96 V (vs. 1.9 V #6) If a horizontal line is drawn from the intersection to the left vertical axis we find I D 0.27 IDSS and I D 0.27(I DSS ) 0.27(10 ma) 2.7 ma (vs. 2.7 ma from #6) (a) V GS Q 1.96 V, I D Q 2.7 ma (b) (c) (d) V DS V DD I D (R D + R S ) V (like #6) V D V DD I D R D V (like #6) V G 0 V, V S I D R S 2.03 V (like #6) RV DD k Ω(20 V) 34. V GG R1 + R2 110 kω+ 910 kω 2.16 V VP 3.5 V m IDSS R S (10 ma)(1.1 k Ω ) VGG (2.16 V) M m V P Find on the vertical axis labeled M and mark the location. Move horizontally to the vertical axis labeled m and then add m to the vertical height ( in total) mark the spot. Draw a straight line through the two points located above, as shown below. 109

113 Continue the line until it intersects the I D I DSS (1 V GS /V P ) 2 curve. At the intersection move horizontally to obtain the I D /I DSS ratio and move down vertically to obtain the V / V ratio. GS p I I D DSS 0.33 and I D Q 0.33(10 ma) 3.3 ma vs. 3.3 ma (#12) VGS V and V GS 0.425(3.5 V) Q P 1.49 V vs. 1.5 V (#12) VP 6 V 35. m IDSS R S (6 ma)(2.2 k Ω) VGG (4 V) M m V (6 V) P Find on the vertical M axis. Draw a horizontal line from M to the vertical m axis. Add to the vertical location on the m axis defined by the horizontal line. Draw a straight line between M and the point on the m axis resulting from the addition of m Continue the straight line as shown below until it crosses the normalized I D I DSS (1 V GS /V P ) 2 curve: 110

114 At the intersection drop a vertical line to determine VGS V 0.34 P and V GS Q 0.34(6 V) 2.04 V (vs. 2 V from problem 15) At the intersection draw a horizontal line to the I D /I DSS axis to determine I D 0.46 I DSS and I D Q 0.46(6 ma) 2.76 ma (vs. 2.7 ma from problem 15) (a) I D Q 2.76 ma, V GS Q 2.04 V (b) V DS V DD + V SS I D (R D + R S ) 16 V + 4 V (2.76 ma)(4.4 kω) 7.86 V (vs V from problem 15) V S V SS + I D R S 4 V + (2.76 ma)(2.2 kω) 4 V V 2.07 V (vs V from problem 15) 111

115 Chapter 8 1. g m0 2I DSS 2(15 ma) V 5 V P 6 ms 2. g m0 2IDSS 2IDSS 2(12 ma) VP 2.4 V V g 10 ms P V P 2.4 V m0 3. g m0 2 I DSS V P I DSS ( g )( ) mo VP 5 ms(3.5 V) 8.75 ma 2 2 VGS 2(12 ma) 1 V 4. g m 0 1 Q gm 1 V P 3 V 3 V 5.3 ms 5. g m 2 I V DSS GS 1 Q V P V P 6 ms 2 I 1 1 V DSS 2.5 V 2.5 V I DSS 12.5 ma 6. g m g 0 m I D 2 IDSS IDSS /4 2(10 ma) 1 I V I 5 V 4 DSS P DSS 20 ma 1 5 V 2 2 ms 7. g m0 2I DSS 2(8 ma) 3.2 ms V 5 V P VGS /4 g m 0 1 Q V P gm 3.2mS 1 V P VP 2.4 ms ms ms (a) g m y fs 4.5 ms (b) r d μS 40 kω yos 9. g m y fs 4.5 ms 1 1 r d 25μS 40 kω yos Z o r d 40 kω A v (FET) g m r d (4.5 ms)(40 kω)

116 10. A v g m r d g m Av r d ( 200) (100 k Ω ) 2 ms 11. (a) g m0 2I DSS 2(10 ma) 4 ms V 5 V P (b) g m ΔI ΔV D GS 6.4 ma 3.6 ma 2 V 1 V 2.8 ms VGS 1.5 V (c) Eq. 8.6: g m 0 1 Q gm 4 ms 1 V P 5 V 2.8 ms (d) g m ΔI ΔV D GS 3.6 ma 1.6 ma 3 V 2 V 2 ms VGS 2.5 V (e) g m 0 1 Q gm 4 ms 1 V P 5 V 2 ms 12. (a) r d ΔV ΔI DS D VGS constant (15 V 5 V) 10 V (9.1 ma 8.8 ma) 0.3 ma kω (b) At V DS 10 V, I D 9 ma on V GS 0 V curve g m0 2 I DSS 2(9 ma) 4.5 ms V 4 V P 13. From 2N4220 data: g m y fs 750 μs 0.75 ms 1 1 r d 100 kω 10μS yos 2I DSS 2(8 ma) 14. (a) g m (@ V GS 6 V) 0, g m (@ V GS 0 V) g m ms VP 6 V (b) g m (@ I D 0 ma) 0, g m (@ I D I DSS 8 ma) g m ms 15. g m y fs 5.6 ms, r d kω 15 μs yos 16. g m r d 2I VGS 2(10 ma) 2 V 1 Q DSS 1 V P V P 4 V 4 V kω 25 μs yos 2.5 ms 113

117 17. Graphically, V GS Q 1.5 V 2I VGS 2(10 ma) 1.5 V g m 1 Q DSS 1 V P V P 4 V 4 V Z i R G 1 MΩ Z o R D r d 1.8 kω 40 kω 1.72 kω A v g m (R D r d ) (3.125 ms)(1.72 kω) ms 18. V GS Q 1.5 V 2I VGS 2(12 ma) 1.5 V g m 1 Q DSS 1 V P V P 6 V 6 V Z i R G 1 MΩ 1 1 Z o R D r d, r d yos 25 kω 40 μs 1.8 kω 25 kω 1.68 kω A v g m (R D r d ) (3 ms)(1.68 kω) ms 19. g m y fs 3000 μs 3 ms 1 1 r d 50 μs 20 kω yos Z i R G 10 MΩ Z o r d R D 20 kω 3.3 kω 2.83 kω A v g m (r d R D ) (3 ms)(2.83 kω) V GS Q 0 V, g m g m0 2I DSS 2(6 ma) 2 ms, r d V 6 V Z i 1 MΩ Z o r d R D 25 kω 2 kω kω A v g m (r d R D ) (2 ms)(1.852 kω) 3.7 P kω 40 μs yos 114

118 21. g m 3 ms, r d 20 kω Z i 10 MΩ RD 3.3 kω Z o RD + RS 3.3 kω+ 1.1 kω 1+ gmrs (3 ms)(1.1 k Ω ) + r 20 kω 3.3 kω 3.3 kω 730 Ω d gmrd (3 ms)(3.3 k Ω) A v RD + RS 3.3 kω+ 1.1 kω 1+ gmrs (3 ms)(1.1 k Ω ) + rd 20 kω g m y fs 3000 μs 3 ms 1 1 r d 100 kω 10 μs yos Z i R G 10 MΩ (the same) Z o r d R D 100 kω 3.3 kω kω (higher) A v g m (r d R D ) (3 ms)(3.195 kω) 9.59 (higher) 23. V GS Q 0.95 V g m 2 I V DSS GS 1 Q V P V P 2(12 ma) 0.95 V 1 3 V 3 V 5.47 ms Z i 82 MΩ 11 MΩ 9.7 MΩ Z o r d R D 100 kω 2 kω 1.96 kω A v g m (r d R D ) (5.47 ms)(1.96 kω) V o A v V i ( 10.72)(20 mv) mv 24. V GS Q 0.95 V (as before), g m 5.47 ms (as before) Z i 9.7 MΩ as before RD Z o RD + R 1+ gmrs + r but r d 10(R D + R S ) d S 115

119 RD 2 kω 2 kω 2 kω Z o 1+ gmrs 1 + (5.47 ms)(0.61 k Ω ) Ω gmrd A v since r d 10(R D + R S ) 1 + gmrs (5.47 ms)(2 k Ω ) (a big reduction) (from above) V o A v V i ( 2.52)(20 mv) mv (compared to mv earlier) V GS Q 0.95 V, g m (problem 23) 5.47 ms Z i (the same) 9.7 MΩ Z o (reduced) r d R D 20 kω 2 kω 1.82 kω A v (reduced) g m (r d R D ) (5.47 ms)(1.82 kω) 9.94 V o (reduced) A v V i ( 9.94)(20 mv) mv V GS Q 0.95 V (as before), g m 5.47 ms (as before) Z i 9.7 MΩ as before RD Z o RD + R 1+ gmrs + r d S since r d < 10(R D + R S ) 2 kω 2 kω kω 1 + (5.47 ms)(0.61 k Ω ) + 20 kω 2 kω 2 kω Ω (slightly less than Ω obtained in problem 24) gmrd A v R 1+ g R + m S D + R r d S (5.47 ms)(2 k Ω) 2 kω kω 1 + (5.47 ms)(0.61 k Ω ) + 20 kω slightly less than 2.52 obtained in problem 24) I VGS 2(9 ma) 2.85 V V GS Q 2.85 V, g m 1 Q DSS 1 V P V P 4.5 V 4.5 V Z i R G 10 MΩ Z o r d R S 1/g m 40 kω 2.2 kω 1/1.47 ms Ω Ω gm( rd RS) (1.47 ms)(40 kω 2.2 k Ω) A v 1 + g ( r R ) 1 + (1.47 ms)(40 kω 2.2 k Ω ) m d S 1.47 ms 116

120 28. V GS Q 2.85 V, g m 1.47 ms Z i 10 MΩ (as in problem 27) Z o r d R S 1/g m 20 kω 2.2 kω Ω Ω < Ω (#27) kω gm( rd RS) 1.47 ms( 20 kω 2.2 k Ω) A v 1 + g ( r R ) ms(20 kω 2.2 k Ω ) m d S < (#27) 29. V GS Q 3.8 V 2I VGS 2(6 ma) 3.8 V g m 1 Q DSS 1 V P V P 6 V 6 V ms The network now has the format examined in the text and Z i R G 10 MΩ Z o r d R S 1/ g m 33.3 kω 3.3 kω 1/0.66 ms 3 kω 1.52 kω 1 kω r d r d + R D 30 kω kω 33.3 kω gmrd (0.733 ms)(30 k Ω) g m r + R 30 kω+ 3.3 kω 33.3 kω d D 0.66 ms g m( r d RS) 0.66 ms(3 k Ω) A v 1 + g ( r R ) ms(3 k Ω ) m d S 30. GS Q V 1.75 V, g m 2.14 ms r d 10R D, Z i R S 1/g m 1.5 kω 1/2.14 ms 1.5 kω Ω Ω r d 10R D, Z o R D 3.3 kω r d 10R D, A v g m R D (2.14 ms)(3.3 kω) 7.06 V o A v V i (7.06)(0.1 mv) mv 117

121 I VGS 2(8 ma) 1.75 V V GS Q 1.75 V, g m 1 Q DSS ms V P V P 2.8 V 2.8 V rd + R D 25 kω kω 28.3 kω Z i R S 1.5 kω 1.5 k 1 gmr Ω d 1 (2.14 ms)(25 k ) + + Ω kω 0.52 kω Ω Z o R D r d 3.3 kω 25 kω 2.92 kω gmrd + RD / rd (2.14 ms)(3.3 k Ω ) k Ω/ 25 kω A v 1 + R / r k Ω/ 25 kω D d V o A v V i (6.36)(0.1 mv) mv V GS Q 1.2 V, g m 2.63 ms r d 10R D, Z i R S 1/g m 1 kω 1/2.63 ms 1 kω Ω Ω Z o R D 2.2 kω A v g m R D (2.63 ms)(2.2 kω) r d y os 20 μs 50 kω, V GS Q 0 V g m g m0 2 I DSS 2(8 ma) 5.33 ms VP 3 A v g m R D (5.33 ms)(1.1 kω) V o A v V i ( 5.863)(2 mv) mv 34. V GS Q 0.75 V, g m 5.4 ms Z i 10 MΩ r o 10R D, r o 10R D, Z o R D 1.8 kω A v g m R D (5.4 ms)(1.8 kω) Z i 10 MΩ Z o r d R D 25 kω 1.8 kω 1.68 kω A v g m (r d R D ) 2I VGS 2(12 ma) 0.75 V g m 1 Q DSS 1 V P V P 3.5 V 3.5 V A v (5.4 ms)(1.68 kω) ms 118

122 36. g m y fs 6000 μs 6 ms 1 1 r d 35 μs kω yos r d 10R D, A v g m (r d R D ) (6 ms)(28.57 kω 6.8 kω) V o A v V i ( 32.94)(4 mv) mv 5.49 kω 37. Z i 10 MΩ 91 MΩ 9 MΩ 2I VGS 2(12 ma) 1.45 V g m 1 Q DSS ms V P V P 3 V 3 V Z o r d R S 1/g m 45 kω 1.1 kω 1/4.13 ms kω Ω Ω gm( rd RS) (4.13 ms)(45 kω 1.1 k Ω) A v 1 + gm( rd RS) 1 + (4.13 ms)(45 kω 1.1 k Ω) (4.13 ms)(1.074 k Ω) (4.13 ms)(1.074 k Ω ) g m 2kV ( GS V ( )) Q GS Th 2( )(8 V 3 V) 3 ms 39. V GS Q 6.7 V g m 2kV ( ) GS V Q T 2( )(6.7 V 3 V) 2.22 ms RF + rd RD 10 MΩ+ 100 kω 2.2 kω Z i 1 + gm( rd RD) 1 + (2.22 ms)(100 kω 2.2 k Ω) 10 MΩ kω 1.73 MΩ ms(2.15 k Ω) Z o R F r d R D 10 MΩ 100 kω 2.2 kω 2.15 kω A v g m (R F r d R D ) 2.22 ms(2.15 kω)

123 40. g m 2kV ( GS V) Q T 2( )(6.7 V 3 V) 1.48 ms RF + rd RD 10 MΩ+ 100 kω 2.2 kω Z i 1 + g ( r R ) 1 + (1.48 ms)(100 kω 2.2 k Ω) m d D 10 MΩ kω 2.39 MΩ > 1.73 MΩ (#39) 1 + (1.48 ms)(2.15 k Ω ) 41. Z o R F r d R D 2.15 kω 2.15 kω (#39) A v g m (R F r d R D ) (1.48 ms)(2.15 kω) < 4.77 (#39) V 5.7 V, g GS m ( ) Q 2kVGS V Q T 2( )(5.7 V 3.5 V) 1.32 ms 1 r d kω 30 μ S A v g m (R F r d R D ) 1.32 ms(22 MΩ kω 10 kω) V o A v V i ( 10.15)(20 mv) 203 mv 42. I D k(v GS V T ) 2 I D(on) 4 ma k ( VGS (on) VT ) (7 V 4 V) g m 2 kv ( GS VGS ( Th) ) 2( )(7 V 4 V) Q 2.66 ms 43. A v g m (R F r d R D ) (2.66 ms)(22 MΩ 50 kω 10 kω) kω V o A v V i ( 22.16)(4 mv) mv V GS Q 4.8 V, g m 2kV ( GS V ) Q GS( Th) 8.33 kω 2( )(4.8 V 3 V) 1.44 ms A v g m (r d R D ) (1.44 ms)(40 kω 3.3 kω) 4.39 V o A v V i ( 4.39)(0.8 mv) 3.51 mv 120

124 r d y os 25 μs 40 kω 2I DSS 2(8 ma) V GS Q 0 V, g m g m0 6.4 ms VP 2.5 V A v g m (r d R D ) 8 (6.4 ms)(40 kω R D ) 8 40 kω RD 1.25 kω 6.4 ms 40 kω+ RD and R D 1.29 kω Use R D 1.3 kω VGS V Q P ( 3 V) 1 V VGS Q 1 V ID I 1 12 ma 1 Q DSS 5.33 ma V P 3 V VS 1 V R S Ω Use R S 180 Ω I D 5.33 ma Q 2I VGS 2(12 ma) 1 V g m 1 Q DSS ms V P V P 3 V 3 V A v g m (R D r d ) or R D 40 kω kω 5.33 ms RD 40 kω kω RD + 40 kω 40 kωr D kωr D kω R D kω R D 1.97 kω R D 2 kω 121

125 Chapter 9 1. (a) 3, 1.699, (b) 6.908, 3.912, (c) results differ by magnitude of (a) log (b) log e ( ) 2.3 log 10 ( ) (c) log e ( ) (a) same (b) same (c) same Po (a) db 10 log 10 P 10 log 100 W 10 i 5 W 10 log (1.301) db (b) db 10 log mw 5 mw 10 log (1.301) db (c) db 10 log 100 μ W μw db 10 log (0.6987) 5. dbm P2 25 W G 10 log log10 1 mw 600 Ω 1 mw dbm Ω V2 6. G db 20 log 10 V 20 log 100 V V 20 log (0.6021) db V2 25 V 7. G db 20 log log10 V 20 log mv 20(3.398) db 8. (a) Gain of stage 1 A db Gain of stage 2 2 A db Gain of stage A db A + 2A +2.7A 120 A db 122

126 Vo 1 (b) Stage 1: A v db 20 log 10 Vi Vo log Vi 1 V o1 Vi 1 Vo 1 and V i1 Vo 2 Stage 2: A v db 20 log 10 Vi 2 Vo log 10 Vi 2 V o2 Vi 2 Vo 2 and V i2 Vo 3 Stage 3: : A v db 20 log 10 Vi 3 Vo log 10 Vi 3 V o3 Vi 3 Vo 3 and V i3 Av A T v A 1 v A 2 V (11.288)(127.35)( ) 99, ? A T 120 db 20 log 10 99, db db (difference due to level of accuracy carried through calculations) P2 9. (a) G db 20 log 10 P 1 48 W 10 log db 5 μ W V PR o o o 20 log 10 (48 W)(40 k Ω) (b) G v 20 log log10 Vi Vi 100 mv db 123

127 (c) R i (d) P o V i P (100 mv) 2 kω 5 μw Vo R V o PR o o (48 W)(40 k Ω ) V o 10. (a) Same shape except A v 190 is now level of 1. In fact, all levels of A v are divided by 190 to obtain normalized plot (190) defining cutoff frequencies at low end f Hz (remember this is a log scale) at high end f khz (b) 11. (a) A v Vo 1 Vi 1 + ( f / f ) f 1 2π RC 2 π(1.2 k Ω)(0.068 μf) Hz A v Hz 1+ f 2 (b) A V db 100 Hz: A v khz: A v khz: A v khz: A v khz: A v (c) f Hz (d)(e) 124

128 1 12. (a) f 1 2π RC θ tan 1 f1 f 1.95 khz 1 tan 1.95 khz f (b) f θ tan khz f 100 Hz khz khz khz khz (c) f 1 1 2π RC 1.95 khz (d) First find θ 45 at f khz. Then sketch an approach to 90 at low frequencies and 0 at high frequencies. Use an expected shape for the curve noting that the greatest change in θ occurs near f 1. The resulting curve should be quite close to that plotted above. 13. (a) 10 khz (b) 1 khz (c) 20 khz 10 khz 5 khz (d) 1 khz 10 khz 100 khz 125

129 14. From example 9.9, r e Ω RC RL ro 4 k 2.2 k 40 k A v Ω Ω Ω r Ω e (vs. 90 for Ex. 9.9) f L s f L C : r o does not affect R i f L s 1 2 π ( R + R ) C s i S π( Ro + RL) CC 2 π( RC ro + RL) CC R C r o 4 kω 40 kω kω 1 2 π (5.636 kω+ 2 k Ω)(1 μf) Hz (vs Hz for Ex. 9.9) f LC the same 6.86 Hz f L E : R e not affected by r o, therefore, f L E Hz is the same. 2π R C In total, the effect of r o on the frequency response was to slightly reduce the mid-band gain. e E 15. (a) βr E 10R 2 (120)(1.2 kω) 10(10 kω) 144 kω 100 kω (checks!) 10 k Ω(14 V) V B 10 kω+ 68 kω V V E V B V BE V 0.7 V V VE V I E R ma 1.2 kω r e E 26 mv 26 mv Ω ma I E (b) A Vmid ( RL RC) (3.3 kω 5.6 k Ω) r Ω e (c) Z i R 1 R 2 βr e 68 kω 10 kω (120)(28.48 Ω) kω kω 126

130 (d) (e) Vo Vo Vi Av s Vs Vi Vs Vi Zi kω Vs Zi + Rs kω kω 0.75 A v s ( 72.91)(0.75) fl S 2 π ( Rs + Ri) Cs 2 π(0.82 kω k Ω)(0.47 μf) Hz 1 1 f L C 2 π ( Ro + RL) CC 2 π(5.6 kω+ 3.3 k Ω)(0.47 μf) Hz 1 R s f L E : R e R E + re 2π ReCE β R s R s R 1 R kω 68 kω 10 kω Ω Ω R e 1.2 kω Ω kω Ω Ω f L E 1 1 2π RC e E 2 π(33.75 Ω)(20 μf) Hz (f) f 1 f L E Hz (g)(h) 127

131 VCC VBE 20 V 0.7 V 19.3 V 16. (a) I B RB + ( β + 1) RE 470 k Ω+ (111)(0.91 k Ω) 470 kω kω 33.8 μa I E (β + 1)I B (111)(33.8 μa) ma 26 mv r e ma 6.93 Ω (b) A vmid Vo ( RC RL) (3 kω 4.7 k Ω) kω V r 6.93 Ω 6.93 Ω i e (c) Z i R B βr e 470 kω (110)(6.93 Ω) 470 kω Ω Ω (d) (e) (f) A Z Ω A ( ) Ω+ 0.6 kω i vs ( mid) vmid Zi Rs 1 1 f L S 2 π ( RS + Zi) CS 2 π(600 Ω Ω)(1 μf) Hz 1 1 f L C 2 π ( Ro + RL) CC 2 π(3 kω+ 4.7 k Ω)(1 μf) Hz 1 R s f Re RE + r L E e 2π R β ece 1 Rs R B 0.91 kω + re 2 π (12.21 Ω)(6.8 μf) β khz 0.6 kω 470 kω 0.91 kω Ω 110 f 1 f L E khz 910 Ω Ω Ω (g, h) 128

132 17. (a) βr E 10R 2 (100)(2.2 kω) 10(30 kω) 220 kω 300 kω (No!) R Th R 1 R kω 30 kω 24 kω 30 k Ω(14 V) E Th 30 kω+ 120 kω 2.8 V ETh VBE 2.8 V 0.7 V I B R + ( β + 1) R 24 kω kω Th 8.53 μa I E (β + 1)I B (101)(8.53 μa) 0.86 ma 26 mv 26 mv r e Ω 0.86 ma I E E (b) A v mid RE RL r + R R e E L 2.2 kω 8.2 kω Ω+ 2.2 kω 8.2 kω (c) Z i R 1 R 2 β(r e + R E ) R E R E R L 2.2 kω 8.2 kω kω 120 kω 30 kω (100)(30.23 Ω kω) kω (d) Vo Vo Vi A v s V V V s i s Vi Zi kω V Z + R kω+ 1 kω s i s (e) f f L S L C 1 2 π ( Rs + Ri) Cs 1 2 π (1 kω k Ω)(0.1 μf) Hz 1 2 π ( R + R ) C o L C R s R o R E + re β 0.96 kω (2.2 kω) Ω Ω f LC 1 2 π (39.12 Ω+ 8.2 k Ω)(0.1 μf) Hz R R R R s s kω 120 kω 30 kω 0.96 kω 129

133 (f) f 1 low Hz (g)(h) 18. (a) I E r e V EE V R E EB 4 V 0.7 V 2.75 ma 1.2 kω 26 mv 26 mv 9.45 Ω 2.75 ma I E (b) RC R A v mid re L 3.3 kω 4.7 kω 9.45 Ω (c) Z i R E r e 1.2 kω 9.45 Ω 9.38 Ω (d) (e) Zi 9.38 Ω(205.1) A v s (mid) Av mid Zi + Rs 9.38 Ω+ 100 Ω f L s 2 π ( Rs + Zi) Cs 2 π(100 Ω Ω)(10 μf) Hz 1 1 f L C 2 π ( Ro + RL) CE 2 π(3.3 kω+ 4.7 k Ω)(10 μf) Hz (f) f f L s Hz (g, h) 130

134 19. (a) V GS I D R S I D I DSS V V 1 GS P 2 V GSQ I DQ 2.45 V 2.1 ma (b) g m0 2 I V DSS P 2(6 ma) 2 ms 6 V VGS ( 2.45 V) g m 0 1 Q gm 2 ms 1 V P ( 6 V) 1.18 ms (c) A v mid g m (R D R L ) 1.18 ms(3 kω 3.9 kω) 1.18 ms( kω) 2 (d) Z i R G 1 MΩ (e) A v s A v 2 (f) f L G π ( R + R ) C 2 π(1 kω+ 1 M Ω)(0.1 μf) sig 1.59 Hz i G f f L C 1 2 π ( Ro + RL) CC 1 2 π (3 kω+ 3.9 k Ω)(4.7 μf) 4.91 Hz 1 L S Req 2π ReqCS 1 2 π ( Ω)(10 μf) Hz 1 1 RS 1.2 kω 1.2 kω Ω g 1.18 ms m Ω (g) f 1 f L S 32 Hz (h, i) 131

135 20. (a) same as problem 19 V 2.45 V, GS Q I D Q 2.1 ma (b) g m0 2 ms, g m 1.18 ms (r d has no effect!) (c) A v mid g m (R D R L r d ) 1.18 ms(3 kω 3.9 kω 100 kω) 1.18 ms (1.67 kω) (vs. 2 for problem 19) (d) Z i R G 1 MΩ (the same) (e) (f) A v s (mid) Z 1 MΩ ( A ) Z vs. 2 for problem 19 i v mid i + Rsig 1 MΩ+ 1 kω ( 1.971) f L G 1.59 Hz (no effect) f L C : R o R D r d 3 kω 100 kω 2.91 kω 1 1 f L C 2 π ( Ro + RL) CC 2 π(2.91 kω+ 3.9 k Ω)(4.7 μf) 4.97 Hz vs Hz for problem 19 RS f L S : R eq 1 + RS (1 + gmrd )/( rd + ( RD RL )) 1.2 kω 1 + (1.2 k Ω )(1 + (1.18 ms)(100 k Ω)) /(100 kω+ 3 kω 3.9 k Ω) 1.2 k Ω Ω 1 1 f L S : 2π ReqC S 2 π(499.2 Ω)(10 μf) Hz vs for problem 19. Effect of r d 100 kω insignificant! 21. (a) V G 68 k Ω(20 V) 68 kω+ 220 kω 4.72 V V GS V G I D R S V GS 4.72 V I D (2.2 kω) V I D I DSS (1 V GS /V P ) 2 (b) g m0 2 I V DSS P GSQ I DQ 2(10 ma) 3.33 ms 6 V 2.55 V 3.3 ma V GS ( 2.55 V) g m gm ms 1 VP 6 V 1.91 ms 132

136 (c) A v mid g m (R D R L ) (1.91 ms)(3.9 kω 5.6 kω) 4.39 (d) Z i 68 kω 220 kω kω (e) (f) Vo Vi A v s (mid) V V V i s Z Ω kω+ 1.5 kω i V i k s Zi Rs A ( 4.39)(0.972) 4.27 f v s (mid) L G π ( R + R ) C 2 π(1.5 kω k Ω)(1 μf) sig 2.98 Hz i G f L C π ( Ro + RL) C C 2 π(3.9 kω+ 5.6 k Ω)(6.8 μf) 2.46 Hz f L S 1 2π R C eq S 1 2 π (388.1 Ω)(10 μf) 41 Hz R eq R S 1 g m kω 1.91 ms 1.5 kω Ω Ω (g) f 1 f L S 41 Hz (h, i) 133

137 22. (a) f H i 1 π R C 2 Th1 i 1 2 π ( Ω)( pf) khz f H o 1 π R C 2 Th2 o 1 2 π (2.08 k Ω)(28 pf) 2.73 MHz R R R R R Th1 s 1 2 i 0.82 kω 68 kω 10 kω kω 0.81 kω kω Ω C i CW + C (1 ) 1 be + Cbc Av 5 pf + 40 pf + 12 pf(1 ( 72.91)) pf Prob. 15 R Th 2 R C R L 5.6 kω 3.3 kω 2.08 kω C o CW + C o ce + CMo 8 pf + 8 pf + 12 pf 28 pf 1 (b) f β 2 πβ r ( C + C ) (c) mid e be bc 1 2 π (120)(28.48 Ω)(40 pf + 12 pf) khz Prob. 15 f T βf β (120)( khz) MHz 23. (a) f H i 1 2π R C Th1 i R Th 1 R s R B R i VCC VBE 20 V 0.7 V R i : I B R + ( β + 1) R 470 k Ω+ (111)(0.91 k Ω) B 33.8 μa E I E (β + 1)I B ( )(33.8 μa) 3.75 ma 26 mv 26 mv r e 6.93 Ω I E 3.75 ma R i βr e (110)(6.93 Ω) Ω R Th 1 R s R B R i 0.6 kω 470 kω Ω Ω 134

138 f H i C i : C i C A v : 1 2 π ( Ω)( ) Wi A v mid be C i + C + (1 A v )C bc ( RL RC) (4.7 kω 3 k Ω) r 6.93 Ω e C i 7 pf + 20 pf + (1 ( 264.2)6 pf 1.62 nf f H i 1 2 π ( Ω)(1.62 nf) 293 khz 1 f H o 2π RTh C 2 o R R C R L 3 kω 4.7 kω kω Th 2 C o C + C + C Wo ce Mo C f C bc 11 pf + 10 pf + 6 pf 27 pf 1 f H o (b) f β (c) 2 π (1.831 k Ω)(27 pf) 3.22 MHz 1 2 πβ r ( C + C ) mid e be bc 1 2 π (110)(6.93 Ω)(20 pf + 6 pf) 8.03 MHz f T β mid f β (110)(8.03 MHz) MHz 135

139 24. (a) f H i 1 π R C 2 Th1 i 1 2 π (955 Ω)(58 pf) 2.87 MHz f H o 1 π R C 2 Th2 o 1 2 π (38.94 Ω)(32 pf) MHz R R R R Z Th1 s 1 2 b Z b βr e + (β + 1)(R E R L ) (100)(30.23 Ω) + (101)(2.2 kω 8.2 kω) kω kω kω R Th 1 1 kω 120 kω 30 kω kω 955 Ω C i CW + C i be + Cbc (No Miller effect) 8 pf + 30 pf + 20 pf 58 pf 24 kω R1 R2 R3 R Th 2 R E R L re + β 24 kω 1 kω 2.2 kω 8.2 kω Ω kω (30.23 Ω Ω) kω Ω Ω C o CW + C o ce 10 pf + 12 pf 32 pf (b) f β (c) 1 2 πβ r ( C + C ) mid e be bc 1 2 π (100)(30.23 Ω)(30 pf + 20 pf) 1.05 MHz f T β mid f β 100(1.05 MHz) 105 MHz 136

140 25. (a) f H i 1 π R C 2 Th1 i R Th 1 R s R E R i VEE VBE 4 V 0.7 V R i : I E 2.75 ma RE 1.2 kω 26 mv 26 mv r e 9.45 Ω I E 2.75 ma R i R E r e 1.2 kω 9.45 Ω 9.38 Ω C i : C i C Wi + C (no Miller cap-noninverting!) be 8 pf + 24 pf 32 pf R i 0.1 kω 1.2 kω 9.38 Ω 8.52 Ω f H i f H o (b) f β (c) C o C MHz 2 π (8.52 Ω)(32 pf) 1 R Th R C R L 3.3 kω 4.7 kω 1.94 kω R C 2 2π Th2 o Wo + C + (no Miller) bc 10 pf + 18 pf 28 pf 1 f H o 2 π (1.94 k Ω)(28 pf) 2.93 MHz 1 2 πβ r ( C + C ) mid e be bc 1 2 π (80)(9.45 Ω)(24 pf + 18 pf) 5.01 MHz f T β mid f β (80)(5.01 MHz) MHz 137

141 26. (a) From problem 19 g m0 2 ms, g m 1.18 ms (b) From problem 19 A A 2 vmid v s (mid) (c) (d) f H i f Hi 1 2π R C Th1 1 2 π (999 Ω)(21 pf) 7.59 MHz f H o 1 π R C 2 Th2 o i 1 2 π (1.696 k Ω)(12 pf) 7.82 MHz R Th 1 R sig R G 1 kω 1 MΩ 999 Ω C i C + C + C Wi gs Mi C M i (1 A v )C gd (1 ( 2)4 pf 12 pf C i 3 pf + 6 pf + 12 pf 21 pf R Th 2 R D R L 3 kω 3.9 kω kω C o C + C + C Wo ds Mo 1 C M o 1 4 pf 2 (1.5)(4 pf) 6 pf C o 5 pf + 1 pf + 6 pf 12 pf 2I DSS 2(10 ma) 27. (a) g m ms VP 6 V From problem #21 V GS Q 2.55 V, I D Q 3.3 ma VGS g m 0 1 Q 2.55 V gm 3.33 ms 1 V 1.91 ms P 6 V 138

142 (b) A v mid g m (R D R L ) (1.91 ms)(3.9 kω 5.6 kω) 4.39 Z i 68 kω 220 kω kω Vi Zi kω Vs Zi + Rsig kω+ 1.5 kω A v s ( 4.39)(0.972) (mid) 4.27 (c) f H i 1 Th 2π RTh C 1 1 i R R sig R 1 R kω kω 1.46 kω C i C + C + (1 A ) C Wi gs v gd 4 pf + 12 pf + (1 ( 4.39))8 pf pf 1 f H i 2 π (1.46 k Ω)(59.12 pf) 1.84 MHz f H o 1 Th2 2π RTh C 2 o 1 C o C + C + 1 C o Av W ds gd 1 6 pf + 3 pf pf ( 4.39) pf 1 f H o 2 π (2.3 k Ω)(18.82 pf) 3.68 MHz R R D R L 3.9 kω 5.6 kω 2.3 kω (d) 139

143 28. A v T Av Av Av Av 4 A v (20) f ( 1/ n 2 1 ) f2 ( 1/4 ) 2 1 (2.5MHz) (2.5 MHz) 1.09 MHz f1 40 Hz 30. f 1 1/ n 1/ Hz Hz 31. (a) v 4 π V 1 1 m sin 2π fst+ sin 2 π(3 fs) t+ sin 2 π(5 fs) t sin 2 π(7 fs) t+ sin 2 π(9 fs) t (sin 2 π( ) t+ sin 2 π( ) t sin 2 π( ) t+ sin 2 π( ) t+ sin 2 π( ) t) (b) BW 0.35 t r μs 500 khz At 90% or 81 mv, t 0.75 μs At 10% or 9 mv, t 0.05 μs t r 0.75 μs 0.05 μs 0.7 μs V V 90 mv 80 mv (c) P V 90 mv P (0.111)(100 khz) f L f o s π π 3.53 khz 140

144 Chapter 10 RF 250 k Ω 1. V o V 1 (1.5 V) R 20 kω V V 2. A v V o i R R For R 1 10 kω: 500 kω A v 10 kω 50 For R 1 20 kω: 500 kω A v 20 kω 25 R f 1 MΩ 3. V o V 1 R 20 kω V 1 2 V 1 F 1 V 1 2 V mv RF 200 kω 4. V o V 1 V 1 R 20 kω 1 10 V 1 For V V: V o 10(0.1 V) 1 V For V V: V o 10(0.5 V) 5 V V o ranges from 1 V to 5 V R F 360 kω 5. V o 1+ V ( 0.3 V) R1 12 kω 31( 0.3 V) 9.3 V R F 360 kω 6. V o 1+ V 1 1+ V 1 R1 12 kω V V mv V 141

145 R F 7. V o 1+ V 1 R1 For R 1 10 kω: 200 kω V o 1 + (0.5 V) 21(0.5 V) 10.5 V 10 kω For R 1 20 kω: 200 kω V o 1+ (0.5 V) 11(0.5 V) 5.5 V 20 kω V o ranges from 5.5 V to 10.5 V. Rf Rf Rf 8. V o V1 + V2 + V3 R1 R2 R3 330 k 330 k 330 k Ω (0.2 V) + Ω ( 0.5 V)+ Ω (0.8 V) 33 kω 22 kω 12 kω [10(0.2 V) + 15( 0.5 V) (0.8 V)] [2 V + ( 7.5 V) V] [24 V 7.5 V] 16.5 V RF RF R F 9. V o V1 + V2 + V3 R1 R2 R3 68 kω 68 kω 68 kω (0.2 V)+ ( 0.5 V) + ( V) 33 kω 22 kω 12 kω [0.41 V 1.55 V V] 3.39 V v o (t) v1 () t dt RC dt (200 k Ω)(0.1 μf) 50(1.5t) 75t 11. V o V V R f 100 kω 12. V o V 1 (1.5 V) R 20 kω 1 5(1.5 V) 7.5 V 13. V 2 V kω (0.2 V) 20 kω 2 V 200 kω 1 + (0.2 V) +4.2 V 10 kω 142

146 400 kω 100 kω 100 kω 14. V o 1 + (0.1 V) + (0.1 V) 20 kω 20 kω 10 kω (2.1 V)( 5) + ( 10)(0.1 V) 10.5 V 1 V 11.5 V 600 k 600 k 300 k 15. V o Ω (25 mv) + Ω ( 20 mv) Ω 15 k 30 k Ω Ω 30 kω 300 kω + ( 20 mv) 15 kω [40(25 mv) + (20)( 20 mv)]( 10) + ( 20)( 20 mv) [1 V 0.4 V]( 10) V 6 V V 6.4 V R f 16. V o 1+ V Io + I Io R f R1 200 kω 1 + (6 mv) + (120 na)(200 k Ω) 2 kω 101(6 mv) + 24 mv 606 mv + 24 mv 630 mv 17. I Io 4 na I + IB I 20 na + IB na 2 2 I Io 4 na I IB I 20 na IB 18 na f khz f1 800 khz f c 3 A v2 5.3 Hz 19. A CL SR 2.4 V/ μs ΔV / Δt 0.3 V/10 μs i 80 R f 200 kω 20. A CL R1 2 kω 100 K A CL V i 100(50 mv) 5 V SR 0.4 V / μs w s rad/s K 5 V 3 w f s s khz 2π 2π 143

147 21. V Io 1 mv, typical I Io 20 na, typical R VIo f V o (offset) 1+ + I Io R f R1 200 kω 1 + (1 mv) + (200 kω)(20 na) 20 kω 101(1 mv) mv + 4 mv 105 mv 22. Typical characteristics for 741 R o 25 Ω, A 200 K R f 200 kω (a) A CL R1 2 kω 100 (b) Z i R 1 2 kω R 25 (c) Z o o Ω 1+ β A (200,000) Ω Ω 2001 Vo 120 mv 23. A d V d 1 mv 120 Vo 20 μv A c Vc 1 mv Ad 120 Gain (db) 20 log 20log Ac 20 log( ) db 144

148 24. V d V i1 V i2 200 μv 140 μv 60 μv Vi1 + Vi2 (200 μv μv) V c 170 μv 2 2 (a) CMRR A d A 200 c A d 6000 A c Ad 5 (b) CMRR 10 A c A d 6000 A c V c Using V o A d V d 1 + CMRR Vd V (a) V o 6000(60 μv) 1 μ μ V mv V (b) V o 6000(60 μv) 1 μ μ V mv 145

149 Chapter 11 RF 180 k Ω 1. V o V 1 (3.5 mv) R 3.6 kω mv R F 750 kω 2. V o 1+ V 1 1+ (150 mv, rms) R1 36 kω V, rms kω 680 kω 750 kω 3. V o 1 + (20 μv) 18 kω 22 kω 33 kω (29.33)( 30.91)( 22.73)(20 μv) 412 mv kω 420 kω 420 kω R1 R2 R2 R k Ω R k Ω R k Ω R kω R kω R 3 14 kω 5. V o (+15)( 22)( 30)V (80 μv) 792 mv V RF1 150 kω V o1 V 1 V 1 R1 R1 Vo 150 kω 1 Av 15 1 V R 1 1 R kω 10 kω 15 RF kω V o2 V 1 V 1 R2 R2 Vo kω Av 30 2 V R 1 2 R kω 5 kω

150 RF R F 470 kω 470 kω 6. V o V1 + V2 (40 mv) + (20 mv) R1 R 2 47 kω 12 kω [400 mv mv] 1.18 V 7. V o 10 kω 150 kω+ 300 kω V 300 k 1 Ω V2 10 kω+ 10 kω 150 kω 150 kω 0.5(3)(1 V) 2(2 V) 1.5 V 4 V 2.5 V 330 kω 470 kω 470 kω 8. V o (12 mv) (18 mv) 33 k + Ω 47 kω 47 kω [( 120 mv)(10) mv] [ 1.2 V V] V V1 12 V 11. I L R 2 kω 6 ma V o I 1 R 1 (2.5 ma)(10 kω) 25 V 13. Io R F 1 V1 R1 Rs 100 kω 1 I o (10 mv) 200 kω 10 Ω 0.5 ma 2R 14. V o 1+ [V R 2 V 1 ] p 2(5000) 1 + [1 V 3 V] 22 V

151 15. f OH 16. f OL 17. f OL f OH 1 1 2π RC π(2.2 k Ω)(0.05 μf) 1.45 khz 1 1 2π RC π(20 k Ω)(0.02 μf) Hz Hz 2π RC π(10 k Ω)(0.05 μf) 1 1 2π RC π(20 k Ω)(0.02 μf) Hz 148

152 Chapter I I BQ CQ VCC VBE 18 V 0.7 V ma RB 1.2 kω β I 40(14.42 ma) ma BQ P i V CC I dc VCC I C Q (18 V)( ma) 10.4 W I C (rms) βi B (rms) 40(5 ma) 200 ma P o I 2 (rms) R (200 ma) 2 (16 Ω) 640 mw C C 2. I B Q I C Q V CC V R I BQ B BE 18 V 0.7 V 11.5 ma 1.5 kω β 40(11.5 ma) 460 ma P i (dc) V CC I dc V ( ) CC IC + I Q BQ 18 V(460 ma ma) 8.5 W P V I i CC C Q 18 V(460 ma) 8.3 W 3. From problem 2: I C Q 460 ma, P i 8.3 W. For maximum efficiency of 25%: Po %η 100% P P o 100% 25% i 8.3 W P o 0.25(8.3 W) 21 W [If dc bias condition also is considered: V C V CC I CQ R 18 V (460 ma)(16 Ω) V C collector may vary ±7.36 V about Q-point, resulting in maximum output power: 2 2 VCE ( P) (7.36 V) P o 1.69 W 2R 2(16) C 149

153 4. Assuming maximum efficiency of 25% with P o (max) 1.5 W Po %η P 100% i P i 1.5 W W Assuming dc bias at mid-point, V C 9 V VCC VC 18 V 9 V IC A Q RC 16 Ω P i (dc) VCC I C Q (18 V)( A) W at this input: Po %η P 100% 1.5 W 100% 14.45% W i 5. R p 2 N 1 N2 R s 2 25 (4 Ω) kω 6. R 2 a 2 R 1 a 2 R2 8 kω R 8 Ω a R 2 a 2 R 1 8 kω a 2 (4 Ω) a 2 8 k Ω 4 Ω 2000 a (a) P pri P L 2 W 2 VL (b) P L RL V L PR L L (2 W)(16 Ω ) V (c) R 2 a 2 R 1 (3.87) 2 (16 Ω) Ω 2 Vpri P pri Rpri 2 W 2 V pri (2 W)(239.6 Ω) V pri V [or, V pri av L (3.87)(5.66 V) 21.9 V] 150

154 (d) P L I R 2 L I L L PL 2 W R 16 Ω L ma 2 P pri 2 W IpriR pri (239.6 Ω) I 2 pri 2 W I pri ma Ω I ma or, I pri L ma a I dc I C Q 150 ma P i VCCI C Q (36 V)(150 ma) 5.4 W Po 2 W %η 100% 100% P 5.4 W 37% 10. i

155 12. (a) P i V CC I dc (25 V)(1.75 A) W Where, I dc 2 2 Vp I 2 22 V p π π R π 8 Ω 1.75 A L (b) P o V 2 2 p (22 V) 2R 2(8 Ω ) W L Po (c) %η P i 100% W W 100% 69% 13. (a) max P i V CC I dc 2 V CC 2 25 V V CC (25 V) π R L π 8 Ω W 2 2 VCC (25 V) (b) max P o 2R 2(8 Ω ) W L (c) max %η max P 100% W o max P i W 100% 78.5% 14. (a) V L (peak) 20 V 2 V L P i V CC I dc VCC π RL 2 20 V (22 V) π 4 Ω 70 W 2 2 VL (20 V) P o 2R L 2(4 Ω ) 50 W Po 50 W %η 100% 100% 71.4% P 70 W i 2 4 V (b) P i (22 V) π 4 Ω 14 W 2 (4) P o 2(4) 2 W Po %η P 100% 2 W 100% 14.3% 14 W i 152

156 (a) max P o (ac) for V L peak 30 V: 2 2 VL (30 V) max P o (ac) 2R 2(8 Ω ) W L (b) max P i (dc) V CC I dc V CC 2 V o 2 30 V VCC π R L π 8 Ω W (c) max %η max Po max P i W 100% W 100% 78.54% (d) max P ZQ 2 V 2 (30) π 22.8 W 2 2 CC 2 2 RL π (a) P i (dc) V CC I dc V CC 2 V o π RL 30 V π 8 27 W (b) P o (ac) V (rms) (8 V) R 8 Ω 2 2 L L 8 W (c) %η Po 8 W 100% 100% 29.6% P 27 W i (d) P 2Q P i P o 27 W 8 W 19 W 153

157 18. (a) P o (ac) V (rms) (18 V) R 8 Ω 2 2 L L 40.5 W 2 VL (b) P i (dc) V CC I dc peak VCC π RL V (40 V) 81 W π 8 Ω Po (c) %η P i 100% 40.5 W 81 W 100% 50% (d) P 2 Q P i P o 81 W 40.5 W 40.5 W A2 19. %D 2 A 1 A3 %D 3 A 1 A4 %D 4 A V 100% 2.1 V 0.1 V 100% 2.1 V 0.05 V 100% 2.1 V 100% 14.3% 100% 4.8% 100% 2.4% 20. %THD D + D + D 100% (0.143) + (0.048) + (0.024) 100% 15.3% 21. D 2 ( VCE + VCE ) 1 2 V max CEmax V min CEmin 100% 1 (20 V V) 10 V 2 20 V 2.4 V 100% 1.2 V 17.6 V 100% 6.8% 22. THD D2 + D3 + D4 (0.15) + (0.01) + (0.05) I1 RC (3.3 A) (4 Ω) P W 2 2 P (1 + THD 2 )P 1 [1 + (0.16) 2 )]21.8 W W

158 23. P D (150 C) P D (25 C) (T 150 T 25 ) (Derating Factor) 100 W (150 C 25 C)(0.6 W/ C) 100 W 125(0.6) W TJ TA 200 C 80 C 24. P D θjc + θcs + θsa 0.5 C/W C/W C/W 120 C 42.9 W 2.8 C/W TJ TA 25. P D θ JA 200 C 80 C 120 C (40C/W) 40C/W 3 W 155

159 Chapter

160 6. 7. Circuit operates as a window detector. 9.1 kω Output goes low for input above ( + 12 V) 7.1 V 9.1 k Ω kω 1 kω Output goes low for input below ( + 12 V) 1.7 V 1 k Ω kω Output is high for input between +1.7 V and +7.1 V (16 V) (16 V) V VREF 10 V 10 V 10. Resolution 2.4 mv/count n See section Maximum number of count steps steps at T ns/count f 20 MHz Period 4096 counts ns 50 count μs 157

161 14. f 1.44 ( R + 2 R ) C A B 350 khz C k Ω + 2(7.5 k Ω)(350 khz) 183 pf 15. T 1.1 R A C 20 μs 1.1(7.5 kω)c C 3 1.1( ) pf 16. T μs f 10 khz T 1.1 R A C 1.1(5.1 kω)(5 nf) 28 μs 158

162 + 2 V V C 17. f o + RC 1 1 V V + 12 V R kω V C ( V ) ( + 12 V) R + R 1.8 k Ω + 11 kω V 2 12 V 10.3 V f o (4.7 k Ω)(0.001 μf) 12 V khz 18. With potentiometer set at top: R3 + R4 + 5 kω+ 18 kω V C V (12 V) V R2 + R3 + R4 510 Ω+ 5 kω+ 18 kω resulting in a lower cutoff frequency of + 2 V V 2 12 V V f o C + 3 RC 1 1 V (10 10 )(0.001 μf) 12 V 4.3 khz With potentiometer set at bottom: R kω V C V (12 V) R2 + R3 + R4 510 Ω+ 5 kω+ 18 kω 9.19 V resulting in a higher cutoff frequency of + 2 V V 2 12 V 9.19 V f o C + RC 1 1 V (10 k Ω)(0.001 μf) 12 V 61.2 khz 19. V + 12 V R kω V C V (12 V) 10.4 V R2 + R3 1.5 k Ω + 10 kω + 2 V V 2 12 V 10.4 V f o C + RC 1 1 V 10 k Ω( C1) 12 V 200 khz 2 C 1 (0.133) 10 k Ω(200 khz) pf 20. f o 21. C RC 1 1 (4.7 k Ω)(0.001 μf) 63.8 khz Rf 300 pf (10 k Ω)(100 khz) 1 159

163 22. f L ± 8 fo V 3 8( ) ± f o 6 V RC k Ω(0.001 μf) 85.1 khz 63.8 khz 23. For current loop: mark 20 ma space 0 ma For RS 232 C: mark 12 V space +12 V 24. A line (or lines) onto which data bits are connected. 25. Open-collector is active-low only. Tri-state is active-high or active-low. 160

164 Chapter A f A β A ( 2000) da A f f 1 da 1 β A A 1 20 ( 1000) (10%) 0.2% A A f β A ( 300) 15 R if (1 + βa)r i 21(1.5 kω) 31.5 kω R 50 k R of o Ω 2.4 kω 1+ β A 21 RoRD 4. R L R + R o D 40 kω 8 kω 6.7 kω A g m R L ( )( ) 33.5 R2 200 kω β R + R 200 kω+ 800 kω A A f 1+ β A 1 + ( 0.2)( 33.5) DC bias: I B VCC VBE 16 V 0.7 V R + ( β + 1) R 600 kω+ 76(1.2 k Ω) B E 15.3 V kω 22.1 μa I E (1 + β)i B 76(22.1 μa) 1.68 ma [V CE V CC I C (R C + R E ) 16 V 1.68 ma(4.7 kω kω) 6.1 V] r e 26 mv 26 mv 15.5 Ω I E (ma) 1.68 ma h ie (1 + β)r e 76(15.5 Ω) 1.18 kω Z i Z o R C 4.7 kω 161

165 hfe 75 A v hie + RE 1.18 kω+ 1.2 kω β R E (1 + βa) 1 + ( )( ) Av A f β Av 38.8 A v f A f R C ( )( ) 3.82 Z i f (1 + βa v )Z i (38.8)(1.18 kω) 45.8 kω Z o f (1 + βa v )Z o (38.8)(4.7 kω) kω without feedback (R E bypassed): RC 4.7 kω A v r 15.5 Ω e C π π pf μf Rf 6 2 (10 10 )( ) f o 2π RC Rc 6+ 4 R π (6 10 )( ) (18 10 /6 10 ) 4.17 khz 4.2 khz f o πRC 2 π(10 10 )( ) 6.6 khz CC C eq C + C f o 1 2 (750 pf)(2000 pf) 750 pf pf pf π LCeq 2π )( ) 1.05 MHz 10. f o 1 2π LC eq, 1 2 π (100μH)(3300 pf) 277 khz CC 1 2 where C eq C + C 1 2 (0.005 μf)(0.01 μf) μf μf 3300 pf 162

166 11. f o 12. f o 1, 2π L C eq π khz (4 10 )( ) 1 2π LC eq, 1 2 π (1800μH)(150 pf) khz L eq L 1 + L M 1.5 mh mh + 2(0.5 mh) 4 mh where L eq L 1 + L M 750 μh μh + 2(150 μh) 1800 μh 13. See Fig a and Fig f o 1 RC ln(1/(1 η)) T T for η 0.5: 1.5 f o R C T T (a) Using R T 1 kω C T R f (1 k Ω)(1 khz) T o 1.5 μf (b) Using R T 10 kω C T 1000 pf R f (10 k Ω)(150 khz) T o 163

167 Chapter ripple factor V r VNL VFL 2. %VR V FL (rms) 2 V/ V 50 V dc 100% 28 V 25 V 25 V 100% 12% 3. V dc 0.318V m Vdc 20 V V m V V r 0.385V m 0.385(62.89 V) 24.2 V 4. V dc 0.636V m Vdc 8 V V m 12.6 V V r 0.308V m 0.308(12.6 V) 3.88 V 5. %r V r (rms) V dc 100% V r (rms) rv dc V 1.2 V V NL V m 18 V V FL 17 V VNL VFL 18 V 17 V %VR 100% VFL 17 V 5.88% 100% 7. V m 18 V C 400 μf I L 100 ma 2.4Idc 2.4(100) V r 0.6 V, rms C Idc V dc V m C 18 V 4.17(100) V V 2.4Idc 2.4(120) 8. V r C V 9. C 100 μf V dc 12 V R L 2.4 kω I dc V 12 V 2.4 kω dc R L 5mA V r (rms) 2.4I 2.4(5) dc C V 164

168 2.4Idc 2.4(150) 10. C 100 μf rv (0.15)(24) dc 11. C 500 μf I dc 200 ma R 8% Idc Using r CV V m V dc + V dc 4.17Idc C dc 2.4I 2.4(200) dc rc 0.08(500) 12 V 12 V + (200)(4.17) V V 13.7 V 2.4Idc 2.4(200) 12. C 6857 μf V (0.07) r 13. C 120 μf I dc 80 ma V m 25 V 4.17Idc V dc V m C 25 V 4.17(80) V 2.4Idc %r CV dc 2.4(80) 100% (120)(22.2) 100% 7.2% rv dc 2(80) 14. V r 1.6 V, rms V r 2 V V dc 24 V R 33 Ω, C 120 μf X C C Ω %r V r V dc 100% 2 V 24 V 100% 8.3% X C 10.8 V r Vr (2 V) 0.65 V R 33 V dc V dc I dc R 24 V 33 Ω (100 ma) 20.7 V V %r r 100% 0.65 V 100% 3.1% V 20.7 V dc 165

169 16. RL V dc V R+ R L dc 500 (40 V) V V dc 36.4 V I dc 72.8 ma R 500 Ω L X C C Ω X C 13 V r Vr (2.5 V) R V, rms 18. V NL 60 V RL 1 kω V FL Vdc (50 V) V R+ RL 100 Ω+ 1 kω VNL VFL 50 V V %VR 100% 100% VFL V 10 % 19. V o V Z V BE 8.3 V 0.7 V 7.6 V V CE V i V o 15 V 7.6 V 7.4 V Vi VZ 15 V 8.3 V I R 3.7 ma R 1.8 kω Vo 7.6 V I L R 3.8 ma L 2 kω I 3.8 ma I B C 38 μa β 100 I Z I R I B 3.7 ma 38 μa 3.66 ma 166

170 R1 + R2 V z + V BE2 R2 20. V o ( ) 33 kω+ 22 kω (10 V V) 22 kω V R 1 12 kω 21. V o 1+ VZ V R2 8.2 kω 24.6 V 22. V o V L 10 V V 10.7 V I L 250 ma V m V r (rms) 2 2 (20 V) 28.3 V 2.4Idc V r peak 3 V r (rms) 3 C 2.4(250) V V dc V m V 28.3 V 2.1 V 26.2 V r peak V i (low) V dc V r peak 26.2 V 2.1 V 24.1 V 25. To maintain V i (min) 7.3 V (see Table 15.1) V V m V i (min) 12 V 7.3 V 4.7 V r peak so that V r peak 4.7 V V r (rms) 2.7 V The maximum value of load current is then Vr (rms) C (2.7 V)(200) I dc 225 ma

171 2 26. V o V ref 1 R + + I adj R L R kω 1.25 V μa(2.4 kω) 240 Ω 1.25 V(8.5) V V V o V ref 1 R + + I adj R 2 R kω 1.25 V μa(1.5 kω) 220 Ω 9.9 V 168

172 Chapter (a) The Schottky Barrier diode is constructed using an n-type semiconductor material and a metal contact to form the diode junction, while the conventional p-n junction diode uses both p- and n-type semiconductor materials to form the junction. (b) 2. (a) In the forward-biased region the dynamic resistance is about the same as that for a p-n junction diode. Note that the slope of the curves in the forward-biased region is about the same at different levels of diode current. (b) In the reverse-biased region the reverse saturation current is larger in magnitude than for a p-n junction diode, and the Zener breakdown voltage is lower for the Schottky diode than for the conventional p-n junction diode. 3. ΔI R 100 μa 0.5 μa 1.33 μ A/ C Δ C 75 C Δ I (1.33 μa/ C) Δ C (1.33 μa/ C)(25 C) 33.25μA R I 0.5μA+33.25μA 33.75μ A R 4. X C 1 1 2π fc 2 π(1 MHz)(7 pf) 22.7 kω R DC VF 400 mv 40 Ω I 10 ma F 5. Temperature on linear scale T(1/2 power level of 100 mw) 95 C 6. V F a linear scale V F (25 C) 380 mv 0.38 V At 125 C, V F 280 mv ΔVF 100 mv Δ 100 C T 1 mv/ C At 100 C V F 280 mv + (1 mv/ C)(25 C) 280 mv + 25 mv 305 mv Increase temperature and V F drops. 169

173 7. (a) C T (V R ) n 1/3 ( ) C(0) 80 pf 1+ V 4.2 V R VT V 80 pf pf (b) k C T (V T + V R ) n pf(0.7 V V) 1/ (a) At 3 V, C 40 pf At 12 V, C 20 pf ΔC 40 pf 20 pf 20 pf Δ C 40 pf (b) At 8 V, 2 pf/v ΔVR 20 V Δ C 60 pf At 2 V, 6.67 pf/v ΔVR 9 V ΔC increases at less negative values of V R. ΔV R 9. Ratio Ct ( 1 V) 92pF C ( 8 V) 5.5 pf t Ct ( 1.25 V) C ( 7 V) t C t 15 pf 1 1 Q 2π frsct 2 π(10 MHz)(3 Ω)(15 pf) vs 350 on chart 11. ΔC Δ C 100% TC C C ( ) 100% T 1 o T1 T0 TCC( Co) + T o (0.11 pf)(100) (0.02)(22 pf) C 12. V R from 2 V to 8 V C t ( 2 V) 60 pf, C t ( 8 V) 6 pf Ratio Ct ( 2 V) 60 pf C ( 8 V) 6 pf t

174 13. Q( 1 V) 82, Q( 10 V) 5000 Q( 10 V) 5000 Ratio Q( 1 V) 82 6 f Hz BW o khz Q 82 6 f Hz BW o 2 khz Q High-power diodes have a higher forward voltage drop than low-current devices due to larger IR drops across the bulk and contact resistances of the diode. The higher voltage drops result in higher power dissipation levels for the diodes, which in turn may require the use of heat sinks to draw the heat away from the body of the structure. 15. The primary difference between the standard p-n junction diode and the tunnel diode is that the tunnel diode is doped at a level from 100 to several thousand times the doping level of a p-n junction diode, thus producing a diode with a negative resistance region in its characteristic curve At 1 MHz: X C π fc 2 π(1 10 Hz)(5 10 F) kω 1 At 100 MHz: X C π ( Hz)(5 10 F) Ω At 1 MHz: X L S 2πfL 2π( Hz)( H) Ω At 100 MHz: X L S 2π( Hz)( H) Ω L s effect is negligible! R and C in parallel: f 1 MHz Z T (152 Ω 180 )(31.83 kω 90 ) 152 Ω j31.83 kω Ω Ω 0 f 100 MHz (152 Ω 180 )( ) Z T 152 Ω j Ω Ω 0 At very high frequencies X C has some impact! 171

175 17. The heavy doping greatly reduces the width of the depletion region resulting in lower levels of Zener voltage. Consequently, small levels of reverse voltage can result in a significant current levels. 18. At V T 0.1 V, I F 5.5 ma At V T 0.3 V I F 2.3 ma ΔV 0.3 V 0.1 V R ΔI 2.3 ma 5.5 ma 0.2 V 62.5 Ω 3.2 ma E 2 V 19. I sat R 5.13 ma 0.39 kω From graph: Stable operating points: I T 5 ma, V T 60 mv I T 2.8 ma, V T 900 mv E 0.5 V 20. I sat R 9.8 ma 51 Ω Draw load line on characteristics f s 2π LC 22. W hf 2 Rl C 1 L (10 Ω ) (1 10 F) π (5 10 H)(1 10 F) 5 10 H ( Hz)(0.9899) 2228 Hz v h λ 34 8 ( J s)(3 10 m/s) 10 (5000)(10 m) J ev J J 2.48 ev 172

176 23. (a) Visible spectrum: 3750 A 7500 (b) Silicon, peak relative response 8400 A (c) BW 10,300 A 6100 A 4200 A W/m 2,486 f 12 c From the intersection of V A 30 V and 2,486 f c we find I λ 440 μa 25. (a) Silicon (b) 1 A m, m m/a 6000 A orange 26. Note that V λ is given and not V. At the intersection of V λ 25 V and 3000f c we find I λ 500 μa and V R I λ R ( A)( Ω) 50 V 27. (a) Extending the curve: 0.1 kω 1000f c, 1 kω 25f c 3 ΔR (1 0.1) 10 Ω 0.92 Ω/f c 0.9 Ω/f c Δf ( ) f c c (b) 1 kω 25f c, 10 kω 1.3f c 3 ΔR (10 1) 10 Ω Ω/f c 380 Ω/f c Δf (25 1.3) f c c (c) 10 kω 1.3f c, 100 kω 0.15f c 3 ΔR (100 10) 10 78, Ω/f c Ω/f c Δfc ( ) fc The greatest rate of change in resistance occurs in the low illumination region. 28. The dark current of a photodiode is the diode current level when no light is striking the diode. It is essentially the reverse saturation leakage current of the diode, comprised mainly of minority carriers f c R 2 kω V o 6 V V i 21 V 3 (2 10 Ω) V i Ω Ω 173

177 30. Except for low illumination levels (0.01f c ) the % conductance curves appear above the 100% level for the range of temperature. In addition, it is interesting to note that for other than the low illumination levels the % conductance is higher above and below room temperature (25 C). In general, the % conductance level is not adversely affected by temperature for the illumination levels examined. 31. (a) (b) (c) Increased levels of illumination result in reduced rise and decay times. 32. The highest % sensitivity occurs between 5250A and 5750A. Fig reveals that the CdS unit would be most sensitive to yellow. The % sensitivity of the CdS unit of Fig is at the 30% level for the range 4800A 7000A. This range includes green, yellow, and orange in Fig (a) 5 mw radiant flux 3.5 mw (b) 3.5 mw W/lm lms 174

178 34. (a) Relative radiant intensity 0.8. (b) Relative radiant vs degrees off vertical θ >30 and relative radiant intensity essentially zero- Drops off very sharply after 25! 35. At I F 60 ma, Φ 4.4 mw At 5, relative radiant intensity 0.8 (0.8)(4.4 mw) 3.52 mw 36. 6, 7, The LED generates a light source in response to the application of an electric voltage. The LCD depends on ambient light to utilize the change in either reflectivity or transmissivity caused by the application of an electric voltage. 39. The LCD display has the advantage of using approximately 1000 times less power than the LED for the same display, since much of the power in the LED is used to produce the light, while the LCD utilizes ambient light to see the display. The LCD is usually more visible in daylight than the LED since the sun s brightness makes the LCD easier to see. The LCD, however, requires a light source, either internal or external, and the temperature range of the LCD is limited to temperatures above freezing. 40. η% P max 2 ( A 2 )(100 mw/cm ) cm Pmax 9% 2 2 (2 cm )(100 mw/cm ) P max 18 mw 100% 100% 41. The greatest rate of increase in power will occur at low illumination levels. At higher illumination levels, the change in V OC drops to nearly zero, while the current continues to rise linearly. At low illumination levels the voltage increases logarithmically with the linear increase in current. 42. (a) Fig mw/cm 2 (b) It is the maximum power density available at sea level. (c) Fig ma (b) 175

179 43. (a) (b) (c) The curve of I o vs P density is quite linear while the curve of V o vs P density is only linear in the region near the optimum power locus (Fig 16.48). 44. Since log scales are present, the differentials must be as small as possible. ΔR ( ) Ω 6000 Ω ΔT (40 0) Ω/ C ΔR (3 1) Ω 2 Ω Δ T Ω/ C From the above 150 Ω/ C: 0.05 Ω/ C 3000:1 Therefore, the highest rate of change occurs at lower temperatures such as 20 C. 45. No. 1 Fenwall Electronics Thermistor material. Specific resistance ,000 Ω cm ρ R A 2x R 2 (10,000 Ω) 20 kω twice 46. (a) 10 5 A 10 μa (b) Power 0.1 mw, R 10 7 Ω 10 MΩ (c) Log scale 0.3 mw 47. V IR + IR unk + V m V I(R + R unk ) + 0 V R unk V R I 0.2 V 2 ma 10 Ω 100 Ω 10 Ω 90 Ω 176

180 Chapter (a) p-n junction diode (b) The SCR will not fire once the gate current is reduced to a level that will cause the forward blocking region to extend beyond the chosen anode-to-cathode voltage. In general, as I G decreases, the blocking voltage required for conduction increases. (c) The SCR will fire once the anode-to-cathode voltage is less than the forward blocking region determined by the gate current chosen. (d) The holding current increases with decreasing levels of gate current. 5. (a) Yes (b) No (c) No. As noted in Fig. 17.8b the minimum gate voltage required to trigger all units is 3 V. (d) V G 6 V, I G 800 ma is a good choice (center of preferred firing area). V G 4 V, I G 1.6 A is less preferable due to higher power dissipation in the gate. Not in preferred firing area. 6. In the conduction state, the SCR has characteristics very similar to those of a p-n junction diode (where V T 0.7 V). 7. The smaller the level of R 1, the higher the peak value of the gate current. The higher the peak value of the gate current the sooner the triggering level will be reached and conduction initiated. Vsec 8. (a) V P (rms) V ( 2 ) V 2 V DC 0.636(82.78 V) V (b) V AK V DC V Batt V 11 V V 177

181 (c) V R V Z + V GK 11 V + 3 V 14 V At 14 V, SCR 2 conducts and stops the charging process. (d) At least 3 V to turn on SCR (e) V 2 1 V 1 (82.78 V) 2 P V 10. (a) Charge toward 200 V but will be limited by the development of a negative voltage V V that will eventually turn the GTO off. V GK ( ) Z C 1 (b) τ R 3 C 1 (20 kω)(0.1 μf) 2 ms 5τ 10 ms (c) 5τ 1 (5 ) 2 τ 5 ms 5R GTO C 1 5 ms 5 ms R GTO 6 5C 5( F) 11. (a) 0.7 mw/cm 2 (b) 0 C 0.82 mw/cm C 0.16 mw/cm % 80.5% kω 1 (20 k Ω above) V C V BR + V GK 6 V + 3 V 9 V V C 40(1 e t/rc ) e t/rc 9 40e t/rc 31 e t/rc 31/ RC ( Ω)( F) s log e (e t/rc ) log e t/rc t/ and t 0.255( ) 0.51 ms V V ± 10% V BR V ± 0.64 V 5.76 V 7.04 V BR1 BR

182 16. V VP I P > R 1 40 V [0.6(40 V) V] MΩ > R 1 V VV < R 1 40 V 1 V I 8 ma kω < R 1 V 1.53 MΩ > R 1 > kω RB (a) η R + R B1 B2 I E kω R B 1.08 kω 2 2 kω+ RB 2 (b) R BB ( RB RB ) + 2 kω kω 3.08 kω 1 2 IE 0 (c) V R B1 ηv BB 0.65(20 V) 13 V (d) V P ηv BB + V D 13 V V 13.7 V RB (a) η R BB IE 0 R B kω R B! 5.5 kω R BB RB + R! B2 10 kω 5.5 kω + R B kω R B 2 (b) V P ηv BB + V D (0.55)(20 V) V 11.7 V V V (c) R 1 < I p ok: 68 kω < 166 kω P 20 V 11.7 V 166 kω 50 μa 179

183 V V (d) t 1 R 1 C log e V V (e) P t 2 ( R + R ) C log e B ms T t 1 + t ms f Hz T ms V P ( )( ) log e 5.56 ms 8.3 V V (0.2 kω kω)( ) log e 1.2 V (f) V V R2 R2 RV k Ω(20 V) R2 + RBB 2.2 kω+ 10 kω 3.61 V R2 ( VP 0.7 V) R + R 2 B1 2.2 k Ω(11.7 V 0.7 V) 2.2 kω+ 0.2 kω V 1 1 (g) f Hz RC log (1/(1 η)) (6.8 k Ω)(0.1 μf)log e difference in frequency levels is partly due to the fact that t 2 10% of t I B 25 μa I C h I (40)(25 μa) 1 ma fe B e 180

184 20. ΔI 21. (a) D F ΔT ( 50) %/ C (b) Yes, curve flattens after 25 C. 22. (a) At 25 C, I CEO 2 na At 50 C, I CEO 30 na 9 ΔI CEO (30 2) 10 A 28 na 1.12 na/ C ΔT (50 25) C 25 C I CEO (35 C) I CEO (25 C) + (1.12 na/ C)(35 C 25 C) 2 na na 13.2 na From Fig I CEO (35 C) 4 na Derating factors, therefore, cannot be defined for large regions of non-linear curves. Although the curve of Fig appears to be linear, the fact that the vertical axis is a log scale reveals that I CEO and T( C) have a non-linear relationship. 23. Io IC 20 ma 0.44 Ii IF 45 ma Yes, relatively efficient. 181

185 24. (a) P D V CE I C 200 mw PD 200 mw I C 6.67 V CE 30 V V 30 V V CE CEmax P I D C 200 mw 20 I C 10 ma 10 ma PD 200 mw I C V 25 V 8.0 V CE 25 V CE Almost the entire area of Fig falls within the power limits. (b) β dc I I C F 4 ma IC 0.4, Fig ma I F 4 ma 10 ma (a) I C 3 ma The fact that the I F characteristics of Fig are fairly horizontal reveals that the level of I C is somewhat unaffected by the level of V CE except for very low or high values. Therefore, a plot of I C vs. I F as shown in Fig can be provided without any reference to the value of V CE. As noted above, the results are essentially the same. (b) At I C 6 ma; R L 1 kω, t 8.6 μs R L 100 Ω; t 2 μs 1 kω:100 Ω 10:1 8.6 μs:2 μs 4.3:1 ΔR:Δt 2.3:1 3RB η 3R + R 4 B2 B2 0.75, V G ηv BB 0.75(20 V) 15 V 27. V P 8.7 V, I P 100 μa Z P V V 1 V, I V 5.5 ma Z V 87 kω: Ω :1 500:1 V I P P V I V V 8.7 V 100 μa 87 kω ( open) 1 V Ω (relatively low) 5.5 ma 182

186 V BB V BB 28. Eq : T RC log e RC loge VBB VP VBB ( ηvbb + VD ) V BB Assuming ηv BB V D, T RC log e RC log e (1/1 η) RC log 1 e VBB (1 η) RB 1 1 RB + R RB + R 1 B R 2 B1 RC log e RC loge 1+ Eq R B R 2 B2 1 B2 29. (a) Minimum V BB : VBB VP R max I P P 20 kω VBB ( ηvbb + VD ) 20 kω I V BB ηv BB V D I P 20 kω V BB (1 η) I P 20 kω + V D IP20 kω + VD V BB 1 η (100 μa)(20 k Ω ) V V 10 V OK V (b) R < BB V I V R < 2 kω V 12 V 1 V 2 kω 5.5 ma R B1 (c) T RC log e 1+ R B R( kω )log e 1+ 5 kω log e R 6 (1 10 )(1.0986) R 1.82 kω 183

187

188 Solutions for Laboratory Manual to accompany Electronic Devices and Circuit Theory Tenth Edition Prepared by Franz J. Monssen 185

189 186

190 EXPERIMENT 1: OSCILLOSCOPE AND FUNCTION GENERATOR OPERATIONS Part 1: The Oscilloscope a. it focuses the beam on the screen b. adjusts the brightness of the beam on the screen c. allows the moving of trace in either screen direction d. selects volts/screen division on y-axis e. selects unit of time/screen division on x-axis g. allows for ac or dc coupling of signal to scope and at GND position; establishes ground reference on screen h. locates the trace if it is off screen i. provide for the adjustment of scope from external reference source k. determines mode of triggering of the sweep voltage m. the input impedance of many scopes consists of the parallel combination of a 1 Meg resistance and a 30pf capacitor n. measuring device which reduces loading of scope on a circuit and effectively increases input impedance of scope by a factor of 10. Part 2: The Function Generator d. T l/f 1/1000 Hz l ms e. (calculated): 1 ms*[l cm/.2 ms] 5cm (measured): 5 cm same f. (calculated): l ms*[cm/.5ms] 2 cm (measured): 2 cm same g. (calculated): 1 ms*[cm/1ms] l cm (measured): l cm same h..2 ms/cm takes 5 boxes to display total wave.5 ms/cm takes 2 boxes to display total wave 1 ms/cm takes 1 box to display total wave i. 1. adjust timebase to obtain one cycle of the wave 2. count the number of cm's occupied by the wave 3. note the timebase setting 4. multiply timebase setting by number of cm's occupied by wave. This is equal to the period of the wave. 5. obtain its reciprocal; that's the frequency. 187

191 j. (calculated): 2cm * [2V/cm] 4Vp-p k. 8 * [.5V/cm] 4Vp-p 1. the signal occupied full screen; the peak amplitude did not change with a change in the setting of the vertical sensitivity m. no: there is no voltmeter built into function generator Part 3: Exercises a. chosen sensitivities: Vert. Sens. l V/cm Hor. Sens. 50 μs/cm T(calculated): 4cm*[50 μs/cm) 200 μs Fig 1.1 b. chosen sensitivities: Vert. Sens..l V/cm Hor. Sens. 1 ms/cm T(calculated):5 cm*[l ms/cm] 5 ms Fig

192 c. chosen sensitivities: Vert. Sens. l V/cm Hor. Sens. l μs/cm T(calculated):10 cm*[1μs/cm]10 μs Fig 1.3 Part 4: Effect of DC Levels a. V (rms) (calculated) 4V * 1/2 * Volts b. V (rms) (measured) 1.35 Volts c. [( )/1.41) * % d. no trace on screen e. signal is restored, adjust zero level f. no shift observed; the shift is proportional to dc value of waveform g. (measured) dc level: 1.45 Volts h. Fig 1.5 i. Switch AC-GND-DC switch, make copy of waveform above. The vertical shift of the waveform was equal to the battery voltage. 189

193 The shape of the sinusoidal waveform was not affected by changing the positions of the AC-GND-DC coupling switch. j. The signal shifted downward by an amount equal to the voltage of the battery. Fig 1.6 Part 5: Problems 1. b. f 2000/(2*3.14) 318Hz c. T l/f 1/ ms d. by inspection: V(peak) 20V e. V(peak-peak) 2*Vpeak 40V f. V(rms).707 * V g. by inspection: Vdc 0V 2. a. f 2 * 3.14 * 4000/(2 * 3.14*) 4 KHz c. T l/f 1/4 Khz 250 μs d. by inspection:vpeak) 8 mv e. V(peak-peak) 2 * V(peak) 16 mv f. V(rms).707 * 8 mv 5.66 mv g. by inspection: Vdc 0V 3. V(t) 1.7 sin (2.51 Kt) volts Part 6: Computer Exercise PSpice Simulation 1-1 See Probe Plot page

194 191

195 EXPERIMENT 2: DIODE CHARACTERISTICS Part 1: Diode Test diode testing scale Test Forward Reverse Both diodes are in good working order. Part 2. Forward-bias Diode characteristics Table 2.1 Si (mv) 535 OL Ge (mv) 252 OL b. V R (V) V D (mv) I D (ma) Table V R (V) V D (mv) I D (ma) d. V R (V) V D (mv) I D (ma) Table V R (V) V D (mv) I D (ma) e. Fig

196 f. Their shapes are similar, but for a given I D, the potential V D is greater for the silicon diode compared to the germanium diode. Also, the Si has a higher firing potential than the germanium diode. Part 3: Reverse Bias b. R m 9.9 Mohms V R (measured) 9.1 mv I S (calculated) 8.21 na c. V R (measured) 5.07 mv I S (calculated) 4.58 μa d. The I S level of the germanium diode is approximately 500 times as large as that of the silicon diode. e. R DC (Si) 2.44*10 9 ohms R DC (Ge) 3.28 M*10 6 ohms Part 4: DC Resistance These values are effective open-circuits when compared to resistors in the kilohm range. a. b. Table 2.5 I D (ma) V D (mv) R DC (ohms) Table 2.6 I D (ma) V D (mv) R DC (ohms) Part 5: AC Resistance a. (calculated)r ac 3.4 ohms b. (calculated)r ac 2.9 ohms c. (calculated)r ac 27.0 ohms d. (calculated)r ac 26.0 ohms Part 6: Firing Potential V T (silicon) 540 mv V T (germanium) 260 mv 193

197 Part 7: Temperature Effects c. For an increase in temperature, the forward diode current will increase while the voltage V D across the diode will decline. Since R D V D /I D, therefore, the resistance of a diode declines with increasing temperature. d. As the temperature across a diode increases, so does the current. Therefore, relative to the diode current, the diode has a positive temperature coefficient. Part 9: Computer Exercises PSpice Simulation See Probe plot page R D 600mV 658 Ω R D 700 mv 105 Ω 4. R D 600 mv 257 Ω 5. See Probe Plot V(D1) versus I(D1) 7. Silicon 8. See Probe plot page See Probe plot page See Probe plot page

198 195

199 196

200 EXPERIMENT 3: SERIES AND PARALLEL DIODE CONFIGURATIONS Part 1: Threshold Voltage V T Fig 3.2 Firing voltage: Silicon: 595 mv Germanium: 310 mv Part 2: Series Configuration b. V D.59 V V O (calculated) V I D 4.41/2.2 K 2 ma c. V D (measured).59 V V O (measured) 4.4 V I D (from measured) 2 ma e. V D 595 mv V O (calculated) (5.595) 1 K/(1 K K) 1.33 V I D 1.36 ma f. V D.57 V V O 1.36 V I D (from measured) 1.36 V/1 K 1.36 ma g. V D (measured) 5 V h. V D (measured) 5 V V O (measured) 0 V V O (measured) 0 V I D (measured) 0 A I D (measured) 0 A j. V 1 (calculated).905 V V O (calculated) 4.1 V I D (calculated) 1.86 ma Part 7: Computer Exercise PSpice Simulation mv 197

201 EXPERIMENT 4: HALF-WAVE AND FULL-WAVE RECTIFICATION Part 1: Threshold Voltage V T.64 V Part 2: Half-wave Rectification b. Vertical sensitivity 1 V/cm Horizontal sensitivity.2 ms/cm c. Fig 4.4 d. Both waveforms are in essential agreement. e. V dc (4.64)/ V f. V dc (measured).979 V % difference ( )/1.07* % g. For an ac voltage with a dc value, shifting the coupling switch from its DC to AC position will make the waveform shift down in proportion to the dc value of the waveform. h. Fig

202 i. V dc (calculated) 1.07 V V dc (measured).970 V Part 3: Half-Wave Rectification (continued) b. Fig 4.8 c. Fig 4.9 The results are in reasonable agreement. d. The significant difference is in the respective reversal of the two voltage waveforms. While in the former case the voltage peaked to a positive 3.4 volts, in the latter case, the voltage peaked negatively to the same voltage. e. V DC (.318)* Volts f. Difference [ ]/1.08* % 199

203 Part 4: Half-Wave Rectification (continued) b. Fig 4.11 c. Fig 4.12 There was a computed 2.1% difference between the two waveforms. d. Fig

204 We observe a reversal of the polarities of the two waveforms caused by the reversal of the diode in the circuit. Part 5: Full-Wave Rectification (Bridge Configuration) a. V (secondary)rms 14 V This value differs by 1.4 V rms from the rated voltage of the secondary of the transformer. b. V (peak) 1.41*14 20 V c. Fig 4.15 Vertical sensitivity: 5 V/cm Horizontal sensitivity: 2 ms/cm d. Fig

205 Again, the difference between expected and actual was very slight. e. V dc (calculated) (.6326)*(20) 12.7 V V dc (measured) V % Difference 10.6% g. Vertical sensitivity 5 V/cm Horizontal sensitivity 2 ms/cm Fig 4.17 i. V dc (calculated) (.636)*(12) 7.63 V j V dc (measured) 7.05 V % Difference 7.6% k. The effect was a reduction in the dc level of the output voltage. Part 6: Full-Wave Center-tapped Configuration a. V rms (measured) 6.93 V V rms (measured) 6.97 V As is shown from the data, the difference for both halves of the center-tapped windings from the rated voltage is.6 volts. b. Vertical sensitivity 5 V/cm Horizontal sensitivity 2 ms/cm 202

206 c. Fig 4.21 d. V dc (calculated) 3.5 V V dc (measured) 3.04 V Part 7: Computer Exercise PSpice Simulation V p 8.47 V; relative phase shift is equal to PIV 2 Vp out of phase 4. See Probe plot page 204. Its amplitude is 7.89 V 5. Yes 6. Reasonable agreement. 203

207 204

208 EXPERIMENT 5: CLIPPING CIRCUITS Part 1: Threshold Voltage V T (Si).618 V V T (Ge).299 V Part 2 Parallel Clippers b. V O (calculated) 4 V c. V O (calculated) V d. Fig 5.2 Vertical sensitivity 1 V/cm Horizontal sensitivity.2 ms/cm e. Fig 5.3 No measured differences appeared between expected and observed waveforms. f. V O (calculated) 4 V g. V O (calculated).62 V 205

209 Part 3: Parallel Clippers (continued) b. V O (calculated).61 V c. V O (calculated).34 V d. Fig 5.7 Vertical sensitivity 1 V/cm Horizontal sensitivity.2 ms/cm e. Fig 5.8 The waveforms agree. Part 4: Parallel Clippers (Sinusoidal Input) b. V O (calculated) 4 V when V i 4 V V O (calculated) 2 V when V i 4 V V O (calculated) 0 V when V i 0 V 206

210 Fig 5.9 c. Waveforms agree within 6.5%. Part 5: Series Clippers b. V O (calculated) 2.5 V when V i 4 V c. V O (calculated) 0 V when V i 4 V d. Fig 5.12 e. agree within 5.1% Vertical sensitivity 1 V/cm Horizontal sensitivity.2 ms/cm f. V O (calculated) 5.5 V when V i 4 V g. V O (calculated) 0 V when V i 4 V 207

211 h. Fig 5.14 i. no major differences Vertical sensitivity 2 V/cm Horizontal sensitivity.2 ms/cm Part 6: Series Clippers (Sinusoidal Input) b. V O (calculated) 2 V when V i 4 V V O (calculated) 0 V when V i 4 V V O (calculated) 0 V when V i 0 V Fig 5.16 Vertical sensitivity 1 V/cm Horizontal sensitivity.2 ms/cm 208

212 Part 7: Computer Exercises PSpice Simulation See Probe plot page V OUT 4 V 3. No 4. V OUT V 5. Yes, V OUT (ideal) 1.5 V 6. Reasonable agreement 7. No significant discrepancies 8. See Probe plot page 211. PSpice Simulation See Probe plot page In close agreement 3. No 4. For V 1 4 V; V out V 1 V D1 1.5 V 4 V V 1.9 V For V 1 4 V; I (D1) 0 A, V out 0 V 5. See Probe plot page See Probe plot page See Probe plot page See Probe plot page Forward bias voltage of about 600 mv when ON. Reverse diode voltage of diode is 4 V 1.5 V 5.5 V 209

213 210

214 211

215 212

216 213

217 EXPERIMENT 6: CLAMPING CIRCUITS Part 1: Threshold Voltage V T.62 V Part 2: Clampers (R, C, Diode Combination) b. V C (calculated) V V O (calculated) 0.62 V c. V O (calculated) V 7.38 V d. Fig 6.2 Vertical sensitivity 1 V/cm Horizontal sensitivity.2 ms/cm 214

218 e. Fig 6.3 f. V C (calculated) 3.38 V V O (calculated) 0.62 V g. V O (calculated) 7.38 V h. Fig 6.4 i. Fig 6.5 Vertical sensitivity 1 V/cm Horizontal sensitivity.2 ms/cm 215

219 Part 3: Clampers with a DC battery b. V C (calculated) 1.88 V V O (calculated) 0.62 V V 2.12 V c. V O (calculated) 1.88 V 4 V 5.88 V d. Fig 6.7 Vertical sensitivity 1 V/cm Horizontal sensitivity.2 ms/cm e. Fig 6.8 f. V C (calculated) 4.88 V V O (calculated) 1.5 V 0.62 V 0.88 V g. V O (calculated) 4 V V 8.88 V 216

220 h. Fig 6.9 Vertical sensitivity 2 V/cm Horizontal sensitivity.2 ms/cm Part 4: Clampers (Sinusoidal Input) b. V O (calculated) 0 V when V i 2 V V O (calculated) 2 V when V i 3.6 V V O (calculated) 1.6 V when V i 0 V Fig 6.11 Vertical sensitivity 1 V/cm Horizontal sensitivity.2 ms/cm 217

221 Part 5: Clampers (Effect of R) a. Tau(calculated) R*C 103 ms b. T(calculated) 1/f 1 ms T/2(calculated) 1 ms/2.5 ms c. 5Tau(calculated) 5*103 ms 515 ms d. otherwise the capacitor voltage will not remain constant e. 5Tau(calculated) 5 ms f. 5 ms/.5 ms 10 g. Fig 6.13 Vertical sensitivity 1 V/cm Horizontal sensitivity.2 ms/cm i. 5Tau.5 ms j..5 ms/.5ms 1 k. Fig 6.14 Vertical sensitivity 1 V/cm Horizontal sensitivity.2 ms/cm m. 5Tau 2.5 T or Tau 1/2 T 218

222 Part 6: Computer Exercise PSpice Simulation See Probe Plot page They are the same. 3. V O (calculated) is close to V(2) of Probe plot. 4. See Probe plot page V(1, 2) remains at 2 V during the cycle of V(1) 6. It rises exponentially toward its final value of 2 V. 7. See Probe plot page

223 220

224 221

225 222

226 EXPERIMENT 7: LIGHT-EMITTING AND ZENER DIODES Part 1: LED Characteristics b. V D (measured) 1.6 V V R (measured) 49.1 mv I D (calculated) 49.1 mv/101.4 ohms 484 μa c. V D (measured) 1.9 V V R (measured) 1.55 V I D (calculated) 1.55 V/101.4 ohms 15.3 ma d. E(v) VD (V) VR (V) ID VR/R (ma) e. Fig 7.2 h. The reversed biased Si diode prevents any current from flowing through the circuit, hence, the LED will not light. k. V R (V) 3.48 V, therefore I D (ma) 1.6 ma and LED is in the good brightness region. Part 2: Zener Diode Characteristics b. and c. Table 7.2 E (V) V Z (V) V R (V) I Z (ma)

227 d. Fig 7.5 e. V Z (V) (approximated) ( )/2 9.7 V f. r av (ohms) (10.4 9)/( ) 39.9 ohms g. R Z (ohms) 39.9 ohms V Z (V) 9.7 V Part 3: Zener Diode Regulation a. R (meas) 979 ohms R L (meas) 986 ohms V Z (V) 10.2 V b. V L (V) 986*15/( ) 7.53 V V R (V) 979*15/( ) 7.47 V I R (ma) 7.47/ ma I L (ma) 7.53/ ma I Z (ma) I R I L 10 μa c. V L (measured) 7.5 V V R (measured) 7.49 V I R (calculated) 7.65 ma I L (calculated) 7.60 ma I Z (calculated) 50 μa d. V L (calculated) 11.5 V V R (calculated) 3.54 V I R (calculated) 3.62 ma I L (calculated) 3.48 ma I Z (calculated).14 ma 224

228 e. V L (measured) 9.82 V V R (measured) 3.54 V I R (calculated) 3.54 ma I L (calculated) 2.98 ma I Z (calculated).56 ma The difference is expressed as a percent with calculated value as the standard of reference. percent change of: V L 14.6% V R 0.% I R 2.21% I L 14.4% I Z 30.0% f. R min /(R min + 979)* V R L (calculated) 1.86 Kohms g. Since 2.2 Kohms > R min 1.86 Kohms, therefore, diode is in the on state. Part 4: LED-Zener diode combination b. V D 1.86 V I D 15.8 ma V Z V V ab (calculated) 11.9 V c. V L (calculated) 11.9 V I L (calculated) 5.41 ma e. E (calculated) V R + V L V f. E (measured) 19.1 V The two values are in agreement within 1.06% using E (calculated) as reference. 225

229 Part 5: Computer Exercise PSpice Simulation See Circuit diagram 9. Yes 226

230 EXPERIMENT 8: BIPOLAR JUNCTION TRANSISTOR (BJT) CHARACTERISTICS Part 2: The Collector Characteristics d., f., g., h. Table 8.3 i. Fig

231 Part 3: Variation of Alpha and Beta b. The variations for Alpha and Beta for the tested transistor are not really significant, resulting in an almost ideal current source which is independent of the voltage V CE. c. The highest Beta s are found for relatively large values of I C and V CE. This is a generally well known factor. d. Beta did increase with increasing levels of I C. e. Beta did increase with increasing levels of V CE. Part 5: Exercises 1. Beta(average) 141 The arithmetic average occurred in the center of Fig V BE(average).678 V Given that.7 V differs by only 3.14% from.678, and given that resistive circuit component can vary by as much as 20%, the assumption of a constant.7 V is entirely reasonable. 3. The Beta of the transistor is increasing. Table 8.3 does substantiate that conclusion. Beta would be a constant anywhere along that line. Part 6: Computer Exercise PSpice Simulation See Circuit diagram. 2. Experimental PSpice α β

232 EXPERIMENT 9: FIXED- AND VOLTAGE-DIVIDER BIAS OF BJTs Part 1: Determining β b. V BE (measured).67 V V RC (measured) 4.9 V c. I B B (VCC V BE )/R BB (20.67)/1.108 M 17.4 μa I C V RC /R C 4.9/2.73 K 1.79 ma d. Beta I C /I B B 1.79 ma/17.4 μa 105 Part 2: Fixed-bias configuration a. I B (calculated) B 17 μa I C (calculated) 1.79 ma b. V B (calculated) B VCC I B * R BB.67 V V C (calculated) V CC I C * R C 13.4 V V E (calculated) 0 V(emitter is at ground) V CE (calculated) V C V E 13.4 V c. V B (measured) B.67 V V C (measured) 13.4 V V E (measured) 0 V V CE (measured) V The difference between measured and calculated values in every case is less than 10%. It s almost too good to be true. d. V BE (measured).68 V V RC (measured) 16.7 V I B (from B measured) 17.4 μa I C (from measured) 6.12 ma Beta(calculated) 352 Table 9.1 Transistor Type V CE (V) I C (ma) I B (μa) β 2N N e. Table 9.2 % Δ β % Δ I C % Δ V CE % Δ I BB

233 Part 3: Voltage-divider configuration b. B Table 9.3 2N3904 V B (V) V E (V) V C (V) V CE (V) (calculated) (measured) B 2N3904 I E (ma) I C (ma) I B μa) (calculated) (measured) c. The agreement between measured and calculated values fall entirely within reasonable limits. d. and e. Table 9.4 Transistor Type V CE (V) I C (ma) I B (μa) Beta 2N N f. Table 9.5 % Δ β % Δ I C % Δ V CE % Δ I BB Part 4: Computer Exercises PSpice Simulation See circuit diagram. 230

234 4. See circuit diagram % 6. %ΔI B B 0.05% %ΔI C 8.2% %ΔI E 8.15% 7. %ΔV CE 6.57% 8. S(β).995 PSpice Simulation See circuit diagram. 231

235 4. See circuit diagram. B 5. %Δβ 8.24% 6. %ΔI B 6.47% %ΔI C 1.13% %ΔI E 1.10% 7. %ΔV CE 0.94% 8. S(β) 1.13% 8.24% Circuit with Q2N Same as # Same as #9. Part 5: Problems and Exercises 1. a. I C(sat, fixed bias) 20/2.73 K 7.33 ma b. I C(sat,volt-divider bias) 20/(1.86 K + 692) 7.83 ma c. The saturation currents are not sensitive to the Beta s in either bias configuration. 2. In the case of the 2N4401 transistor, which had a higher Beta than the 2N3904 transistor, the Q point of the former shifted higher up the loadline toward saturation. (See data in Table 9.4). 3. a. Table 9.6 Fixed bias % Δ I C % Δ V CE % Δ I BB % Δ β % Δ β % Δ β Volt-divider The ideal circuit has Beta independence when the ratio of %Δ I C /%Δ β is equal to 0. Thus, the smaller the ratio, the more Beta independent is the circuit. Using this as a criterion of stability, it becomes apparent that the voltage divider bias circuit is the more stable of the two. 232

236 4. a. I C β(v CC.67)/R B B ma b. I C [R 2 /(R 1 + R 2 )*V CC.7]/[(R 1 R 2 )/β + R E ] ma c. In equation 4a, the Beta factor cannot be eliminated by a judicious choice of circuit components. In 4b however, if the quantity R 1 R 2 /β is made much smaller than R E, then I C is no longer dependent upon Beta. In particular: I C [R 2 /(R 1 + R 2 )*V CC.7]/R E ma In that case, we have achieved Beta independent biasing. 233

237 EXPERIMENT 10: EMITTER AND COLLECTOR FEEDBACK BIAS OF BJTs Part 1: Determination of β b. V B B (measured) 5.04 V V RC (measured) 4.04 V c. I B B (from measured) ( )/1.1 M 13.6 μa I C (from measured) 4.04/2.2 K 1.84 ma d. β 1.84 ma/13.6 μa 135 Part 2: Emitter-bias configuration a. Using KVL: 20 + I C * (1.01 M/β) +.67 V + I C * (2.23 K) 0 V therefore: I C (20.67)/9.1 K 2.1 ma I B B 2.1 ma/ μa b. and c. Table 10.1 Calculated Values Transistor type V B (V) V C (V) V E (V) V BE (V) V CE (V) 2N N B Transistor type I B (μa) I C (ma) 2N N Measured Values Transistor type V B (V) V C (V) V E (V) V BE (V) V CE (V) 2N N B Transistor type I B (μa) I C (ma) Beta 2N N d. See Table e. See Table f. In every case, the difference between calculated and measured values were less than 10% apart. 234

238 g. Table 10.3 % Δβ % Δ I C %Δ V CE % Δ I BB Part 3: Collector Feedback Configuration (R E 0 ohms) b. Using KVL: 20 + I C (3.2 K) + I C (395 K)/ V 0 V from which: I B B 21 μa and IC 3.4 ma Table 10.4 Calculated Values B Transistor type V B (V) V C (V) V CE (V) I B (μa) I C (ma) 2N N Table 10.5 Measured Values B Transistor type V B (V) V C (V) V CE (V) I B (μa) I C (ma) 2N N Table 10.6 % Δ β % Δ I C % Δ V CE % Δ I BB Part 4: Collector Feedback Configuration (with R E ) a. For 2N3904: 20 + I C (3.2 K) + I C (395 K/150) + I C (2.2 K) 0 V from which: I B B 15 μa and IC 2.4 ma for 2N4401: 20 + I C (3.2 K) + I C (395 K/286) + I C (2.2 K) 0 V from which: I B B 9.7 μa and IC 2.8 ma b. See Table c. See Table d. See Table e. See Table f. B Table 10.7 Calculated Values C (V) V E (V) V CE (V) I C (ma) I E (ma) I B (μa) B V Transistor V B (V) 2N N

239 B B Table 10.8 Measured Values Transistor V B (V) V C (V) V E (V) V CE (V) I C (ma) I E (ma) I B (μa) 2N N Part 5: Computer Exercises PSpice Simulation See Circuit diagram. Table 10.9 % Δ β % Δ I C % Δ V CE % Δ I BB See Circuit diagram. 236

240 8. %Δβ 8.87% 9. %ΔI B B 2.18% %ΔI C 6.50% %ΔI E 6.42% 10. %ΔV CE 7.43% 11. S(β) P(Q2N3904) mw P(Q2N2222) mw Yes 13. Yes, see circuit diagram above. 14. Yes, see circuit diagram above. PSpice Simulation See Circuit diagram. 7. See Circuit diagram. 237

241 8. %Δβ 8.64% 9. %ΔI B B 5.43% %ΔI C 2.75% %ΔI E 2.69% 10. %ΔV CE 4.96% 11. S(β) See circuit diagrams above. Part 6: Problems and Exercises 1. a. I C(sat) 20/(2.2 K K) 4.55 ma b. I C(sat) 20/3 K 6.67 ma c. I C(sat) 20/5.2 K 3.85 ma d. Beta does not enter into the calculations. 2. The Q point shifts toward saturation along the loadline. 3. a. Table Emitter bias % Δ I C % Δ V CE % Δ I BB % Δ β % Δ β % Δ β b. The smaller that ratio, the better is the Beta stability of a particular circuit. Looking at the results, which were computed from measured data, it appears that the collector feedback circuit with R E 0 ohms is the most stable. This is counter to expectations. Theoretically, the most stable of the two collector feedback circuits should be the one with a finite R E. Since the stability figures of both of those circuits are so small, the apparent greater stability of the collector feedback circuit without R E is probably the result of measurement variability. 4. Using KVL: V CC + I C /β*r B B + VBE + I C *R E 0 V from this: I C (V CC V BE )/(R B B/β + RE) ma This division results in: I C β(v CC V BE )/(R B B + β*re) ma If β*r E >>R B B then IC (V CC V BE )/R E ma 5. Using KVL: V CC + I C *R C + I C /β*r B B + VBE 0 V from this: I C (V CC V BE )/(R C + R B /β) B if R C >>R B B/β then IC (V CC V BE )/R C ma 6. Using KVL: V CC + I C *R C + I C /β*r B B + V from this: BE + I C *R E 0 V I C (V CC V BE )/(R C + R E + R B /β) B ma if (R C + R E )>>R B B/β then I C (V CC V BE )/(R C + R E ) ma 238

242 EXPERIMENT 11: DESIGN OF BJT BIAS CIRCUITS Part 1: Collector-Feedback Configuration a. R C (15 7.5)V/5 ma 1.5 Kohms R C (commercial) 1.5 ohms d. V RC (measured) 5.14 V V CEQ (measured) 7.7 V I CQ (from measured) 3.4 ma β(calculated) 104 e. The most critical values for proper operation of this design is the voltage V CEQ measured at 7.7 V. It being within 2.7% of the design makes this a workable design. f. R B /(β*r B C) 214 K/(104*1.5 K) 1.37 g. R F1 + R F2 189 K R B (commercial) B K h. No, the value of R B B is fixed both by VCC and V BE, neither of which changed. i. V RC (measured) 5.64 V V CEQ (measured) 9.27 V I CQ (from measured) 3.76 ma β(calculated) 3.73 ma/([9.27.7)/214 K] 108 j. The measured voltage V CE is somewhat high due to the measured current I C being below its design value. In general, the lowest I C which will yield proper V CE is preferable since it keeps power losses down. For the given specifications, this design, for small signal operation, will probably work since most likely no clipping will be experienced. k. R B /(β*r B C)(calculated) 214 K/(108*1.5 K) 1.4 R B /(β*r B C)(calculated) 1.34 (see above) The parameters of the circuit do not change significantly with a change of transistor. Thus, the design is relatively stable in regard to any Beta variation. l. S(β) 3.76 ma 3.4 ma)/3.4 ma.8 Part 2: Emitter-bias Configuration a. R C (calculated) [(V CC ( )]V/5 ma 1.2 K R C (commercial) 1.2 K b. R E (calculated) 1.5 V/5 ma 300 ohms R E (commercial) 285 ohms d. R B (measured) B R1 + R K R B (commercial) B 394 K 239

243 e. V RC (measured) 6.04 V V CE (measured) 7.55 V I C (from measured) 4.7 ma β(calculated) 144 f. All measured values are well within a 10% tolerance of the design parameters. This is acceptable. g. R B /(β*r B E) 9.6 h. R B (calculated) B 950 K R B (commercial) B 1 M i. Yes, it changed from 214 K to a value of 950 K. The increase in Beta was compensated for by the increase in R B B in such a way that ICQ, and consequently V C, V CEQ and V E remained constant. Hence, so did R C and R E. j. V RC (measured) 5.2 V V CEQ (measured) 8.6 V I CQ (calculated) 4.2 ma β(calculated) 372 k. The important voltage V CEQ was measured at 8.61 V while it was specified at 7.5 V. Thus, it was larger by about 12%. This is probably the largest deviation to be tolerated. If the design is used for small signal amplification, it is probably OK; however, should the design be used for Class A, large signal operation, undesirable cut-off clipping may result. l. The magnitude of the Beta of a transistor is a property of the device, not of the circuit. All the circuit design does is to minimize the effect of a changing Beta in a circuit. That the Betas differed in this case came as no surprise. m. (calculated)r B /(β*r B E) (2N3904) 10.4 (calculated)r B /(β*r B E) (2N4401) 9.6 n. S(β).66 Part 3: Voltage-divider Configuration a. R C (calculated) [25 ( )]V/5 ma 1.2 K R C (commercial) 1.25 K b. R E 1.5 V/5 ma 300 ohms R E (commercial) 285 ohms d. R 2 (calculated) 2.94 K R 2 (commercial) 3.2 K R 1 (calculated) 17.1 K R 1 (commercial) 18.2 VK 240

244 e. V RC (measured) 6.47 V V CEQ (measured) 7.09 V I CQ (calculated) 5.2 ma β(calculated) 144 The difference between the calculated and the measured values of I CQ and V CEQ are insignificant for the operation of this circuit. f. R 1 R 2 /(β*r E ).066 g. V RC (measured) 6.98 V V CEQ (measured) 6.47 V I CQ (calculated) 5.6 ma β(calculated) 368 h. The measured values of the previous part show that the circuit design is relatively independent of Beta. i. The Betas are about the same. j. R 1 R 2 /(β*r E ) (2N4401).026 R 1 R 2 (β*r E ) (2N3904).066 k. S(β).051 Part 4: Problems and Exercises 1. Table 11.1 Configuration I CQ (ma) V CEQ (V) Collector-feedback Emitter-bias Voltage-divider The critical parameter for this design is the voltage V CEQ. Given that its variation for the various designs is less than 10%, the results are satisfying. 2. B Table 11.2 Configuration Stability factors R B /(β RC) S(β) Collector-feedback Emitter-bias Voltage-divider The data in adjacent columns is consistent. The voltage-divider bias configuration was the least sensitive to variations in Beta. This is expected since the resistor R 2, while decreasing the current gain of the circuit, stabilized the circuit in regard to any current changes. 241

245 3. Using KVL: V CC + I C *R C + I C /β*r B B + VBE 0 V from which: I C (V CC V BE )/(R C + R B )/β) B ma for stable operation, make: R C >>R B B/β 4. Using KVL: V CC + I C /β*r B B + IC * R E + V BE 0 V from which: I C (V CC V BE )/(R E + R B )/β) B ma for stable operation, make: R E >>R B B/β 5. Using KVL: V BB + I C /Beta*R 1 R 2 + V BE + I C *R E 0 V where: V BB R 1 /(R 1 + R 2 )*V CC from which: I C (V BB V BE )/(R E + R 1 R 2 /β) ma for stable operation: make R E >>R 1 R 2 /β Part 5: Computer Exercises PSpice simulation See Circuit diagram. 2. β S Yes 5. See Circuit diagram above. 242

246 PSpice simulation See Circuit diagram. 2. β S No 5. See Circuit diagram. 6. Yes 7. Not needed 8. See circuit diagram above. 243

247 EXPERIMENT 12: JFET CHARACTERISTICS Part 1: Measurement of the Saturation Current I DSS and Pinch-off Voltage V P c. V R (measured).754 V d. ID SS 7.44 ma e. V p (measured) 2.53 V f. 1. ID SS 8.3 ma, V p 3.1 V 2. ID SS 9.1 ma V p 3.9 V It is extremely unlikely that two 2N4416 ever have the same saturation current and pinch-off voltage. Fig 12.1 Part 2: Drain-Source Characteristics a. through d. Table 12.1 V GS (V) V DS (V) I D (ma) I D (ma) I D (ma)

248 Fig 12.3 ID SS (Fig 12.3) 7.5 ma ID SS (Part 1) 7.44 ma V P (Fig 12.3) 3 V V P (Part 1) 2.53 V Part 3: Transfer Characteristics a. b. Table 12.2 V DS (V) 3V 6V 9V 12V V GS (V) I D (ma) I D (ma) I D (ma) I D (ma) d. Given that the various variables in the above Table vary by less than 10%, it is reasonable that the curves can be replaced on an approximate basis by a single curve defined by Shockley s equation if the average values of both ID SS and V GS(off) are used. Part 5: Problems and Exercises 1. Shockley s equation involves four parameters. Given two of them, such as I D and V GS, an infinite number of curves can be drawn through their interception all of which can satisfy Shockley s equation for particular ID SS and V P. 2. V G V P *[1 (I D /ID SS ) 1/2 ] V 3. For: ID SS 10 ma; V P 5 V; and I D 4 ma V GS (calculated) ( 5)*[(.4) 1/2 ] 3.16 V a. gm O (calculated) 2*(7.44 ma)/ ms b. The slope of the Shockley curve is maximum at V GS 0 V. c. gm(calculated) gm O (1 V P /V P ) 0 S when V GS V P. The slope of the transfer curve at V GS V P 0 S 245

249 d. V GS /V P 1/4 V GS /V P 1/2 V GS /V P 3/4 g m 4.41 ms 2.94 ms 1.47 ms Note: gm ms e. The slope is a constant value. f. It is proportional to the derivative of Shockley s equation. Part 6: Computer Exercises PSpice Simulation See Circuit diagram. PSpice Simulation 12-2 Part A 4. See Probe Plot page I DSS 16 ma 6. V P 1.5 V Part B 4. See Probe plot page I DSS 18.2 ma V P 1.4 V 246

250 247

251 248

252 EXPERIMENT 13: JFET BIAS CIRCUITS Part 1: Fixed-Bias Network b. ID SS 12 ma c. V P (measured) 6 V e. I D 12 3 (1 1/6) 1/ ma f. V RD (measured) 8 V I DQ (measured) 8.2 ma R D (measured) 976 ohms Part 2: Self-Bias Network b. I DQ 2.64 ma V GSQ 3.3 V c. V GS (calculated) 3.3 V V D (calculated) 12.4 V V S (calculated) 3.1 V V DS (calculated) 9.3 V V G (calculated) 0 V d. V GS (measured) 3.4 V V D (measured) 12.2 V V S (measured) 2.1 V V DS (measured) 9.1 V V G (measured) 0 V The percent differences are determined with the calculated values as the reference. V GS (calculated %) 3.1% V D (calculated %) 1.6% V S (calculated %).64% V DS (calculated %) 2.3% V G (calculated %) 0% Part 3: Voltage Divider-Bias Network b. For voltage divider-bias-line see Fig c. I DQ (calculated) 4.8 ma V GS (calculated) 2.4 V d. V D (calculated) 10.3 V V S (calculated) 5.2 V V DS (calculated ) 5.1 V e. V GSQ (measured) 2.3 V V D (measured) 10.4 V V S (measured) 5.3 V V DS (measured) 5.1 V 249

253 f. The percent differences are determined with calculated values as the reference. V GS (calculated %) 4.2 % V D (calculated %).97% V S (calculated %) 1.9% V DS (calculated %) 1.2% g. I DQ (measured) 4.8 ma I DQ (calculated %).4% Part 4: Computer Exercises PSpice Simulation μa V V mw 5. See Circuit diagram. 6. Negligible due to back bias of gate-source function mw 8. No 250

254 PSpice Simulation See circuit diagram. 9. No 251

255 EXPERIMENT 14: DESIGN OF JFET BIAS CIRCUITS Part 1: Determining ID SS and V P b. ID SS (measured) 10.8 ma c. V P (measured) 6 V Part 2: Self-bias Circuit Design a. ID Q (calculated) 5.4 ma V DSQ (calculated) 15 V V DD (calculated) 30 V d. R S (calculated) 1/g m 333 ohms R S (commercial) 330 ohms e. V RD V DD V DSQ V RS V R D 2.4 K f. V DSQ (measured) 14.7 V I DQ (measured) 5.6 ma V DSQ (calculated) 15 V I DQ (calculated) 5.4 ma g. Agreements between calculated and measured values are within 10% of each other and thus are within acceptable limits. h. V DSQ (measured) 13.7 V I DQ (measured) 6 ma ID SS (borrowed JFET) 9.8 ma V P (borrowed JFET) 5.1 V Even though in our case, the variations between JFETs was relatively small, such may not be the case in general. Thus, the values of the biasing resistors for the same bias design but employing different JFETs may differ considerably. Best is not to use the arithmetic but the geometric average for the range of ID SS and V P. Thus in our case, the geometric averages would be: ID SS (geometric average) [ID SS(min) * ID SS(max) ] 1/2 [5 ma*15ma)] 1/ ma V P (geometric average) [1*6] 1/ V Statistically, these values are most likely the ones encountered. Part 3: Voltage-divider Circuit Design a. V GS (calculated) 2.6 V b. R S (V GG V GS )/I DQ (6 2.6)V/4 ma 850 ohms R S (commercial value) 820 ohms V G (calculated) V GS + I D *R S ma* V 252

256 c. V RD (calculated) V DD V DSQ V RS V where V RS I DQ *R S 4 ma* V R D [V DD (V DSQ + V RS )]/I D [20 ( )] 2.18 Kohms R D (commercial value) 2 Kohms d. R 2 10*R S 10* Kohms R 2 (commercial value) 10 Kohms Solving equation 14.3 for R 1 we obtain: R 1 R 2 *(V DD V G )/V G 10 K*( )/ Kohms R 1 (commercial value) 22 Kohms e. V DSQ (measured) 7.9 V ID Q (measured) 4.2 ma V DSQ (specified) 8 V I DQ (specified) 4 ma f. %I DQ (calculated) 5% %V DSQ (calculated) 1.25% Such relative small percent deviations are almost too good to be true. The voltage divider bias line is parallel to the self-bias line. To shift the Q point in either direction, it is easiest to adjust the bias voltage V G to bring the circuit parameters within an acceptable range of the circuit design. g. In the present case, the percent differences for I DQ and V DSQ were well within the 10% tolerance allowed. If not, the easiest adjustment would be the moving of the voltagedivider bias line parallel to itself by means of raising or lowering of V G. This could best be accomplished by a change of the voltage divider R 2 /(R 1 + R 2 )*V DD. Its value determines the voltage V G which in turn determines the Q point for the design. h. V DSQ (measured) 13.7 V I DQ (measured) 3.68 ma I DSS (borrowed JFET) 9.8 ma V P (borrowed JFET) 5.1 V Part 4: Problems and Exercises 1. R D (commercial value) 2.7 Kohms R S (commercial value) 180 ohms 2. R D (commercial value) 2.4 Kohms R S (commercial value) 680 ohms R 1 (commercial value) 6.8 Kohms R 2 (commercial value) 33 Kohms 253

257 3. In the design, use the geometric mean of both the given ranges on IDSS and VP for a given type JFET. Part 5: Computer Exercises PSpice Simulation See circuit diagram. PSpice Simulation See circuit diagram. 254

258 2. See circuit diagram. 3. See above circuit diagrams. 4. %V DS 7.37% 5. Yes 255

259 EXPERIMENT 15: COMPOUND CONFIGURATIONS Part 1: Determining the BJT(β) amd JFET (I DSS and V P ) Parameters a. R B (measured) B 982 Kohms R C (measured) 2.6 Kohms I B B (VCC V BE )/R BB (20.7)/982 K 19.7 μa V RC (measured) 6.45 V I C V RC /R C 6.45/2.6 K 2.48 ma β(calculated) 1.48 ma/19.7 μa 126 Part 2: Capacitive-Coupled Multistage System with Voltage-Divider Bias b. V B1 4.7 K/(4.7 K + 15 K)* V V E V I E1 I C1 V E1 /R E1 4.1/1 K 4.1 ma V C1 V CC I C1 * R C ma*2.7 K 9.2 V V B2 2.4 K/(2.4 K + 15 K)* V V E V I E2 I C2 V E2 /R E2 2.1/ ma V C2 V CC I C2 * R C ma * 1.2 K 14.5 V Table 15.1 V B1 (V) V C1 (V) V B2 (V) V C2 (V) Calculated Values Measured values % Difference As can be seen from the above data, the differences between the calculated and measured values were much less than 10%. f. We note that the voltages V C1 and V B2 are not the same as they would be if the voltage across capacitor C C was 0 Volts, indicating a short circuit across that capacitor. Part 3: DC-Coupled Multistage Systems Use the same equations to determine the circuit parameters as in Part 2 except that V B2 V C1. b. Table 15.2 V B1 (V) V C1 (V) V B2 (V) V C2 (V) Calculated Values Measured values % Difference Again, the percent differences between calculated and measured values are less than 10% in every instance. 256

260 f. The dc collector voltage of stage 1 determines the dc base voltage of stage 2. Note that no biasing resistors are needed for stage 2. Part 4: A BJT-JFET Compound Configuration b. V B B 4.7 K/(4.7 k + 15 k) * V V E V B B.7 V 6.5 V I E I D 6.5 V/1.2 K 5.4 ma V D V DD *R D ma* V For the JFET used: ID SS 10.1 ma V P 3.2 V determine V GS : I D /ID SS [1 V GS /V P ] 1/2 ma 5.4 ma/10.1 ma [1 V GS /3.2] 1/2 ma therefore: [5.4 ma/10.1 ma] 2 [1 V GS /3.2].286 [1 V GS /3.2] from which: V GS (1.286)* V remember: V GS is a negative number: V C V B B VGS 7.2 ( 2.28) 9.5 V Table 15.3 V B (V) V D (V) V C (V) Calculated Values Measured values % Difference d. See Table e. Differences were less than 10%. f. V GS (calculated from measured values) V B B VC V V GS (measured) 1.7 V g. V RD V DD V D V I D 5.3 V/ ma I D (measured) 6.4 ma The percent difference between the measured and the calculated values of I D was 18.5%, with the calculated value of I D used as the standard of reference. V E (calculated) V I C (calculated) 6.5 V/1.26 K 5.2 ma I C (measured) 5.06 ma 257

261 The percent difference between the measured and the calculated values of I C was 2.7%, with the calculated value of I D used as the standard of reference. Part 5: Problems and Exercises 1. a. There will be a change of V B B and VC for the two stages if the two voltage divider configurations are interchanged. b. The voltage divider configuration should make the circuit Beta independent, if it is well designed. Thus, there should not be much of a change in the voltage and current levels if the transistors are interchanged. 2. Again, depending on how good the design of the voltage divider bias circuit is, the changes in the circuit voltages and currents should be kept to a minimum. Part 6: Computer Exercises PSpice Simulation See below. 258

262 PSpice Simulation See below. 259

263 260

264 EXPERIMENT 16: MEASUREMENT TECHNIQUES Part 1: AC and DC Voltage Amplitude Measurements DC MEASUREMENT e. V O (calculated) 2K/(2K K)* V f. V O (measured) 3.78 V %Diff. (calculated) 2% g. V O (measured shift) 3.8 V The shift was down from the center of the screen. There is almost complete agreement between the two sets of measurements. The measurement taken with the DMM is the more accurate of the two, especially for a DMM, since it reads to 1/100 of a volt. AC MEASUREMENTS h. V i(rms) (calculated) 8/2* V i. V O(rms )(calculated) [(2 K 3.9 K + j0)*( j0)]/(2.41 K j1.59 K) V j. V O (measured) 1.31 V % diff. (calculated) 1.51% k. V O(p p) (measured) 3.72 V l. If we convert the measured rms value of V O to peak value, we obtain 3.78 volts. Comparing that to the measured peak value of V O which was 3.72 V, we can be satisfied with the results. Part 2: Measurements of the Periods and Fundamental Frequencies of Periodic Waveforms b. Horizontal sensitivity 100 μs/div c. number of divisions 5.6 d. Period(T) 100 μs/div*5.6 div 560 μs e. Frequency(f) 1/T 1/560 μs 1800 Hz f. f(dial setting) 1750 Hz g. The dial setting on the signal generator at best can only give an approximate setting of the frequency. h. f(counter) 1810 Hz i. Indeed it is, the difference between calculated and measured values is only 10 Hz using the counter, whereas the difference between signal generator setting and calculated values was 50 Hz. That measurement which is closest to that of the counter is the better measurement. In our case, the scope measures better than the signal generator. 261

265 Part 3: Phase-Shift Measurements b. V i(rms) (calculated) 6/2* V c. V O(rms) (0 j1.59 K)*( j0)/(1k j1.59 K) V V O(p p)(rms) 1.81*1.41*2 5.1 V f. A (number of divisions).8 g. B (number of divisions) 10 h. angle θ(calculated) 31.6 degrees j. The network is a lag network, i.e., the output voltage V O lags the input voltage by the angle theta, in our case it lags it by 31.6 degrees. k. V R(rms) (calculated) 1.1 V V R(p p) (calculated) 3.1 V angle theta 58.4 degrees The output voltage V O leads the input voltage by 58.4 degrees. Note that an angle of 58.4 degrees is the complement of an angle of 31.6 degrees. l. V R(p p) (measured) 3 V angle θ 58 degrees It s a lead angle. Part 4: Loading Effects c. V O(p p) (calculated) 1 K/(1 K + 1 K)*8 4 V d. V O(p p) (measured) 3.98 V f. V O(p p) (calculated) 1 M/(1 M + 1 M)*8 4 V V O(p p) (measured) 2.7 V g. The real part of the input impedance of the scope is now in parallel with the R2 resistor and since for many scopes, that real part is about 1 Mohm, therefore, R scope R kohms. Thus, V O is considerably reduced. h. R (prime) 1 M/[Vi/V O 1] 1 M/[8/2.7 1] 588 kohms R (scope) R (prime) *R 2 /[R (prime) R 2 ] 1.43 Megohms Most general purpose oscilloscopes have an input impedance consisting of a real part of 1 Megohms in parallel with a 30 pf capacitor. The result obtained for the real part of that impedance is reasonably close to that. i. V O(p p) (calculated) 1 K/(1 K + 1 M)*8 8 mv j. V O(p p) (measured) 7.9 mv k. The results agree within 1.25 percent. 262

266 Part 5: Problems and Exercises 1. No. for the frequency of operation, the capacitor represents an impedance of 1.59k 90 ohms. Therefore, in relationship to the existing resistors in the circuit, it cannot be neglected without making a serious error. 2. It depends upon the waveform. In case of sinusoidal voltages, the advantage is probably with the DMM. For more complex waveforms, the nod goes to the oscilloscope. 3. For measuring sinusoidal waves, the DMM gives a direct reading of the rms value of the measured waveform. However, for non-sinusoidal waves, a true rms DMM must be employed. The oscilloscope only gives peak-peak values, which, if one wants to obtain the power in an ac circuit, must be converted to rms. 4. T 5 div*.1 ms/div.5 ms f 1/T 1/.5 ms 2 KHz 5. angle theta 1.5/8* degrees V O /V i R /(R + R 1 ) therefore: V i /V O (R + R 1 )/R solving for R : R (V i /V O ) R + R 1 R (V i /V O 1) R 1 Hence: R R 1 /(V i /V O 1) ohms Part 6: Computer Exercises PSpice Simulation See Probe plot page See Probe plot page See Probe plot page See Probe plot page V out 9. See Probe plot page See Probe plot page V in(rms) 2.84 V V out(rms) 1.32 V 12. Yes 13. See Probe plot page See Probe plot page R3 2 K V out (12 V) (12 V) R2 + R3 ( K) V 16. Agree 263

267 264

268 265

269 266

270 267

271 PSpice Simulation Using VOM, R2 100 kω 2. Using DMM, R2 1 kω 3. For R2 1 kω 4. Both circuits 5. No 268

272 EXPERIMENT 17: COMMON-EMITTER TRANSISTOR AMPLIFIERS Part 1: Common-Emitter DC Bias b. V BB R 2 /(R 1 + R 2 ) * V CC 10 K/(10 K + 33 K) * V V E V BB V V C V CC I C * R C ma * 3 K 5.1 V I E V E /R E 1.63/1 K 1.63 ma r e 26 mv/i E 26 mv/1.63 ma 16 ohms c. V B (measured) B 2.25 V V E (measured) 1.57 V V C (measured) 4.95 V I E V E /R E 1.57/ ma r e 26 mv/1.6 ma 16.2 ohms The two values for r e obtained are within.2 ohms. This represents a 1.25 percent difference. Part 2: Common-Emitter AC Voltage Gain a. A V (no load) RC/re 3.2 K/ b. V sig 8.3 mv(rms) V O (no load) 1.47 V (rms) A V (no load) 177 The two values of A V agree within 10.6 percent of each other. Part 3: AC Input Impedance, Z i Z in R 1 R 2 Beta * r e 10 K 33 K (150 * 16) 1.8 Kohms V i (measured) 12 mv (rms) V sig 20 mv(rms) Z in [12 mv/(20 mv 12 mv)] * 1 K 1.5 Kohms The two values of the input impedance were within 18.9% of each other. This relatively large divergence is in part the result of using an assumed value of Beta for our transistor. For a 2N3904 transistor, the geometric average of Beta is closer to 126. Part 4: Output Impedance a. Z O (calculated) R C 3.2 Kohms b. V sig(rms) 10 mv (rms) V O (no load)(rms) 1.8 V (rms) V O (loaded)(rms).913 V(rms) R L 3.2 Kohms Z O [(V O V L )/V L ] * R L [( )/.913] * 3.2 K 3.1 K The two values for Z O are within 3.15% of each other. 269

273 Part 6: Computer Analysis PSpice Simulation See Circuit diagram. 2. r e 6.93 Ω 3. See Probe plot page See Probe plot page As I(B) increases, so does I(C). As I(C) increases, so does V(RC) and V(RE). Therefore V(C) decreases. 7. Z in (theoretical) Ω 8. See Probe plot page See Probe plot page Z in (PSpice) k Z in (theoretical) Determining output impedance 1. Z out RC 3 k 2. See Probe plot page See Probe plot page Z out (PSpice) k RC 270

274 271

275 272

276 273

277 EXPERIMENT 18: COMMON-BASE AND EMITTER-FOLLOWER (COMMON-COLLECTOR TRANSISTOR AMPLIFIERS Part 1: Common-Base DC Bias a. V B (calculated) B 10 K/(10 K + 33 K) * V V E V B B.7 V 1.63 V I E I C V E /R E 1.63 V/1 K 1.63 ma V C 10 I C * R C 10 (1.63 ma) * 3 K 5.1 V r e 26 mv/i E 26 mv/1.63 ma 16 ohms b. V B (measured) B 2.26 V V E (measured) 1.57 V V C (measured) 4.95 V I E (from measured values) V E /R E 1.57 V/ ma r e (from measured values) 26 mv/i E 26 mv/ ohms In every case, the differences between the two sets of values are less than 10% apart. Such divergence is not excessive given the variability of electronic components. Part 2: Common-Base AC Voltage Gain a. A V (calculated) R C /r e 3.2 K/ b. V sig 50 mv V O 2.43 V A V 2.43/V sig 2.43/ The two gains differed by 38 percent with the calculated gain used as the standard of comparison. Part 3: CB Input Impedance, Z i a. Z i r e 16.3 ohms b. V sig 50 mv V i 9.9 mv R X 100 ohms Z i [V i /(V sig V i )] * R X [9.9 mv/(50 mv 9.9 mv)] * ohms The two values of the input impedance differed by 45 percent with the theoretical value of r e (16.3 ohms) used as the standard of comparison. Part 4: CB Output Impedance, Z O a. Z O R C 3.2 K b. V sig 20 mv V O (measured, no load) 2.43 V V L (measured, loaded) 1.22 V Z O [(V O V L )/V L ] * R L [( )/1.22] * 3 K 3.18 Kohms The agreement between the two values of the output impedance is within less than 1 percent. 274

278 Part 5: Emitter-Follower DC Bias a. V B (calculated) B 2.33 V V E (calculated) 1.63 V I E (calculated) 1.63 V V C (calculated) 10 V r e (calculated) 26 mv/i E 26 mv/1.63 ma 16 ohms b. V B (measured) B 2.26 V V E (measured) 1.78 V V C (measured) 10.1 V I E V E /R E 1.78 V/1 K 1.78 ma r e 26 mv/1.78 ma 14.3 ohms Part 6: Emitter-Follower AC Voltage Gain a. A V R E /(R E + r e ) 1 K/(1 K ).986 b. V sig 1 V V O (measured).987 V A V V O /V sig.987/1.987 The two values of gain are within.1 percent of each other. Part 7: Emitter Follower (EF) Input Impedance, Z i a. Z i R 1 R 2 (Beta * (1 K + r e ) 7.31 Kohms b. V sig 2 V R X 10 Kohms f 1 KHz V i (measured).85 V Z i [V i /(V sig V i )] * R X [.85/(2.85)] * 10 K 7.39 Kohms The input impedance calculated from measured values is within 1.1 percent of the theoretically calculated value of Z i. Part 8: Emitter Follower (EF) Output Impedance, Z O a. Z O r e 16 ohms b. V O (measured) 19.8 mv V L (measured) 11.2 mv Z O [(V O V L )/V L ]*R L [(19.8 mv 11.2 mv)/11.2 mv] * ohms In the theoretical formulation, Z O was equated with r e, this is an approximation. A better expression for the output impedance is: Z O r e + (R G R 1 R 2 )/Beta. Thus it can be seen that the given formulation was actually a minimum value of the output impedance. 275

279 Part 9: Computer Analysis PSpice Simulation 18-1 Bias Point Analysis 1. See Circuit diagram. 2. See circuit diagram. 4. r e Ω 5. A v Z in r e Ω 7. Z out 3 kω Transient Analysis 1. See Probe plot page A v , see Probe plot page 278. Input Impedance 1. Z in 20.7 Ω, see Probe plot page 279. Output Impedance 1. Z out 2.87 kω, see Probe plot page

280 277

281 278

282 279

283 280

284 PSpice Simulation 18-2 Bias Point Analysis 1. See Circuit diagram. 2. See circuit diagram. 4. r e Ω 5. A v Z in 7.31 kω 7. Z out r e kω Transient Data 1. See Probe plot page Input Impedance kω Output Impedance Ω 281

285 282

286 EXPERIMENT 19: DESIGN OF COMMON-EMITTER AMPLIFIERS Part 2. Computer Analysis PSpice Simulation See Circuit diagram. 3. β V CE 4.78 V 5. Yes Transient Analysis 1. A V Yes 4. Z in 2.78 kω 5. Yes 8. Z out kω 9. Yes Part 3: Build and Test CE Circuit b. V B (measured) B 1.54 V V E (measured).87 V V C (measured) 7.15 V I C I E V E /R E.87 V/ ma r e 26 mv/i E 26 mv/.89 ma 29.3 ohms c. V sig 10 mv V L (measured).815 V A V (R C R L )/r e (3.2 K 10.2 K)/ d. V sig 20.5 mv R X 3.17 Kohms V i (measured) 8.8 mv Z i (R 1 R 2 Beta*r e ) (100.2 K 21.6 K 100 * Kohms e. V O (measured) 1.08 V Z O (V O V L )/V L *R L ( )/.82 * 10.2 K 3.25 Kohms 283

287 f. Design parameter Measured value A V 100 min Z i (Kohms) 1 Kmin K Z O (Kohms) 10 Kmax K V O max(p p) 3 Vp p min. 7.1 Vp p The design of the circuit was successful with all parameters, but the gain, meeting and even exceeding the design specification. The gain is about 20 percent below the expected value. To increase it, the supply voltage V CC could be increased. This would increase the quiescent current, lower the dynamic resistance r e and consequently increase the gain of the amplifier. 284

288 EXPERIMENT 20: COMMON-SOURCE TRANSISTOR AMPLIFIERS Part 1: Measurement of I DSS and V P a. I DS 9.1 ma b. V P 2.9 V Part 2: DC Bias of Common-Source Circuit a. V GS 1.33 V I D 2.55 ma V D V DD I D * R D ma * 2.2 K 13.8 V c. V G (measured) 0 V V S (measured) 1.46 V V D (measured) 13.8 V V GS (measured) 1.37 V I D V D /R S 13.8/ ma The agreement between calculated and measured values was in most cases within 10 percent of each other, the exception being the 17.3 percent difference between the calculated and measured value of I D. Part 3: AC Voltage Gain of Common-Source Amplifier a. A V g m R D where g m I DSS /(2 * V P ) * (1 V GS /V P ) 2 2 * 9.1 ma/2.9 * (1 1.33/2.9) 3.4 ms therefore: A V 3.4 ms * 2.2 K 7.48 b. V sig 10 mv f 1 KHz V O (measured) 758 mv A V V O /V sig 758 mv/100 mv 7.58 The difference between the theoretical gain and the gain calculated from measured values was only 1.34 percent. Part 4: Input and Output Impedance Measurements a. Z i R G Z i (expected) 1 Megohm b. Z O R D Z O (expected) 2.25 Kohms c. V i (measured) 37.2 mv Z i (calculated) V i * R X (V sig V i ) 592 Kohms 285

289 d. V O (measured) 760 mv R L (measured) 9.9 Kohms V L (measured) 620 mv Z O (V O V L ) * R L /V L (760 mv 620 mv) * 9.9 K/620 mv 2.24 Kohms The infinite input impedance of the JFET is predicated upon the assumption of the zero reverse gate current. Such may not be entirely true. Hence, we observe a 41 percent difference between the theoretical input impedance and the input impedance calculated from measured values. The two values of the output impedance are in far better agreement. They differ only by.44 percent. Part 5: Computer Exercises PSpice Simulation See Circuit diagram. 3. g mo ms; g m 7.48 ms 4. A v A v Z in kω 11. Z out 2.34 kω 13. A v 14. A R 4 kω v D 286

290 EXPERIMENT 21: MULTISTAGE AMPLIFERS: RC COUPLING Part 1: Measurement of I DSS and V P I DSS 10.4 ma V P 3.2 V Part 2: DC Bias of Common-Source Circuit a. V GS1 (calculated) 1.36 V I D1 (calculated) 3.1 ma V D1 (calculated) V DD I D1 * R D1 20 V 3.1 ma * 2.2 K 13.2 V V GS2 (calculated) 1.38 V I D2 (calculated) 3.54 ma V D2 (calculated) V DD I D2 * R D2 20 V 3.54 ma * 2.2 K 12.2 V c. V G1 (measured) 0 V V S1 (measured) 1.49 V D1 (measured) V V GS1 (measured) 1.04 V I D1 V S1 /R S V/496 3 ma V G2 (measured) 0 V V S2 (measured) 1.52 V V D2 (measured) 11.3 V V GS2 (measured).8 V I D2 V S2 /R S V/ ma The theoretical and the measured bias values were consistently in close agreement. Part 3: AC Voltage Gain of Amplifier a. For stage 2: A V2 g m2 (R D2 R L ) ( 3.64 ms)(2.2 K 10 K) 6.6 For stage 1: A V1 g m1 (R D1 Z i2 ) ( 3.51 ms)(2.2 K 1 M) 7.72 note: Z i2 R G2 1 Megohm A V A V1 * A V2 6.6 * b. V sig (measured) 20 mv V L (measured) 945 mv A V V L /V sig 945 mv/20 mv 47.3 V O1 (measured) 145 mv V sig (measured) 20 mv A V1 V O1 /V sig 145 mv/20 mv 7.25 A V2 V L /V O1 945 mv/145 mv 6.52 The voltage gains differed by less than 10 percent from each other. 287

291 Part 4: Input and Output Impedance Measurements a. Z i R G1 1 Megohm b. Z O R D2 2.2 Kohms c. V i1 (measured) 7.5 mv V sig 20 mv R X 1 Megohm Z i V i1 * R X /(V sig V i1 ) 7.5 mv * 1 M/(20 mv 7.5 mv) 600 Kohms d. V L (measured) 330 mv V O (measured) 410 mv Z O (V O V L ) * R L /V L (410 mv 330 mv) * 10 K/330 mv 2.42 Kohms Again, the input impedance calculated from measured values is about 40 percent below that which we expected from the assumption that the JFET was ideal and had no reverse gate current. This seems not to be the case in actuality. There is a reverse leakage current at the gate which reduces the effective input impedance below that of R G by being in parallel with it. The output impedances again are in reasonable agreement, differing by no more than 9 percent from each other. Part 5: Computer Exercise Pspice Simulation See circuit diagram. 3. g mo ms g mj ms g mj ms 4. A v A v A v

292 7. A v (A v1 )(A v2 ) (A v1 )(A v2 ) Yes 16. Interchange J1 with J2 17. Z in kω 20. Z out Ω 289

293 EXPERIMENT 22: CMOS CIRCUITS Part 1: CMOS Inverter Circuit Table 22.1 Table 22.2 IN OUT IN OUT 0V 5V 0V 5V 5V.3V 5 V.3 V Part 2: CMOS Gate Table 22.3 A B OUTPUT 0 V 0 V 5 V 0 V 5 V 0 V 5 V 0 V 0 V 5 V 5 V 0 V Part 3: CMOS Input-Output Characteristics a. IN (V) OUT (V) IN (V) OUT (V) IN (V) OUT (V) Part 4: Computer Exercise 1. See Probe plot page No VPlot data 1. See Probe plot page

294 291

295 292

296 EXPERIMENT 23: DARLINGTON AND CASCODE AMPLIFIER CIRCUITS Part 1: Darlington Emitter-Follower Circuit a. V B (calculated) B 2.21 V V E (calculated) 1.01 V A V R E /(R E + r e ) 47/( ).83 b. V B (measured) B 5.9 V V E (measured) 4.94 V I B (calculated) B 199 μa I E (calculated) 106 ma β(calculated) 106 ma/199 μa 535 c. V i (measured) 350 mv V O (measured) 340 mv A V V O /V i 340 mv/350 mv.97 Part 2: Darlington Input and Output Impedance a. Z i (calculated) 20.6 K (535 * 47) 11.3 Kohms Z O r e + (R G R B B)/β 9 ohms b. V sig 500 mv V i (measured) 55.6 mv Z i [V i /(V sig V i ) * Rx [55.6 mv/(500 mv 55.6 mv)] * 100 K 12.5 Kohms c. V O (measured) 492 mv V L (measured) 476 mv R L 100 ohms Z O [(V O V L )/V L ] * R L [(492 mv 476 mv)/476 mv] * ohms The two values of the input impedance differed by about 10.6 percent while the two values of the output impedance differed by 53 percent. It is to be noted however that with such small values the difference in just one ohm manifests itself as a large percent change. Given the tolerances of electronic circuit due to their components and that of the Darlington chip, the results are quite satisfactory. Part 3: Cascode Circuit a. V B1 (calculated) 5.5 V V E1 (calculated) 4.8 V V C1 (calculated) 11 V V B2 (calculated) 12 V V E2 (calculated) 11.3 V V C2 (calculated) 12.5 V I E1 V E1 /R E1 4.8 V/1 k 4.8 ma I E2 11.3/1.8 K 6.24 ma r e1 26 mv/i E1 26 mv/4.8 ma 5.4 ohms r e2 26 mv/i E2 26 mv/6.24 ma 4.2 ohms b. V B1 (measured) 4.69 V V E1 (measured) 4.0 V 293

297 V C1 (measured) 10.7 V V B2 (measured) 12.0 V V E2 (measured) 10.5 V V C2 (measured) 12.3 V I E1 (calculated) V E1 /R E1 4 V/1 K 4 ma I E2 (calculated) V E2 /R E2 10.5/1.8 K 5.2 ma r e1 26 mv/i E1 26 mv/4 ma 6 ohms r e2 26 mv/i E2 26 mv/5.2 mv 5 ohms c. A V1 1 (as per equation 23.5) A V2 R C /r e2 1.8 K/5 360 d. V sig 10 mv V i (measured) 8 mv V O2 (measured) 7.91 mv V O1 (measured) 948 mv A V1 (calculated) V O1 /V i 7.91/8 mv.98 A V2 (calculated) V O2 /V O1 948 mv/7.91 mv 120 A V V O2 /V i 948 mv/8 mv 119 The voltage gains for stage 1 were within 2 percent of each other, while the overall theoretical gain of 180 differs from the calculated gain from measured values by 34 percent. Part 4: Computer Exercises PSpice Simulation See circuit diagram. 2. r e 249 Ω 3. See Probe plot page See Probe plot page See Probe plot page A V Z in kω Z out 2.04 kω 294

298 295

299 PSpice Simulation See circuit diagram. 2. r eq Ω r eq Ω 5. See Probe plot page See Probe plot page RC 1.8 k For Q 1 ; A V r 5.63 Ω 319 re For Q 2 ; A V r e e Ω Ω 1 296

300 297

301 298

302 EXPERIMENT 24: CURRENT SOURCE AND CURRENT MIRROR CIRCUITS Part 1: JFET Current Source a. V DS (measured) 9.64 V b. I L (V DD V DS )/R L ( )/ ma c. Table 24.1 R L (ohms) V DS (Volts) I L (ma) Part 2: BJT Current Source a. I L 1.9 ma b. V E (measured).68 V V C (measured).404 V c. I E (calculated) 2.13 ma I L (calculated) 1.88 ma d. Table 24.2 R L (kohms) V E (Volts) V C (Volts) I E (ma) I L (ma) Part 3: Current Mirror a. I X.9 ma b. V B1.669 V V C V I X.89 ma I L 1.0 ma c. I X (calculated) 1 ma V B1 (measured).669 V V C2 (measured) 4.1 V I X.9 ma I L 1.5 ma 299

303 Part 4: Multiple Current Mirrors a. I X (calculated) 1 ma b. V B1 (measured).672 V V C2 (measured) 1.67 V V C3 (measured) 1.65 V I X 1.01 ma I L ma I L ma c. I X (calculated) 1 ma V B1 (measured).672 V V C2 (measured) 3.81 V V C3 (measured) 2.87 V I X 1.02 ma I L ma I L ma Part 5: Computer Exercise PSpice Simulation See circuit diagram. 2. I(R X ) μa I(R L ) ma 3. Yes 300

304 4. See Circuit diagram. 5. I(R X ) μa I(R L ) μa 6. Yes 8. Yes 10. Yes 11. No 12. Yes 301

305 EXPERIMENT 25: FREQUENCY RESPONSE OF COMMON-EMITTER AMPLIFIERS Résumé f L,1 1/(2 * 3.24 * 1.39 K * 10 μf) 11.5 Hz f L,2 1/(2 * 3.24 * 6.1 K * 1 μf) 26 Hz f L,E 1/(2 * 3.14 * 2.2 K * 20 μf) 3.62 Hz f H,i 1/(2 * 3.14 * 1.68 K * 960 μf) 98.7 KHz f H,O 1/(2 * 3.14 * 1.43 K * 45 pf) 2.43 MHz Part 1: Low-Frequency Response Calculations a. C be (specified) 100 pf C bc (specified) 10 pf C ce (specified) 15 pf C W,i (approximated) 20 pf C W,o (approximated) 30 pf b. β(measured) 126 c. V B B (calculated) 4.08 V V E (calculated) 3.38 V V C (calculated) 14 V I E (calculated) 1.54 ma r e 26 mv/i E 26 mv/1.54 ma 16.9 ohms d. A V (mid) (R C R L )/r e (3.9 K 2.2 K)/ e. f L,1 (calculated) 11.5 Hz f L,2 (calculated) 26.2 Hz f L,E (calculated) 3.62 Hz Part 2: Low Frequency Response Measurements b. V sig (measured) 30 mv V O (measured) 2.1 V A V (mid) 70 Table 25.1 f (Hz) K 2 K 3 K 5 K 10 K V O(p p) Table 25.2 f (Hz) K 2 K 3 K 5 K 10 K A V Part 3: High Frequency Response Calculations a. f H,I (calculated) 98.7 KHz f H,O (calculated) 2.47 MHz 302

306 b. Table 25.3 f (KHz) V O(p p) Table 25.4 f (KHz) A V Part 4: Plotting Bode Plot and Frequency Response Fig 25.2 from plot: f Hz f Hz Part 5: Computer Exercise PSpice Simulation See circuit diagram. 2. r e 17.2 Ω; A V mid See Probe plot Almost identical 6. See Probe plot page See Probe plot page log(78.028) both gains agree 303

307 304

308 305

309 EXPERIMENT 26: CLASS A AND CLASS B POWER AMPLIFIERS Part 1: Class A Amplifier: DC Bias a. V B B (calculated) 1.53 V V E (calculated).83 V I E (calculated) I C V E /R E.83/20 41 ma V C (calculated) 5.1 V b. V B B (measured) 1.59 V V E (measured).88 V V C (measured) 5.3 V I E (calculated) I C V E /R E.88/20 44 ma Part 2: Class-A Amplifier: AC Operation a. P i (calculated) 400 mw V O (calculated) 5.3 Vp p P O (calculated) 29.3 mw % efficiency (calculated) 7.3 percent b. V i (measured) 65 mv V o (measured) 5 Vp p c. P i 400 mw P O 26 mw % efficiency (calculated) 6.5 percent While the values for the power and the efficiency are fairly consistent between the theoretical and those calculated from measured values, the low efficiency of the amplifier is an undesirable feature. In general, Class A amplifiers operate close to a 25 percent efficiency. This circuit would need to be redesigned to make it a practical circuit. d. V i (measured) 32.5 mvp p V O (measured) 3 Vp p e. P i (calculated) 400 mw P O (calculated) 9.38 mw % efficiency (calculated) 2.3 percent f. P i 400 mw P O 93 mw % efficiency 2.3 percent As stated previously, while the data is consistent, the values of the efficiency makes this not a practical circuit. 306

310 Part 3: Class-B Amplifier Operation a. for V O 1 V peak P i (calculated) 1.59 W P O (calculated) 50 mw % efficiency (calculated) 3.1 percent for V O 2 V peak P i 1.59 W P O 200 mw % efficiency (calculated) 12.6 percent b. V i (measured) 2.9 Vp p V O (measured) 2.7 Vp p P i 890 mw P O 91 mw % efficiency 10.2% c. V i (measured) 5 Vp p V O (measured) 4 Vp p I dc (measured) 159 ma P i 1.27 W P O 637 mw % efficiency 50.2% Note that the efficiency of the Class B amplifier increases with increasing input signal and consequent increasing output signal. Also observe that the two stages of the Class B amplifier shown in Figure 26.2 are in the emitter follower configuration. Thus, the voltage gain for each stage is near unity. This is what the data of the input and the output voltages show. Note also, that as the output voltage approaches its maximum value that the efficiency of the device approaches its theoretical efficiency of about 78 percent. Part 4: Computer Exercises PSpice Simulation See Circuit diagram. 307

311 2. Yes. 3. V CE V V 4.98 V mw 5. Q 1 7. See Probe plot page Yes 9. No P o (AC) 4.59 mw 12. %η 1.04% 13. DC values remain the same P o (AC) 1.16 mw %η 0.26% See Probe plot page (10 V) 2 308

312 309

313 310

314 PSpice Simulation See circuit diagram. P i (DC) mw 2. Q 1 and Q 2 3. Yes. 4. V(E2) V 1 (10 V) 2 5. V(BE) Q V V(BE) Q V 6. Maintain proper bias across Q 1 and Q V 9. See Probe plot page V(OUT) p p V 11. %η 55.8% 14. V(OUT) p p V %η 16.1% 311

315 312

316 EXPERIMENT 27: DIFFERENTIAL AMPLIFIER CIRCUITS Part 1: DC Bias of BJT Differential Amplifier a. V B B (calculated) 0V V E (calculated).7 V V C (calculated) 5.43 V I E (calculated) 457 μa r e (calculated) 57 ohms B b. Q1 Q2 V B (measured).10 V 0 V V E (measured).65 V.65 V V C (measured) 5.10 V 4.9 V I E (calculated) 490 μa 510 μa r e 53 ohms 51 ohms Part 2: AC Operation of BJT Differential Amplifier a. A V,d (calculated) 179 A V,c (calculated).5 b. V O1 (measured) 1.48 V V O2 (measured) 1.43 V V O,d (V O,1 + V O,2 )/2 ( )/ V A V,d V O,d /V i 72.8 c. V O,c (measured).55 V A V,c V O,c /V i.55 Part 3: DC Bias of BJT Differential Amplifier with Current Source a. For either Q1 or Q2: V B B (calculated) 0 V V E (calculated).7 V V C (calculated) 9 V I E (calculated).5 ma r e (calculated) 52 ohms For Q3: V B B (calculated) 5 V V E (calculated) 5.7 V V C (calculated).7 V I E (calculated) 1 ma r e (calculated) 26 ohms 313

317 b. For Q1, Q2, and Q3: B Q 1 Q 2 Q 3 V B (measured) 47 mv 0 mv 4.69 V V E (measured).64 V.64 V 5.35 V V C (measured) 7.91 V 2.97 V.64 V I E (calculated) 110 μa 612 μa 783 μa r e (calculated) 236 ohms 42.5 ohms 33.2 ohms Part 4: AC Operation of Differential Amplifier with Transistor Current Source a. A V,d R C /(2 * r e ) 10 K/(2 * 57.8) 173 Part 5: JEFT Differential Amplifier a. For Q1: I DSS 7.9 ma V P 3.1 V For Q2: For Q3: I DSS 8.1 ma V P 3.4 V I DSS 11.2 ma V P 4.2 V b. V D,1 (calculated) 9.84 V V D,2 (calculated) 9.84 V V S,1 (calculated0.845 V c. V G,1 (measured) 0 V V D,1 (measured) 9.71 V V D,2 (measured) 9.72 V V D,3 (measured).84 V d. A V,d.184 e. V O,1 (measured) 50 mv V O,2 (measured) 46 mv A V1,d.5 A V2,d

318 Part 6: Computer Exercises Pspice Simulations See circuit diagram. P(DC) VCC mw P(DC) VEE mw 2. Practically yes 3. VCE ( ) VCE ( ) 6 V Q1 Q2 4. Yes. 5. I(Q 1 ) μa I(Q 2 ) μa 6. Yes 9. See Probe plot page (VOUT1) p p (VOUT2) p p 3.23 V phase shift See Probe plot page 317. A V See Probe plot page (VOUT1) p p (VOUT2) p p 0.98 V phase shift See Probe plot page 319. A V 0 315

319 316

320 317

321 318

322 319

323 Pspice Simulations See circuit diagram. P(DC) VCC mw P(DC) VEE mw 2. VC ( ) Q V VC ( ) Q V Yes 3. I(Q 1 ) μa I(Q 2 ) μa I(Q 3 ( μa IQ ( ) IQ ( ) IQ ( 3) 2 IQ ( 1) 2 IQ ( 2 ) 320

324 7. See Probe plot page Both voltages are V p p phase shift See Probe plot page 323. A V See Probe plot page mv p p phase shift See probe plot page 325. A V 0 321

325 322

326 323

327 324

328 325

329 EXPERIMENT 28: OP-AMP CHARACTERISTICS Part 1: Determining the Slew Rate f. 5 V p-p g. 12 us h V/us Part 2: Determining the Common Mode Rejection Ratio g. Vout(rms) V Vin(rms) 8.7 V h. A(cm) V(out)/V(in) i. A(dif)R1/R21000 j. CMR(dB) 90.4 db k. Published values: db Part 3: Computer Exercises PSpice Simulation: Determining the Slew Rate b. V(Vout) max 5 V V(Vout)min 0 V c. Time interval 12 us d. SR 0.40 us e. Published values: us PSpice Simulation: Determining the Common Mode Rejection Ratio b. A(cm) V(out)/V(in) 0.26 V/8.7 V 0.03 c. A(dif) R1/R d. CMR(dB) 90.4 e. Published values: db 326

330 EXPERIMENT 29: LINEAR OP-AMP CIRCUITS Part 1: Inverting Amplifier a. V O /V i (calculated) R O /R i 100 K/20 K 5 b. V O (measured) 4.87 A V V O /V i 4.87/ c. V O /V i (calculated) R O /R i 100 K/100 K 1 V O (measured) 1 V A V V O /V i 1.06/ d. Fig 29.6 Part 2: Noninverting Amplifier a. A V (calculated) (1 + R O /R i ) ( K/20 K) 6 b. V O (measured) 5.24 V A V V O /V i 5.25/ The two gains are within 12.5 percent of agreement. c. A V (calculated) ( K/100 K) 2 V O (measured) 2.17 V V O /V i 2.17 The two gains are within 8.5 percent of agreement. Part 3: Unity-Gain Follower a. V i (measured) 2.06 V V O (measured) 2.05 V The ratio of the computed gain from measured values is equal to.995, which is practically identical to the theoretical unity gain. 327

331 Part 4: Summing Amplifier a. V O (calculated) [100 K/100 K * K/20 K * 1] 6 V b. V O (measured) 5.02 V The difference between the two values of V O is equal to 16.3 percent. c. V O (calculated) [100 K/100 K * K/100 K*1] 2 V V O (measured) 2.01 V The difference between the two values of V O is equal to.5 percent. Part 5: Computer Exercises PSpice Simulation See Probe plot page (VOUT) peak 5 V (VIN) peak 1 V 3. Vo Rout A V 5 V R 4. VOUT 5 V 5 VIN 1 V 5. Yes Yes in in 328

332

333 PSpice Simulation See Probe plot page (VOUT) peak 6 V (VIN) peak 1 V 3. V o R out 100 kω Vin Rin 20 kω 4. V out 6 V 6 Vin 1 V 5. Yes Yes 6 330

334

335 EXPERIMENT 30: ACTIVE FILTER CIRCUITS Part 1: Low-Pass Active Filter a. f L (calculated) 1/(2 * 3.14 * 10 K *.001 μf) 15.9 KHz b. Table 30.1 Low Pass Filter f (Hz) K 2 K 5 K 10 K 15 K 20 K 30 K V O (V) c. Fig 30.4 d. f L (from graph) 15 KHz Part 2: High-Pass Filter a. f H 1/(2 * 3.14 * R 2 * C 2 ) 1/(2 * 3.14 * 10 K*.001 μf) 15.9 KHz b. Table 30.2 High-Pass Filter f (Hz) 1 K 2 K 5 K 10 K 20 K 30 K 50 K 100 K 300 K V O (V) c. Fig

336 d. f H (from graph) 15 KHz Part 3: Band-Pass Active Filter c. Table 30.3 Band-Pass Filter f (Hz) K 2 K 5 K 10 K 15 K 20 K 30 K V O (V) f (Hz) 50 K 100 K 200 K 300 K V O (V) d. Fig 30.6 Part 4: Computer Exercises PSpice Simulation See Probe plot page See Probe plot page Slight variance due to PSpice cursor position. 6. f C (calculated) KHz f C (numeric gain) KHz f C (log. gain) KHz 333

337

338

339 PSpice Simulation See Probe plot page See Probe plot page Numeric f C (low): KHz f C (high): KHz Bandwidth: KHz Logarithmic KHz KHz KHz 10. See tabulation in #9. 336

340

341

342 EXPERIMENT 31: COMPARATOR CIRCUITS OPERATION Part 1: Comparator with 74IC Used as a Level Detector a. R 3 10 Kohms, V ref 5 V R 3 20 Kohms, V ref 6.7 V c. V ref (measured) 4.97 V d. V i (measured) (LED goes on) 5.01 V V i (measured) (LED goes off) 4.98 V e. V ref (measured) 6.63 V V i (measured) (LED goes on) 6.65 V V i (mesasured) (LED goes off) 6.61 V All values of voltages measured and calculated relative to a particular R 3 are in very close agreement. Part 2: Comparator IC Used as a Level Detector a. R 3 10 Kohms V ref (calculated) 4.98 V R 3 20 Kohms V ref (calculated) 6.63 V c. V ref (measured) 4.97 V (R 3 10 Kohms) d. V i (measured) (LED goes on) 5.01 V V i (measured) (LED goes off) 4.97 V e. Replace R 1 with 20 Kohm resistor. V ref (measured) 6.67 (R 3 20 Kohms) V i (measured) (LED goes on) 6.69 V V i (measured) (LED) goes off) 6.65 V f. V i (measured) (LED goes on) 6.65 V V i (measured) (LED goes off) 6.67 V The agreement between calculated and measured values in every case was near perfect. Part 3: Window Comparator a. V + (pin5, calculated) 7.5 V V (pin6, calculated) 2.5 V c. V i (pin1, measured) 7.6 V V + (pin5, measured) 7.36 V V (pin6, measured) 2.3 V d. V i (measured) (LED goes on) 7.6 V V i (measured) (LED goes off) 2.6 V 339

343 e. V i (measured) (LED goes on) 7.46 V V i (measured) (LED goes off) 2.2 V f. V i (measured) (LED goes on) 7.46 V V i (measured) (LED goes off) 5.01 V Again as in the previous case, the agreement between measured and calculated values was excellent. Part 4: Computer Exercises PSpice Simulation See circuit diagram. 31-1: 2. V in 6 V; V ref 5 V 3. Yes. I(D1) ma 340

344 4-6. See circuit diagram. 31-1: 8. V in 4 V; V ref 5 V 9. No, I(D1) < 8 ma; I(D1) μa PSpice Simulation See Probe plot page

345

346 EXPERIMENT 32: OSCILLATOR CIRCUITS 1: THE PHASE-SHIFT OSCILLATOR Part 1: Determining Vout d. f(theoretical) 650 Hz f. Estimated setting of RPot 3 kohm g. Vout (peak-peak) 29 V h. Period 1.54 ms i. f(experimental) Hz j. Calculated % difference 0.15 k. RPot + Rf 29.5 kohm l. Open-loop gain 29.5 m. Calculated % difference 7.8% Part 2: PSpice Simulation b. Vout(peak-peak) 28.8 V c. Vout(period) 1.54 ms d. Vout(frequency) Hz e. Vout(peak-peak) 19.1 V f. Vout(frequency) Hz j. P(V(feedback) degrees P(V(VOUT) 89.4 degrees P(V(VOUT) P(V(feedback) 180 degrees 343

347 EXPERIMENT 33: OSCILLATOR CIRCUITS 2 Part 1: Wien Bridge Oscillator c. T (measured) 305 μs d. f 1/T 1/305 μs 3.28 KHz e. T (measured, C 0.01 μf) 3 ms f (calculated, C 0.01 μf) 328 Hz f. f (calculated, C.001 μf) 3.12 KHz f (calculated, C.01 μf) 312 Hz Again, the agreement between the two sets of values was well within 10 percent. Part 2: 555 Timer Oscillator c. T (measured) 20.1 μs d. f 1/T 49.3 KHz e. T (measured, C 0.01 μf) 203 μs f 1/T 4.93 KHz f. k frc.48 f 4.91 KHz The agreement between the two values differed by only.4 percent. Part 3: Schmitt-trigger Oscillator c. T (measured) 21 μs d. f 1/T 46.9 KHz e. T (measured, C 0.01 μf) 210 μs f 1/T 4.69 KHz f. f (calculated, C μf) 46 KHz f (calculated, C 0.01 μf) 4.6 KHz The measured and calculated values of the frequency for each capacitor were within 2 percent of each other. 344

348

349 PSpice Simulation See Probe plot page 347. (VOUT) min 0 V (VOUT) max 10 V 2. Yes μs 4. PW 8.63 μs 5. f 63.2 KHz 6. See Probe plot page Yes 8. No 9. P μs 10. PW μs 11. f KHz 12. Yes 346

350

351

352 EXPERIMENT 34: VOLTAGE REGULATION POWER SUPPLIES Note: The data obtained in this experiment was based on the use of a 10 volt Zener diode. Part 1: Series Voltage Regulator a. V L V Z V BE 10 V.7 V 9.3 V b. V O (measured) 9.3 V Table 34.1 V i (V) V O (V) The voltage regulation of the system was.54 percent. Part 2: Improved Series Regulator a. A 1 + R 1 /R K/2 K 1.5 V L A VZ V L (calculated) 15 V b. Table 34.2 V i (V) V L (V) Upon coming near the nominal voltage level, the regulation of the system was 2 percent. Part 3: Shunt Voltage Regulator a. V L (R 1 + R 2 ) * V Z /R 1 3 K/2 K * 10 V 15 V b. V L (measured) 14.7 V Table 34.3 V i (V) V O (V) The regulation of this system was 2.7 percent. Part 4: Computer Exercises PSpice Simulation See Probe plot page V in is swept linearly from 2 V to 8 V in 1 V increments. 3. V(V2) 4.68 V V(OUT) 4 V 4. Approx. at V(VIN)) 6.5 V V 6. Yes 7. V L 4.68 V 0.68 V 4 V 349

353

354 PSpice Simulation See Probe plot page V(IN) increases linearly from 6 V to 16 V in 0.5 V increments. 3. V L V(OUT) 1 k Ω+ 1 k Ω (4.68 V) 9.36 V 1 kω 4. V (OUT) 9.36 V theor. V (OUT) V PSpice 5. V(V2) 4.68 V V(VOUT) V 351

355

356 EXPERIMENT 35: ANALYSIS OF AND, NAND, AND INVERTER LOGIC GATES Part 1: The AND Gate: Computer Simulation a. Table 35-1 Input terminal 1 Input terminal 2 Output terminal Traces U1A:A and U1A:B are the inputs to the gate. Trace U1A:Y is the output of the gate. b. The output is at a logical HIGH if and only if both inputs are HIGH. c. Over the period investigated, the Off state is the prevalent one. d. Terminal 25 ms 125 ms 375 ms

357 Part 2. The AND Gate: Experimental Determination of Logic States a. Ideally, the same. b. 10 Hz c. Should be the same as that for the simulation. d. The amplitude of the TTL pulses are about 5 volts, that of the Output terminal 3 is about 3.5 volts. e. The internal voltage drop of across the gate causes the difference between these voltage levels. Part 3: Logic States versus Voltage Levels b. Example of a calculation: assume: V(V1A:Y) 3.5 volts, VY 3.4 volts 3.5V 3.4V %deviation * percent 3.5V c. For this particular example, the calculated percent deviation falls well within the permissible range. Part 4: Propagation delay a. For the current case, the propagation delay at the lagging edge of the applied TTL pulse should be identical to that at the leading edge of that pulse. Thus, it should measure about 18 nanoseconds. b. Ideally, the propagation delays determined by the simulation should be identical to that determined in the laboratory. c. From Laboratory data, determine the percent deviation using the same procedure as before. 354

358 Part 5: NOT-AND Logic A. Computer Simulation a. Table 35-2 Input1(7408) Input 2(7408) Input1(7404) Output(7404) Traces U1A: A and U1A:B are the inputs to the 7408 gate, U1A:Y its output trace. Trace U2A:Y is the output of the 7404 gate. b. The Output of the 7404 gate will be HIGH if and only if the input to both terminals of the 7408 gate are HIGH, otherwise, the output of the 7404 gate will be LOW. c. The most prevalent state of the Output terminal of the 7404 gate is HIGH. d. The PSpice cursor was used to determine the logic states at the requested times. The logic states are indicated at the left margin. At t 25 milliseconds: A m, 1 A , 1 dif m 355

359 At t 125 milliseconds A m, 1 A , 1 dif m At t 375 milliseconds A m, 0 A , 1 dif m B. Experimental Determination of Logic States a. They should be relatively close to each other. b. They are identical. c. The output of the 7404 gate is the negation of the output of the 7408 gate. 356

360 Part 6: The 7400 NAND Gate A. Computer Simulation Table 35-3 a. Input terminal 1 Input terminal 2 Output terminal b. B. Experimental Determination of Logic States Table 35-4 Input terminal 1 Input terminal 2 Output terminal

361 EXPERIMENT 36: ANALYSIS OF OR, NOR AND XOR LOGIC GATES Part 1: The OR Gate: Computer Simulation a. Table 36-1 Input terminal 1 Input terminal 2 Output terminal Traces U1A:A and U1A:b are the inputs to the gate. Trace U1A:Y is the output of the gate. b. The output is a logical LOW if and only if both inputs are LOW, otherwise the output is HIGH. c. Over the period investigated, the ON, or HIGH, state is the prevalent one. This differs from that of the AND gate. Its prevalent state was the OFF or LOW state. 358

362 d. The PSpice cursor was used to determine the logic states at the requested times. The logic states are indicated at the left margin. At t 25 milliseconds: A m, 1 A , 1 dif m At t 125 milliseconds A m, 1 A , 1 dif m At t 375 milliseconds A m, 0 A , 1 dif m 359

363 Part 2: The OR Gate: Experimental Determination of Logic States a. The pulse of 100 milliseconds of the TTL pulse is identical to that of the simulation pulse. b. The frequency of 10 Hz of the TTL pulse is identical to that of the simulation pulse. c. They were determined to be the same at the indicated times. d. The voltage of the TTL pulse was 5 volts. The voltage at the output terminal was 3.5 volts. e. The difference in these two voltages is caused by the internal voltage drop across the 7432 gate. Part 3: Logic States versus Voltage Levels a. The PSpice simulation produced the identical traces as shown on the PROBE plot for Figure b. Example of a calculation: assume V(V1A:Y) 3.6 volts, VY 3.4 volts 3.6V 3.4V %deviation * percent 3.6V a. It is larger by ( ) 2.7 percent. Part 4: Combining AND with OR Logic A. Computer Simulation a. 360

364 Table 36-2 U1A:A U1A:B U1A:Y U2A:A U2A:B U2A:Y U3A:A U3A:B U3A:Y c. At t 25 milliseconds A m, 1 A , 1 dif m At t 125 milliseconds A m, 1 A , 1 dif m 361

365 At t 375 milliseconds A m, 0 A , 1 dif m b. The output of the 7432 gate, U3A:Y, is evenly divided between the ON state and the OFF state during the simulation. B. Experimental Determination of Logic States a. The logic states of the simulation and those experimentally determined are identical. b. The logic state of the output terminal U3A:Y is identical to that of the TTL clock. c. The logic state of the output terminal U3A:Y is identical to that of the output terminal U2A:Y of the U2A gate. Part 5: NOR and XOR Logic combined A. Computer Simulation a. The output trace of the 7402 NOR gate, U1A:Y and the output trace of the XOR gate, U2A:Y are both shown in the above plot. 362

366 b. Table 36-3 U1A:A U1A:B U1A:Y U2A:A U2A:B U2A:Y c. The output of the 7402 gate, U1A:Y is HIGH if and only if both inputs are LOW, otherwise the output is LOW. d. This is a logical inversion of the OR gate. c. The output of the 7486 gate is HIGH if and only if the two inputs U2A:A and U2A:B are at opposite logic levels. f. The logic state of the OR gate is HIGH if both inputs are at opposite logic levels and if both inputs are HIGH. B. Experimental Determination of Logic States a. The experimental data is identical to that obtained from the simulation. b. Refer to the data in Table c. Refer to the data in Table d. Refer to the data in Table e. The output of the 7486 XOR gate is HIGH if and only if its input terminals have opposite logic levels, otherwise, its output is at a LOW. f. For an OR gate, its output is HIGH if both, or at least one input terminal, is HIGH. Its output will be LOW if both inputs are LOW. For an XOR gate, its output is HIGH if and only if both input terminals are at opposite logic levels, otherwise, the output will be LOW. g. The output of an XOR gate will be HIGH when both input terminals are at opposite logic levels. Otherwise, its output is at a logical LOW. 363

367 EXPERIMENT 37: ANALYSIS OF INTEGRATED CIRCUITS Part 1: Positive Edge-Triggered D Flip-Flop A. Computer Simulation a. The PROBE data shows the flip flop to be in the SET condition. b. The flip flop goes to RESET at 200 milliseconds because the D input terminal goes negative. The flip flop goes to SET at 400 milliseconds because both the CLOCK input and the D input are positive. c. The importance to note is that the D input can be negative and positive during the time that the Q output is low. d. After the initial SET condition of the flip flop, and after a RESET state of 200 milliseconds, the flip flop returns to its SET condition because at 400 milliseconds, both the CLOCK and the D inputs are positive. e. Starting from a SET condition, a transition to RESET will occur when the D input is negative and the CLOCK pulse goes positive. The flip flop will SET again when the D input is positive and the CLOCK goes positive. f. The conditions stated in previous answer define a positive edge triggered flip flop as defined in the first paragraph of Part 1. g. See above answers. h. 364

368 i. Let us assume that D is high when a positive CLOCK pulse goes high. This will SET the flip flop. This SET will be stored, or remembered, until D is negative and the CLOCK triggers positive again. At that time, the flip flop will RESET. This RESET will be stored, or remembered, until D is positive and the CLOCK triggers positive again. At that time the flip flop will SET. Events repeat themselves after this. B. Experimental Determination of Logic States a. Both input terminals are held at 5 volts during the experiment. b. The amplitude of the voltage of the TTL pulse is 5 volts. c. The amplitude of the output voltage at the Q terminal is 3.5 volts. d. The difference between the input voltages and the output voltage is caused by the voltage drop through the flip flop. e. The experimental and the simulation transition states occur at the same times. 365

369 Part 2: Frequency Division A. Computer Simulation Answer all questions below with reference to the following PROBE plot. a. The frequency at the U1A:Q terminal is 5 Hz. b. The frequency at the U1A:Q terminal is one-half that of the U1A:CLK terminal. c. The frequency at the U2A:Q terminal is 2.5 Hz. d. The frequency of the U2A:Q terminal is one-half that of the U2A:CLK terminal. e. The overall frequency reduction of the output pulse U2A:Q relative to the input pulse U1A:CLK is one-fourth. f. Each flip flop reduced its input frequency by a factor of two. g. It would take four flip-flops. B. Experimental Determination of Logic States. a. The J and CLR terminals of both flip flops are kept at 5 volts during the experiment. b. The voltage level of the U1A:CLK terminal is 5 volts. The voltage level of the U2A:CLK terminal is 3.5 volts. The voltage level of the U2A:Q terminal is 3 volts. 366

370 c. Refer to the above PROBE plot. d. Pulse U1A:CLK U1A:Q U2A:CLK U2A:Q Frequency 10.0 Hz 5.0 Hz 5.0 Hz 2.5 Hz e. They are identical. Part 3: An Asynchronous Counter: the 7493A Integrated Circuit A. Computer Simulation a. A m, 0 A , 0 dif m b. See PROBE plot above. d. t 175 milliseconds. There is one clock pulse to the left of the cursor. A m, 1 A , 0 dif m 367

371 e. t 375 milliseconds. There are three clock pulses to the left of the cursor. A m, 1 A , 0 dif m f. t 575 milliseconds. There are five clock pulses to the left of the cursor. A m, 1 A , 0 dif m g. t seconds. There are ten clock pulses to the left of the cursor. 368

372 A , 1 A , 0 dif h. At t milliseconds, the output terminals, QA, QB, QC and QD have resumed their initial states. i. The MOD 10 counts to ten in binary code after which it recycles to its original condition. j. The output terminal QA represents the most significant digit. k. The indicated propagation delay is about 12.2 nanoseconds. A , A , dif n, B. Experimental Determination of Logic States a. The logic states of the output terminals were equal to the number of the TTL pulses. b. The experimental data is equal to that obtained from the simulation. c. The propagation delay measured was about 13 nanoseconds. d. The difference in the experimentally determined propagation delay was 13 nanoseconds compared to a propagation delay of 12 nanoseconds as obtained from the simulation data. 369