Voltage Divider Bias

Transcription

1 Voltage Divider Bias ENGI 242 ELEC 222 BJT Biasing 3 For the Voltage Divider Bias Configurations Draw Equivalent Input circuit Draw Equivalent Output circuit Write necessary KVL and KCL Equations Determine the Quiescent Operating Point Graphical Solution using Load lines Computational Analysis Design and test design using a computer simulation 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 1

2 Voltage-divider bias configuration 23 February 2005 ENGI 242/ELEC Voltage Divider Input Circuit Approximate Analysis This method is valid only if R2.1 β RE Under these conditions RE does not significantly load R2 and it may be ignored: I B << I 1 and I 2 and I 1 I 2 Therefore: R2 V B = VCC R+R 1 2 We may apply KVL to the input, which gives us: -VB + VBE + IE RE = 0 Solving for IE we get: I E = V B- V BE RE 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 2

3 Input Circuit Exact Analysis This method is always valid must be used when R2 >.1 β RE Perform Thevenin s Theorem Open the base lead of the transistor, and the Voltage Divider bias circuit is: V TH = V CC Calculate RTH R2 R+R 1 2 We may apply KVL to the input, which gives us: -VTH + IB RTH + VBE + IE RE = 0 Since IE = (β + 1) IB RTH -V TH + I E + V BE + I E R E = 0 β + 1 Solving for I E we obtain I E = V TH - V BE RTH β R E : 23 February 2005 ENGI 242/ELEC Redrawing the input circuit for the network 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 3

4 Determining VTH V TH = V CC R2 R+R February 2005 ENGI 242/ELEC Determining RTH R TH = R 1R 2 R 1+ R 2 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 4

5 The Thévenin Equivalent Circuit Note that VE = VB VBE and IE = (β + 1)IB 23 February 2005 ENGI 242/ELEC Input Circuit Exact Analysis We may apply KVL to the input, which gives us: -VTH + IB RTH + VBE + IE RE = 0 Since IE = (β + 1) IB RTH -V TH + I E + V BE + I E R E = 0 β + 1 Solving for I E we obtain I E = V TH - V BE RTH β R E : 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 5

6 Collector-Emitter Loop 23 February 2005 ENGI 242/ELEC Collector-Emitter (Output) Loop Applying Kirchoff s voltage law: -VCC + IC RC + VCE + IE RE = 0 Assuming that IE IC and solving for VCE: I C = V CC - V CE R C+ R E Solve for VE: Solve for VC: VE = IE RE VC = VCC -IC RC or VC = VCE + IE RE Solve for VB: VB = VCC -IB RB or VB = VBE + IE RE 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 6

7 VCC = 22V R1 = 39kΩ R2 = 3.9kΩ RC = 10kΩ RE = 1.5kΩ β = 140 Voltage Divider Bias Example 1 23 February 2005 ENGI 242/ELEC VCC = 18V R1 = 39kΩ R2 = 8.2kΩ RC = 3.3kΩ RE = 1kΩ β = 120 Voltage Divider Bias Example 2 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 7

8 VCC = 16V R1 = 62kΩ R2 = 9.1kΩ RC = 3.9kΩ RE =.68kΩ β = 80 Voltage Divider Bias Example 3 23 February 2005 ENGI 242/ELEC Design of CE Amplifier with Voltage Divider Bias 1. Select a value for VCC 2. Determine the value of β from spec sheet or family of curves 3. Select a value for ICQ 4. Let VCE = ½ VCC (typical operation, 0.4 VCC VC 0.6 VCC ) 5. Let VE = 0.1 VCC (for good operation, 0.1 VCC VE 0.2 VCC ) 6. Calculate RE and RC 7. Let R2 0.1 β RE (for this calculation, use low value for β) 8. Calculate R1 V CC - V B R 1= R2 VB 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 8

9 CE Amplifier Design Design a Common Emitter Amplifier with Voltage Divider Bias for the following parameters: VCC = 24V IC = 5mA VE =.1VCC VC =.55VCC β = February 2005 ENGI 242/ELEC February 2005 ENGI 242/ELEC Voltage Divider Bias 9

10 CE Amplifier Design 23 February 2005 ENGI 242/ELEC CE Amplifier Design Voltage Divider Bias 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 10

11 Collector Feedback Bias ENGI 242 ELEC 222 BJT Biasing 4 For the Collector Feedback Bias Configuration: Draw Equivalent Input circuit Draw Equivalent Output circuit Write necessary KVL and KCL Equations Determine the Quiescent Operating Point Graphical Solution using Loadlines Computational Analysis Design and test design using a computer simulation 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 11

12 DC Bias with Collector (Voltage) Feedback Another way to improve the stability of a bias circuit is to add a feedback path from collector to base In this bias circuit the Q-point is only slightly dependent on the transistor β 23 February 2005 ENGI 242/ELEC Base Emitter Loop Solve for IB Applying Kirchoff s voltage law: -VCC + IC RC + IBRB + VBE + IERE = 0 Note: IC = IE = IC + IB Since IE = (β + 1) IB then: -VCC + (β + 1)IB RC + IBRB + VBE (β + 1)IBRE = 0 Simplifying and solving for I B : VCC - VBE I= B R+ B (β + 1) (R C + R E ) 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 12

13 Base Emitter Loop Solve for IE Applying Kirchoff s voltage law: -VCC + IERC + IBRB + VBE + IERE = 0 Since IE = (β + 1) IB then: RB -V CC + I E R C + I E + V BE + IER E = 0 ( β + 1) VCC - VBE Simplifying and solving for I E : I E = R B + (R C + R E ) (β + 1) 23 February 2005 ENGI 242/ELEC Collector Emitter Loop Applying Kirchoff s voltage law: IE RE + VCE + IC RC VCC = 0 Since IC =IE and IE = (β + 1) IB: IE(RC + RE) + VCE VCC =0 Solving for VCE: VCE = VCC IE (RE + RC) 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 13

14 Network Example 23 February 2005 ENGI 242/ELEC Network Example 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 14

15 Collector feedback with RE = 0Ω 23 February 2005 ENGI 242/ELEC Design of CE Amplifier with Collector Feedback Bias 1. Select a value for VCC 2. Determine the value of β from spec sheet or family of curves 3. Select a value for IEQ 4. Let VCE = ½ VCC (typical operation, 0.4 VCC VC 0.6 VCC ) 5. Let VE = 0.1 VCC (for good operation, 0.1 VCC VE 0.2 VCC ) 6. Calculate RE, RC and RB V E=.1V CC V - V V -.6V I I V - I R - V - I R I β + 1 CC CQ CC CC R C = = ; E E CC E C BE E E R B = ; E R E = R C = R B =.1V IE.4V I CC CC E V CC - I E (R C + R)- E 0.7 IE β + 1 V 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 15

16 Common Emitter Bias with Dual Supplies Voltage Divider Bias with Dual Power Supply 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 16

17 Voltage Divider Bias with Dual Power Supply Input Circuit Find VTH and RTH R 2 V TH1 = V CC R 1 + R 2 (Note V EE is negative) R 1 V TH2 = -V EE R + R V TH = V TH1 +V TH2 1 2 R 2 R 1 V TH = V CC - V EE R 1+ R 2 R 1+ R 2 R 1R 2 R TH = R 1 + R 2 23 February 2005 ENGI 242/ELEC Voltage Divider Bias with Dual Power Supply Output Circuit -V CC + ICR C + V CE + IER E - V EE = 0 If we assume I E I C (when β > 100) CC EE CE I C = R C+ RE If we use the exact solution I C = αi E I C = V + V - V V + V - V RE RC + α β where α = β + 1 CC EE CE 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 17

18 Voltage Divider Bias with Dual Power Supply 23 February 2005 ENGI 242/ELEC PSpice Simulation Voltage Divider Bias 18

19 PSpice Bias Point Simulation 23 February 2005 ENGI 242/ELEC PSpice Simulation for DC Bias 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 19

20 PSpice Simulation for DC Sweep 23 February 2005 ENGI 242/ELEC PSpice Simulation for DC Sweep The response of VC demonstrates rises rapidly towards the Q Point and then increases gradually towards a maximum value The response of VCE demonstrates that it reaches a peak value near the Q point and then decreases 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 20

21 PSpice Simulation for AC Sweep 23 February 2005 ENGI 242/ELEC PSpice Simulation for AC Sweep 23 February 2005 ENGI 242/ELEC Voltage Divider Bias 21