SBCCI 2010 Sessions Chip in Sampa

Transcription

1 SBCCI 2010 Sessions Chip in Sampa Mon. Sep. 6th 08:30 10:00 Tutorial 1: Low Power Design Host: Ricardo Reis (UFRGS, Brazil) Energy-Efficient Design of Digital Circuits Vojin G. Oklobdzija Center for Integrated Circuits and Systems University of Texas, USA Tutorial 2: Design Space Exploration Host: Guido Araujo (UNICAMP, Brazil) The Cross-Layer Multi-Dimensional Design Space of Power, Reliability, Temperature and Voltage in Highly Scaled Geometries Fadi J. Kurdahi Center for Embedded Computer Systems University of Califórnia at Irvine, USA Tutorial 3: Testing Host: Alex Orailoglu (UCSD, USA) Silicon Debug Using Data Mining Techniques of Delay Test Measurements Magdy S. Abadir Freescale Semiconductor, USA Tutorial 4: Logic Synthesis Host: Elmar Melcher (UFCG, Brazil) Logic Synthesis And Place & Route, New Links in a Long Standing Partnership Antun Domic Senior VP and General Manager, Implementation Group Synopsys Inc. Tue. Sep. 7th

2 Session 1: Low Power Design Chair: Ricardo Reis (UFRGS, Brazil) Invited Talk 1: Computing at the Ultimate Low-Energy Limits Vojin G. Oklobdzija Center for Integrated Circuits and Systems University of Texas, USA Performance Analysis of Dynamic Threshold MOS (DTMOS) based 4-input Multiplexer Switch for Low Power and High Speed FPGA Design Deepak Kumar, Pankaj Kumar and Manisha Pattanaik Reducing and Smoothing Power Consumption of ROM-based Controller Implementations Bertrand LE Gal and Lilian Bossuet Session 2: Analog and RF Circuits Chair: Wilhelmus Noije (USP, Brazil) A 5.4 GHz Fully-Integrated Low-Noise Mixer Stanley Ho and Carlos Saavedra Wideband Ring VCO for Cognitive Radio Five-Port Receiver Francisco de Assis Brito Filho and Fernando Rangel Sousa A High-Speed, Highly-Linear CMOS Fully Differerential Track-and-Hold Circuit Shaahin Haddadi Nejad, Ziaaddin Daei Kouzekanani, Jafar Sobhi, Iman Salami Fard and Kuresh Ghanbari A Precision Autozero Amplifier for EEG signals Guillermo Costa, Alfredo Arnaud and Matías Miguez Session 3: Analog and Mixed-Signal Design Chair: Fernando Rangel (UFSC, Brazil) A -60dB THD/100MHz True Unity-gain Voltage Buffer CMOS Circuit Andre L. Fortunato and Carlos A. dos Reis Filho Systematic Analysis & Optimization of Analog/Mixed-Signal Circuits Balancing Accuracy and Design time Antonio Colaci, Gianluigi Boarin, Andrea Roggero, Lorenzo Civardi, Carlo Roma, Gunter Strube, Andreas Ripp and Michael Pronath Design Methodology Using Inversion Coefficient for Low-Voltage Low-Power CMOS

3 Voltage Reference Dalton Colombo, Gilson Wirth and Christian Fayomi SwitchCraft - A Framework for Transistor Network Design Vinicius Callegaro, Felipe Souza Marques, Carlos Eduardo Klock, Leomar S. da Rosa Jr, Renato P. Ribas and André I. Reis Wed. Sep. 8th 8:30 10:00 Session 4: Testing Chair: Alex Orailoglu (UCSD, USA) Invited Talk 2: Design for Reality: Knowledge Discovery in Design and Test Data Magdy S. Abadir Freescale Semiconductor, USA Low-Power Test in Compression-Based Reconfigurable Scan Architectures Sobeeh Almukhaizim, Mohammad Mohammad and Mohammad Khajah Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors Andrea Calimera, Enrico Macii, Danilo Ravotto, Ernesto Sanchez and Matteo Sonza Reorda Session 5: Multiprocessor SoCs Chair: Edna Barros (UFPE, Brazil) Adaptive Multi-Threading for Dynamic Workloads in Embedded Multiprocessors Chenjie Yu and Peter Petrov Evaluating the Impact of Task Migration in Multi-Processor Systems-on-Chip Gabriel Marchesan Almeida, Sameer Varyani, Rémi Busseuil, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Everton Alceu Carara and Fernando Gehm Moraes Exploring Memory Organization in Virtual MP-SoC Platforms Ivan Saraiva Silva, Edgard de Faria Corrêa, Márcio Kreutz and Bruno Cruz de Oliveira Session 6: NoC Design and Evaluation Chair: Altamiro Susin (UFRGS, Brazil) Evaluation of a Hardware Transactional Memory Model in an NoC-based Embedded MPSoC

4 Leonardo Kunz, Gustavo Girão and Flávio Rech Wagner Implementation and Evaluation of a Congestion Aware Routing Algorithm for Networks-on-Chip Leonel Tedesco, Ney Calazans, Fabien Clermidy and Fernando Moraes The LRD Traffic Impact on the NoC-based SoCs Martha Johanna Sepulveda Florez, Ricardo Pires, Marius Strum and Wang Jiang Chau Session 7: Digital Design Chair: Flávio Wagner (UFRGS, Brazil) Zero Logic Overhead Integration of Partial Modules for Reconfigurable Instruction Set Extensions Dirk Koch, Christian Beckhoff and Jim Torresen On Evaluating the Signal Reliability of Self-checking Arithmetic Circuits Denis Franco, Maí Vasconcelos, Lirida Naviner and Jean-François Naviner A GALS Pipeline DES Architecture to Increase Robustness against DPA and DEMA Attacks Rafael Soares, Ney Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine and Lionel Torres An Efficient Implementation of Montgomery Powering Ladder in Reconfigurable Hardware Guilherme Perin, Daniel Mesquita, Fernando Luís Herrmann and João Batista Martins Thu. Sep. 9th 8:30 10:00 Session 8: Design Reliability Issues Chair: Guido Araujo (UNICAMP, Brazil) Invited Talk 3: Designing Working Systems with Imperfect Chips Fadi J. Kurdahi Center for Embedded Computer Systems University of California at Irvine, USA Modeling the Impact of RTS on the Reliability of Ring Oscillators Maurício Banaszeski da Silva and Gilson Inácio Wirth Evaluating the Effectiveness of a Mixed-Signal TMR Scheme Based on Design Diversity Gabriel de M. Borges, Luiz F. Gonçalves, Tiago R. Balen and Marcelo S. Lubaszewski

5 A Methodology to Improve the Yield in Analog Circuits by using Geometric Programming Jorge Johanny Sáenz, Elkim Roa, Armando Ayala Pabón and Wilhelmus Van Noije Session 9: Compressed Video Architectures Chair: Elmar Melcher (UFCG, Brazil) An MPEG-2 Transport Stream Demultiplexer IP Core compliant with SBTVD Leonardo Medeiros and Antonio Carlos Cavalcanti A High Performance Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Refinement Marcel Moscarelli Corrêa, Mateus Thurow Schoenknecht and Luciano Volcan Agostini Performance Enhancement of H.264/AVC Intra Frame Prediction Hardware Using Efficient 4-2 and 5-2 Adder-Compressors Cláudio Diniz, João Altermann, Eduardo Costa and Sergio Bampi A Novel Macroblock-level Filtering Upsampling Architecture for H.264/AVC Scalable Extension Thaísa Silva, Luís Cruz and Luciano Agostini Session 10: Image, Video and Signal Processing Chair: Antônio Cavalcanti (UFPB, Brazil) A 720p H.264/AVC Decoder ASIC Implementation for Digital Television Set-top Boxes Alexsandro Cristovão Bonatto, André Borin Soares, Adriano Renner, Leandro Max de Lima Silva, Sergio Bampi and Altamiro Amadeu Susin A Low Complexity Image Compression Solution for Onboard Space Applications Antonio Lopes Filho and Roberto d'amore Ordering and Partitioning of Coefficients Based on Heuristic Algorithms for Low Power FIR Filter Realization Angelo Luz, Eduardo Costa and Marilton Aguiar Variable Block Size Motion Estimation Architecture with Integrated Motion Compensation with Fast Bottom-Up Mode Decision for the H.264/AVC Video Coding Standard Robson Dornelles, Felipe Sampaio, Luciano Agostini and Sergio Bampi

6 Session 11: Algorithmic Advances in CAD Chair: Wang Jiang Chau (USP, Brazil) Improvements on the Detection of False Paths by using Unateness and Satisfiability Felipe S. Marques, Osvaldo Martinello Jr, Renato P. Ribas and André I. Reis A Modular CNF-based SAT Solver Bernardo Vieira, Fabrício Andrade and Antônio Otávio Fernandes CentroidM: A Centroid-based Localization Algorithm for Mobile Sensor Networks Leonardo Oliveira, Gustavo Dessbesell, João Baptista Martins and José Monteiro Implementation Comparisons of the QR decomposition for MIMO detection Gabriel Luca Nazar, Christina Gimmler and Norbert Wehn