Multi-Port Network Modeling of Multi-Layer Planar Circuits Containing Ground Plane Slots

Transcription

1 ulti-ort Network odelig of ulti-ayer laar Circuits Cotaiig Groud lae lots ARRZA KAJNAR, AFDDN AFA-NAN Deartet of lectrical ad Couter gieerig iversity of Waterloo 00 iversity Ave. West, Waterloo, Otario, N 3G CANADA Abstract: - A ew aroach for ulti-ort Network odelig (N of ulti-layer laar circuits cotaiig slots is itroduced. Geeralied etwork forulatio for aerture robles is cobied wi Okoshi s odel for laar circuits to obtai a uified circuit odel for two laar circuits couled rough a slot of arbitrary shae i eir coo groud lae. The eodology, which ca be easily geeralied to structures havig ore a two layers, is clarified by alyig e eod to a ulti-layer icrostri filter. Key-Words: - ulti-ort Network odelig, ulti-layer laar Circuits, urface quivalece Theore, Gree s Fuctio. troductio ulti-ort Network odelig (N of oeboudary laar circuits has bee successfully eloyed i aalysis ad desig of i laar structures. Wi soe iroveets, N eod has also bee alied to icrostri atch ateas ad arrays o i substrates []. egetatio ad desegetatio eods of aalysis, which are based o N, ake is aroach a very roisig ad aroriate eodology for couter-aided desig of laar icrowave circuits. As well, N for lectroagetically Couled (C icrostri atch ateas has bee develoed []. This alicatio of N eod is iortat because of e fact at C feed echais is essetially ree-diesioal. is aer, we will cobie N eod ad geeralied etwork forulatio for aerture robles [3] to eted alicability of is eodology to ulti-layer laar circuits. Forulatio We first cosider e roble of a icrostri atch o a slotted groud lae, as illustrated i Fig. ad Fig.. N for oe-boudary laar circuits, e erihery of e laar structure is divided u ito sufficiet uber of saller segets ad each seget is treated as a ort i low-frequecy circuits havig a terial voltage ad curret. The wid of each ort is take to be uch saller a e waveleg to ake sure at e curret

2 desity is alost costat over e wid of each ort ad cosequetly a ort curret ca be defied as e roduct of is curret desity ad e wid of e ort. ach ort has a self-iedace ad its utualiedace wi e oer orts accouts for iteractio betwee voltages ad currets of differet orts. The whole circuit is rereseted by a iedace atri, which relates orts voltages ad currets. We will ter ese orts as edge orts ad will use e subscrit to distiguish e fro slot orts, which will be defied later. The N for a oe-boudary laar circuit ca erefore be rereseted as: Z ( f e laar circuit is slot-couled to aoer laar circuit o e oer side of eir coo groud lae, ere will scattered fields fro e slot at will chage field atters i bo laar circuits. Therefore, N odels of bo laar circuits have to be odified to accout for e resece of e slot. This odificatio ust also ake it ossible to lik e N odels of e two laar circuits to each oer ad hece fid a uified etwork odel for e ulti-layer laar circuit. urface equivalece eore is used to relace e slot wi a equivalet surface agetic curret,. The directed electric field due to is agetic curret ca be writte as (. The iduced voltages at e edge orts will erefore be ( d(. o equatio ( ca be odified as follows: Z + ( ( where ( reresets e iduced voltages at edge orts. et us write equatio ( for oe of e edge ort, say edge ort. That is: N, Z, q,q +, ( (3 for,, N, where N is e uber of edge orts ad ( is e iduced voltage at e, edge ort due to. A siilar equatio ca be writte for e laar circuit below e groud lae. We will use subscrits ad to deote e laar circuits above ad below e coo groud lae, resectively. We will erefore have: N, Z, q,q +, ( (4- for,,,n ad N Z, q,q +, ( (4- for,,n. order to derive a iedace atri reresetatio for e two-layer circuit, (4- ad (4- have to be liked to each oer. This ca be accolished by eforcig electroagetic boudary coditios over e slot [3]. Cotiuity of e electric field is esured if. A set of basis fuctios ca be used to ead as follows: ( (5 where. Due to e liearity of e awell s equatios, we will have: N Z + ( ( (6-,, q,q, N, Z, q,q (, ( (6- atri forat, we will have: Z + T (7- Z T (7- T,,( (8- T,,( (8- Cotiuity of e agetic field ust be eforced. Though it is a coo ractice i i laar circuits to assue at oly T odes are ecited, i is case, where a slot is reset, full odal easio i ters of bo T ad T odes will be used to calculate tagetial agetic field cooets over e slot. These ca be writte as: N ( + ( ( (9-,q N (,q ( ( (9- f we use a set of vector testig fuctios rereseted by W ad defie e ier roduct of two vectors i e liear sace saed by s as [3]:

3 < A,B lot ( A B dv (0 quatios (9- ad (9- ca be discretied as follows: N <,W < (,q, W + ( N <,W < ( ( <,q <, W ( (, W, W (0- (0- for,,. f we defie slot currets as: ( <,W <, W ( Note at ( s are ot eier electric or agetic currets over e slot. As a atter of fact, it is ot ossible to treat slot orts i e sae way as edge orts. This is due to e fact at we assue a arbitrary shae for e slot ad cosequetly slot orts are ot ecessarily hysical orts. quatios (8- ad (8- i atri forat ca be writte as: T + Y (- T Y (- where < (,,W T, (3-, < (,,W T, (3-, Note at ere is o restrictio o e sie or shae of e slot. The oly restrictio is at e sae easio ad weightig fuctios should be used for bo of e laar circuits. quatios (7- ad (- rereset N for a laar circuit wi a slotted groud lae. Z + T (4- T + Y (4- Z is e iedace atri of e laar circuit wiout e slot i e groud lae. t ca be derived usig iedace Gree s fuctios for atches havig regular shaes. For irregular shaes, segetatio, desegetatio, or e Cotour-tegral eod [4] ca be used. T is e trasfer atri betwee e socalled slot orts ad edge orts voltages. As it ca be see fro (8-, i order to calculate T, we have to able to fid e cooet of e electric field ecited by each of e basis fuctios used to ead. a like aer, T is e trasfer atri betwee e so-called slot orts ad edge orts currets. As it ca be see fro (3-, calculatio of T ivolves fidig tagetial agetic field over e slot ecited by e edge orts currets. Y is e geeralied adittace atri of e slot ad accouts for iteractio betwee slot orts. t is iortat to use ree-diesioal field easio i is case. reality, bo T ad T are ecited wii e oe cavity. ice e ickess of e laar circuits is usually uch saller a e waveleg, electroagetic fields of a oe cavity, is aroiated by two-diesioal T odes. This is e coo ractice i N eod. Due to e resece of slot, e effect of T odes caot be igored i areas close to e slot. actual facts, electroagetic field distributio i ose areas will be oticeably differet fro what is redicted by solely T ode easio. areas far fro e slot, esecially at e edge orts, which are of our iterest, T odes will be doiatig ad it is ot ecessary to take e effect of T odes ito accout. Coutatio of Y requires easio of bo T ad T agetic field cooets ecited by s. sig is hybrid forulatio for laar circuits o bo sides of e groud lae, a uique iedace atri reresetatio for e ulti-layer laar structure ca be derived. 3 Rectagular atch wi Groud lae lot is sectio, e eod develoed i revious sectio will be alied to a rectagular atch o a slotted groud lae. The slot is assued to be a arrow rectagular slot orieted at θ wi resect to e ais (Fig. 3. The coordiates of e idoit of e slot are ad y, ad is e leg of e

4 slot. Z ca be readily evaluated usig iedace Gree s fuctio for rectagular atches [, 4]: jωµd δδφ(, y φ( q,yq Z, q ab 0 0 ( π / a + ( π / b k (5 For orts orieted alog e y ais : π πy w φ (,y cos( cos( si c( (6- a b b Ad for orts orieted alog e ais : π πy w φ (,y cos( cos( si c( (6- a b a We also have: 0 δ (7 0 k ω µε ε ( jtaδ (8 ( 0 r, y ad ( q, yq deote e locatios of e ad q orts, resectively. e case of T, we oly cosider whose oly cooets are,, ad T odes,. As a result, will oly have a cooet ad we will have d( ẑ. is e equivalet agetic curret desity used to relace e slot. ice e slots are usually very arrow, it ca be assued at e electric field i e slot has o cooet alog e leg of e slot (Fig.. o it is ossible to defie a corresodig slot voltage as w, where w is e wid of e slot. The equivalet agetic y curret source to relace e slot is give by ẑ. ad are e electric field ad voltage across e slot, resectively. For a agetic source i a cavity, electric field is eaded i ters of orooral ode vectors, i is case T ode vectors as follows [5]: jω dv (9 ω ω where ω is e resoace frequecy of e T ode. The terial voltage is defied as e averaged (,y over e wid of each ort. sig sub-doai basis fuctios for s, we will have: T F cosθ jωd q, q φ(,y 0 0 ω ω w ε ab (0 Fq (,(,y + taθ y,(,y ddy ( ad itegratio is erfored over e q slot ort. For a electric source i a cavity, agetic field easio i ters of orooral ode vectors, i is case T ode vectors, is as follows [5]: jω J dv ( ω ω sig e sae sub-doai basis fuctios for bo easio ad weightig fuctios, eleets of T ca be writte as: jω cosθ F δδ T, q φ ( q, yq 0 0 ω ω ε ab (3 As it was already etioed, full-wave reediesioal odal easio ust be used for Y : jω (, y,0 q(, y, 0 q dv ω ω (4 where bo T ad T odes eed to be cosidered. After soe legy but straightforward aeatics, e eleets of e geeralied adittace atri ca be rereseted as: δ δ

5 jωcos θ Rq R Gq G Y, q ω ω w (5 T Gq ( ˆ + taθŷ ( (,y,0 ddy (6- T Rq ( ˆ + taθŷ ( (,y,0 ddy (6- bo cases itegratio is erfored over e q slot ort. e coferece, we will reset soe results for ulti-layer laar structures usig e develoed N eod ad will coare e wi e results available fro coercial softwares. [5] R.F. arrigto, Tie-aroic lectroagetic Fields, Joh Wiley & os, Coclusios We have develoed a ew aroach for couteraided aalysis ad desig of ulti-layer laar circuits icludig groud lae slots. This aroach ca be cosidered as a geeraliatio of Okoshi s laar circuit odel. Wi recet advaces i ulti-layer circuit techology ad icreased iterest i ulti-layer icrowave circuits, we believe at is eod ca be effectively used for aalysis ad desig otiiatio uroses. Ackowledgeet This work was suorted by NRC (Natioal ciece ad gieerig Research Coucil of Caada ad Drago Wave c. (Ottawa, Caada. Refereces: [] J.R. Jaes, ad.. all, adbook of icrostri Ateas, lectroagetic Wave eries 8, 989. [] R.. arrikar, ad K.C. Guta, ultiort Network odel for CAD of lectroagetically Couled icrostri atch Ateas, Tras. Ateas roag., vol. A-46, o. 4, Aril 998, [3] R.F. arrigto, ad J.R. aut, A Geeralied Network Forulatio for Aerture robles, Tras. Ateas roag., vol. A-4, o. 6, Nov. 976, [4] T. Okoshi, laar Circuits for icrowave ad ightwaves, riger-erlag, 985.