Canon EOS 20D CMOS Image Sensor (704W) Process Review
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1 May 31, 2006 Canon EOS 20D CMOS Image Sensor (704W) Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:
2 Table of Contents Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Major Findings 2 Package and Die 2.1 Package and Device Architecture 2.2 Die 2.3 Die Features 3 Process Analysis 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 MOS Transistors and Polysilicon 3.7 Isolation 3.8 Wells 4 CMOS Pixel Array Analysis 4.1 Pixel Schematic 4.2 Pixel Array Plan-View Analysis 4.3 Pixel Array Cross-Sectional Analysis 5 Materials Analysis 5.1 TEM-EDS 5.2 Spreading Resistance Profiles 6 Critical Dimensions 6.1 Package and Die 6.2 Vertical Dimensions 6.3 Horizontal Dimensions Report Evaluation
3 Overview Overview 1.1 List of Figures 2 Device Overview Canon EOS 20D Camera Identification Markings on EOS 20D Camera Identification Markings on EOS 20D Camera Inside Canon EOS 20D Showing 704W CMOS Imager W CMOS Image Sensor Assembly Package and Ribbon Cable - Top View Package and Ribbon Cable Package - Top View Package - Bottom View Package X-Ray - Plan-View Package X-Ray - Side View Die with Organic Lenses and Color Filters Intact Pixel Array Corner Die with Lenses and Color Filters Removed Nitride Lenses Plan-View Die Corner a Die Corner b Die Corner c Die Corner d Minimum Pitch Bond Pads Single Bond Pad Single Bond Pad and Test Pattern Single Bond Pad and Test Pattern Test Pattern Die Photo Annotated with Analysis Regions 3 Process Analysis General Structure (Horizontal Section) Composite TEM Image of General Structure Die Edge (Vertical Section) Die Seal (Vertical Section) Bond Pad (Vertical Section) Bond Pad Edge Detail (Vertical Section) Bond Pad Edge Detail (Vertical Section)
4 Overview General Dielectric Structure Lens and Passivation Passivation ILD ILD PMD Pixel Anti-Reflection Coating PMD and Anti-Reflection Coating Detail TEM Image of Side Wall Spacer Detail Minimum Pitch Metal 3 (Vertical Section) Minimum Pitch Metal 2 (Vertical Section) TEM Image of Metal 2 TiN Cap TEM Image of Metal 2 TiN Barrier TEM Image of Metals 2 and Minimum Pitch Metal 1 (Horizontal Section) Metal 1 TiN Barrier Via 2 (Vertical Section) Via 1 (Horizontal Section) TEM Image of Via 1 Top Contact to Poly (Vertical Section) Contact to Substrate (Vertical Section) TEM Image of Contact Top TEM Image of Contact Bottom TEM Image of Contact Bottom Detail Peripheral NMOS NMOS Detail Peripheral PMOS PMOS Detail Minimum Pitch Poly TEM Image of MOS Transistor Gate Image of NMOS Pixel Transfer Transistor Gate TEM Image of SWS Detail TEM Image of Gate Oxide Minimum Width LOCOS Isolation (Horizontal Section) LOCOS Bird s Beaks (Horizontal Section) LOCOS Bird s Beak Detail (Horizontal Section) Peripheral Wells SCM Image of Pixel Array Well Structure
5 Overview CMOS Pixel Array Analysis Pixel Schematic Circuit Plan-View Image of Pixel Array Corner Plan-View Image of Pixel Array Corner Plan-View Image of Organic Lenses Plan-View Image of Organic and Nitride Lenses Pixel Array at Metal 3 Plan-View Pixel Array at Metal Pixel Array at Metal Pixel Array at Poly SCM Image of Pixel Array at Substrate Plan-View Image Showing Cross-Sectional Planes A-D Pixel Array General Structure (Horizontal Section A; Left Side) Pixel Array General Structure (Horizontal Section A; Right Side) Pixel Array General Structure with Red/Green Filters (Vertical Section B) Pixel Array General Structure with Blue/Green Filters (Vertical Section B) Lenses and Red/Green Filters (Vertical Section) Lenses and Blue/Green Filters (Vertical Section) Nitride Lenses (Horizontal Section) Edge of Nitride Lens Array (Horizontal Section) TEM Image of Nitride Lens Layers Embossed TEM Image of Nitride Lens Layers TEM Image of Nitride Lens Bottom Layer Pixel Structure Through Transfer Transistor (Horizontal Section A) SCM Image of Pixel Through Transfer Transistor (Horizontal Section A) T1/T2 Transfer Transistor TEM Image of T1/T Pixel Array General Structure (Horizontal Section C) T4 Source Follower and T5 Row Select Transistors (Horizontal Section C) TEM Image of T4 and T Pixel Array General Structure (Horizontal Section D) T3 Reset and V SS P-Well Contact (Horizontal Section D) T3 Reset Transistor TEM Image of T3
6 Overview Materials Analysis FESEM Image Showing TEM-EDS Analysis Points FESEM Image Showing TEM-EDS Analysis Points TEM-EDS Analysis of Lens Top Nitride TEM-EDS Analysis of Lens Top Nitride TEM-EDS Analysis of Passivation Oxide TEM-EDS Analysis of ILD 2 Oxide TEM-EDS Analysis of Metal 2 TiN Barrier TEM-EDS Analysis of ILD 1 Oxide TEM-EDS Analysis of PMD-2 PSG or BPSG TEM-EDS Analysis of PMD 1 Oxide TEM-EDS Analysis of Anti-Reflection Coat Oxide TEM-EDS Analysis of Anti-Reflection Coat Nitride TEM-EDS Analysis of LOCOS Oxide SRP Analysis of Peripheral N-Well SRP Analysis of Peripheral P-Well SRP Analysis of Pixel Array Wells 1.2 List of Tables Summary of Major Findings Package and Die Dimensions Dielectric Composition and Thicknesses Metallization Thicknesses Minimum Pitch Metals Via and Contact Dimensions Transistor and Polysilicon Horizontal Dimensions Transistor and Polysilicon Vertical Dimensions Isolation Horizontal Dimension Wells Verical Dimension Pixel Horizontal Dimensions Pixel Vertical Dimensions Transistor Dimensions in Pixel Array
7 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
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Figure 1 Wafer with Notch
Glass Wafer 2 SCHOTT is an international technology group with more than 125 years of experience in the areas of specialty glasses, materials and advanced technologies. With our high-quality products and
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ower MOS FET R07ZZ0007EJ0200 (revious: REJ27G0014-0100) Rev.2.00 Renesas has two types of ower MOS FETs, D Series (vertical structure) and S Series (lateral structure), as shown in Figure 1 and Figure