CSCE 350 Computer Architecture. Designing a Single Cycle Datapath. Adapted from the lecture notes of John Kubiatowicz(UCB) and Praveen

Transcription

1 CSCE 35 Computer Architecture Designing a Single Cycle Datapath Adapted from the lecture notes of John Kubiatowicz(UCB) and Praveen

2 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Memory Datapath Input Output Today s Topic: Design a Single Cycle Processor

3 The Big Picture: The Performance Perspective Performance of a machine is determined by: Instruction count Clock cycle time Clock cycles per instruction Inst. Count CPI Cycle Time Processor design (datapath and control) will determine: Clock cycle time Clock cycles per instruction Today: Single cycle processor: - Advantage: One clock cycle per instruction - Disadvantage: long cycle time

4 How to Design a Processor: step-by-step. Analyze instruction set => datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers - possibly more datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic

5 The MIPS Instruction Formats All MIPS instructions are bits long. The three instruction formats: R-type I-type J-type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits 3 26 op target address 6 bits 26 bits The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of the jump instruction

6 Step a: The MIPS-lite Subset for today ADD and SUB addu rd, rs, rt subu rd, rs, rt op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 6 OR Immediate: ori rt, rs, imm6 LOAD and STORE Word lw rt, rs, imm6 sw rt, rs, imm6 BRANCH: beq rs, rt, imm op rs rt immediate 6 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits 26 2 op rs rt immediate 6 bits 5 bits 5 bits 6 bits 6 6

7 Logical Register Transfers RTL gives the meaning of the instructions All start by fetching the instruction op rs rt rd shamt funct = MEM[ PC ] op rs rt Imm6 = MEM[ PC ] inst Register Transfers ADDU R[rd] < R[rs] + R[rt]; PC < PC + 4 SUBU R[rd] < R[rs] R[rt]; PC < PC + 4 ORi R[rt] < R[rs] zero_et(imm6); PC < PC + 4 LOAD R[rt] < MEM[ R[rs] + sign_et(imm6)]; PC < PC + 4 STORE MEM[ R[rs] + sign_et(imm6) ] < R[rt]; PC < PC + 4 BEQ if ( R[rs] == R[rt] ) then PC < PC sign_et(imm6)] else PC < PC + 4

8 Step : Requirements of the Instruction Set Memory instruction & data Registers ( ) read RS read RT Write RT or RD PC Etender Add and Sub register or etended immediate Add 4 or etended immediate to PC

9 Step 2: Components of the Datapath Combinational Elements Storage Elements Clocking methodology

10 Combinational Logic Elements (Basic Building Blocks) Adder A B Adder CarryIn Sum Carry MUX A B Select MUX Y OP ALU A B ALU Result

11 Storage Element: Register (Basic Building Block) Register Similar to the D Flip Flop ecept - N-bit input and output - Write Enable input Write Enable: - negated (): Data Out will not change - asserted (): Data Out will become Data In Write Enable Data In N Data Out N

12 Storage Element: Register File Register File consists of registers: Two -bit output busses: busa and busb One -bit input bus: busw Register is selected by: RA (number) selects the register to put on busa (data) RB (number) selects the register to put on busb (data) RW (number) selects the register to be written via busw (data) when Write Enable is Clock input (CLK) RW RA RB Write Enable busw -bit Registers The CLK input is a factor ONLY during write operation busa busb During read operation, behaves as a combinational logic block: - RA or RB valid => busa or busb valid after access time.

13 Storage Element: Idealized Memory Memory (idealized) One input bus: Data In One output bus: Data Out Memory word is selected by: Address selects the word to put on Data Out Write Enable = : address selects the memory word to be written via the Data In bus Clock input (CLK) Write Enable Address Data In DataOut The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: - Address valid => Data Out valid after access time.

14 Clocking Methodology Setup Hold Don t Care Setup Hold All storage elements are clocked by the same clock edge Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time

15 Step 3: Assemble Datapath meeting our requirements Register Transfer Requirements Datapath Assembly Instruction Fetch Read Operands and Eecute Operation

16 3a: Overview of the Instruction Fetch Unit The common RTL operations Fetch the Instruction: mem[pc] Update the program counter: - Sequential Code: PC <- PC Branch and Jump: PC <- something else PC Net Address Logic Address Instruction Memory Instruction Word

17 3b: Add & Subtract R[rd] <- R[rs] op R[rt] Eample: addu rd, rs, rt Ra, Rb, and Rw come from instruction s rs, rt, and rd fields ALUctr and RegWr: control logic after decoding the instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits busw Rd Rs RegWr Rw Ra Rb -bit Registers busa busb ALUctr ALU Result

18 Register-Register Timing: One complete cycle PC Rs,, Rd, Op, Func ALUctr Old Value -to-q New Value Old Value Old Value Instruction Memory Access Time New Value Delay through Control Logic New Value RegWr Old Value New Value Register File Access Time busa, B Old Value New Value ALU Delay busw Old Value New Value RegWr busw Rd Rs Rw Ra Rb -bit Registers busa busb ALUctr ALU Result Register Write Occurs Here

19 3c: Logical Operations with Immediate R[rt] <- R[rs] op ZeroEt[imm6] ] RegDst busw RegWr Rd imm6 3 Rs? Rw Ra Rb -bit Registers 6 26 busb ZeroEt busa 2 op rs rt immediate 6 bits 5 bits 5 bits rd? 6 bits bits 6 ALUSrc ALUctr ALU Result immediate 6 bits

20 3d: Load Operations R[rt] <- Mem[R[rs] + SignEt[imm6]] Eample: lw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits rd 6 bits RegDst busw Rd RegWr imm6 Rs Rw Ra Rb -bit Registers 6? busb Etender busa ALUctr ALU Data In?? ALUSrc MemWr WrEn Adr Data Memory W_Src Mu EtOp

21 3e: Store Operations Mem[ R[rs] + SignEt[imm6] <- R[rt] ] Eample: sw rt, rs, imm6 RegDst busw 3 RegWr op rs rt immediate 6 bits 5 bits 5 bits 6 bits Rd ALUctr MemWr imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 busb Etender busa Data In ALU WrEn Adr Data Memory W_Src Mu EtOp ALUSrc

22 3f: The Branch Instruction op rs rt immediate 6 bits 5 bits 5 bits 6 bits 6 beq rs, rt, imm6 mem[pc] Fetch the instruction from memory Equal <- R[rs] == R[rt] Calculate the branch condition if (Equal) Calculate the net instruction s address - PC <- PC ( SignEt(imm6) 4 ) else - PC <- PC + 4

23 Equal? Datapath for Branch Operations beq rs, rt, imm6 Datapath generates condition (equal) op rs rt immediate 6 bits 5 bits 5 bits 6 bits Inst Address Cond 4 imm6 PC Et npc_sel Adder Adder PC busw RegWr Rs Rw Ra Rb -bit Registers busa busb

24 imm6 Putting it All Together: A Single Cycle Datapath Inst Memory Adr Rs <2:25> <:5> <:5> <6:2> Rd Imm6 Instruction<3:> npc_sel RegDst Rd Equal ALUctr MemWr MemtoReg 4 PC Et Adder Adder PC RegWr busw imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 busa busb Etender = ALU WrEn Adr Data In Data Memory EtOp ALUSrc

25 Net Address PC An Abstract View of the Critical Path Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: - Address valid => Output valid after access time. Ideal Instruction Memory Instruction Address Rd 5 Instruction Rs 5 5 Rw Ra Rb -bit Registers Imm 6 A B Critical Path (Load Operation) = PC s -to-q + Instruction Memory s Access Time + Register File s Access Time + ALU to Perform a -bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew ALU Data Address Data In Ideal Data Memory

26 Net Address PC An Abstract View of the Implementation Ideal Instruction Memory Instruction Address Rd 5 Instruction Rs 5 5 Rw Ra Rb -bit Registers A B Control Control Signals ALU Conditions Data Address Data In Ideal Data Memory Data Out Datapath

27 Recap: A Single Cycle Datapath Rs,, Rd and Imed6 hardwired into datapath from Fetch Unit We have everything ecept control signals (underline) Today s lecture will show you how to generate the control signals RegDst busw RegWr Rd imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 npc_sel busb Etender busa EtOp ALUSrc Instruction Fetch Unit ALUctr Data In ALU Instruction<3:> Zero <2:25> WrEn Rs <6:2> MemWr Adr Data Memory Rd <:5> <:5> Imm6 MemtoReg

28 imm6 Recap: Meaning of the Control Signals npc_mux_sel: PC < PC + 4 PC < PC SignEt(Im6) Later in lecture: higher-level connection between mu and branch cond npc_mux_sel 4 Adr Inst Memory PC Et Adder Adder PC

29 Recap: Meaning of the Control Signals EtOp: zero, sign ALUsrc: regb; immed ALUctr: add, sub, or RegDst RegWr busw imm6 Rd 5 5 Rs 5 Rw Ra Rb -bit Registers 6 busa busb Etender Equal MemWr: write memory MemtoReg: ALU; Mem RegDst: rt ; rd RegWr: write register ALUctr = ALU MemWr WrEn Adr Data In Data Memory MemtoReg EtOp ALUSrc

30 RTL: The Add Instruction op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The actual operation PC <- PC + 4 Calculate the net instruction s address

31 imm6 Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction <- mem[pc] This is the same for all instructions Inst Memory Adr Instruction<3:> npc_mux_sel 4 PC Et Adder Adder PC

32 The Single Cycle Datapath during Add op rs rt rd shamt funct R[rd] <- R[rs] + R[rt] RegDst = RegWr = busw Rd imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 busb Etender EtOp = npc_sel= +4 busa ALUctr = Add Data In ALUSrc = Instruction Fetch Unit ALU Zero Instruction<3:> <2:25> WrEn Rs <6:2> MemtoReg = MemWr = Adr Data Memory Rd <:5> <:5> Imm6

33 imm6 Instruction Fetch Unit at the End of Add PC <- PC + 4 This is the same for all instructions ecept: Branch and Jump Inst Memory Adr Instruction<3:> npc_mux_sel 4 Adder Adder PC

34 The Single Cycle Datapath during Or Immediate op rs rt immediate R[rt] <- R[rs] or ZeroEt[Imm6] RegDst = RegWr = busw Rd imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 npc_sel = busb Etender busa EtOp = 6 ALUctr = ALUSrc = Instruction Fetch Unit Data In ALU Zero Instruction<3:> <2:25> WrEn Rs <6:2> MemWr = Adr Data Memory Rd <:5> <:5> Imm6 MemtoReg =

35 The Single Cycle Datapath during Load op rs rt immediate R[rt] <- Data Memory {R[rs] + SignEt[imm6]} RegDst = RegWr = busw Rd imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 busb Etender EtOp = npc_sel= +4 busa ALUctr = Add ALUSrc = Instruction Fetch Unit Data In ALU Zero Instruction<3:> <2:25> WrEn Rs <6:2> MemWr = Adr Data Memory Rd <:5> Imm6 MemtoReg = <:5>

36 The Single Cycle Datapath during Store op rs rt immediate Data Memory {R[rs] + SignEt[imm6]} <- R[rt] RegDst = RegWr = busw Rd imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 npc_sel = busb Etender busa EtOp = ALUctr = ALUSrc = Instruction Fetch Unit Data In ALU Zero Instruction<3:> <2:25> WrEn Rs <6:2> MemWr = Adr Data Memory Rd <:5> <:5> Imm6 MemtoReg =

37 The Single Cycle Datapath during Store op rs rt immediate Data Memory {R[rs] + SignEt[imm6]} <- R[rt] RegDst = RegWr = busw Rd imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 busb Etender EtOp = npc_sel= +4 busa ALUctr = Add Data In ALUSrc = Instruction Fetch Unit ALU Zero Instruction<3:> <2:25> WrEn Rs <6:2> MemtoReg = MemWr = Adr Data Memory Rd <:5> <:5> Imm6

38 The Single Cycle Datapath during Branch op rs rt immediate if (R[rs] - R[rt] == ) then Zero <- ; else Zero <- RegDst = RegWr = busw Rd imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 npc_sel= Br busb Etender EtOp = busa ALUctr =Sub ALUSrc = Instruction Fetch Unit Data In ALU Zero Instruction<3:> <2:25> WrEn Rs <6:2> MemWr = Adr Data Memory Rd <:5> <:5> Imm6 MemtoReg =

39 imm6 Instruction Fetch Unit at the End of Branch op rs rt immediate 6 if (Zero == ) then PC = PC SignEt[imm6]*4 ; else PC = PC + 4 npc_sel Inst Memory Adr Instruction<3:> Zero npc_mux_sel What is encoding of npc_sel? Direct MUX select? Branch / not branch 4 Adder Adder PC Let s choose second option npc_sel zero? MUX

40 Step 4: Given Datapath: RTL -> Control Instruction<3:> Inst Memory Adr Op <2:25> Fun <2:25> <:5> <:5> <6:2> Rs Rd Imm6 Control npc_sel RegWr RegDst EtOp ALUSrc ALUctr MemWr MemtoReg Zero DATA PATH

41 A Summary of Control Signals inst Register Transfer ADD R[rd] < R[rs] + R[rt]; PC < PC + 4 ALUsrc = RegB, ALUctr = add, RegDst = rd, RegWr, npc_sel = +4 SUB R[rd] < R[rs] R[rt]; PC < PC + 4 ALUsrc = RegB, ALUctr = sub, RegDst = rd, RegWr, npc_sel = +4 ORi R[rt] < R[rs] + zero_et(imm6); PC < PC + 4 ALUsrc = Im, Etop = Z, ALUctr = or, RegDst = rt, RegWr, npc_sel = +4 LOAD R[rt] < MEM[ R[rs] + sign_et(imm6)]; PC < PC + 4 ALUsrc = Im, Etop = Sn, ALUctr = add, MemtoReg, RegDst = rt, RegWr, npc_sel = +4 STORE MEM[ R[rs] + sign_et(imm6)] < R[rs]; PC < PC + 4 ALUsrc = Im, Etop = Sn, ALUctr = add, MemWr, npc_sel = +4 BEQ if ( R[rs] == R[rt] ) then PC < PC + sign_et(imm6)] else PC < PC + 4 npc_sel = Br, ALUctr = sub

42 A Summary of the Control Signals See func We Don t Care :-) Appendi A op add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite npcsel Jump EtOp ALUctr<2:> Add Subtract Or Add Add Subtract R-type op rs rt rd shamt funct add, sub I-type op rs rt immediate ori, lw, sw, beq J-type op target address jump

43 The Concept of Local Decoding op R-type ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump EtOp ALUop<N:> R-type Or Add Add Subtract op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3 ALU

44 The Encoding of ALUop op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3 In this eercise, ALUop has to be 2 bits wide to represent: () R-type instructions I-type instructions that require the ALU to perform: - (2) Or, (3) Add, and (4) Subtract To implement the full MIPS ISA, ALUop has to be 3 bits to represent: () R-type instructions I-type instructions that require the ALU to perform: - (2) Or, (3) Add, (4) Subtract, and (5) And (Eample: andi) R-type ori lw sw beq jump ALUop (Symbolic) R-type Or Add Add Subtract ALUop<2:>

45 The Decoding of the func Field op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3 R-type ori lw sw beq jump ALUop (Symbolic) R-type Or Add Add Subtract ALUop<2:> R-type op rs rt rd shamt funct P. 286 tet: funct<5:> Instruction Operation add subtract and or set-on-less-than ALUctr ALU ALUctr<2:> ALU Operation And Or Add Subtract Set-on-less-than

46 The Truth Table for ALUctr ALUop R-type ori lw sw beq (Symbolic) R-type Or Add Add Subtract ALUop<2:> funct<3:> Instruction Op. add subtract and or set-on-less-than ALUop bit<2> bit<> bit<> bit<3> func bit<2> bit<> bit<> ALU Operation ALUctr bit<2> bit<> bit<> Add Subtract Or Add Subtract And Or Set on <

47 The Logic Equation for ALUctr<2> ALUop func bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ALUctr<2> ALUctr<2> =!ALUop<2> & ALUop<> + This makes func<3> a don t care ALUop<2> &!func<2> & func<> &!func<>

48 The Logic Equation for ALUctr<> ALUop func bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ALUctr<> ALUctr<> =!ALUop<2> &!ALUop<> +! ALUop<2> ALUop<> ALUop<> + ALUop<2> &!func<2> &!func<>

49 The Logic Equation for ALUctr<> ALUop func bit<2> bit<> bit<> bit<3> bit<2> bit<> bit<> ALUctr<> ALUctr<> =!ALUop<2> & ALUop<> + ALUop<2> &!func<3> & func<2> &!func<> & func<> + ALUop<2> & func<3> &!func<2> & func<> &!func<>

50 The ALU Control Block func 6 ALUop 3 ALU Control (Local) ALUctr 3 ALUctr<2> =!ALUop<2> & ALUop<> + ALUop<2> &!func<2> & func<> &!func<> ALUctr<> =!ALUop<2> &!ALUop<> + ALUop<2> &!func<2> &!func<> ALUctr<> =!ALUop<2> & ALUop<> + ALUop<2> &!func<3> & func<2> &!func<> & func<> + ALUop<2> & func<3> &!func<2> & func<> &!func<>

51 Step 5: Logic for each control signal npc_sel <= (OP == `BEQ)? `Br : `plus4; ALUsrc <= (OP == `ype)? `regb : `immed; ALUctr <= (OP == `ype`)? funct : (OP == `ORi)? `ORfunction : (OP == `BEQ)? `SUBfunction : `ADDfunction; EtOp <= MemWr <= MemtoReg <= RegWr: <= RegDst: <=

52 Step 5: Logic for each control signal npc_sel <= (OP == `BEQ)? `Br : `plus4; ALUsrc <= (OP == `ype)? `regb : `immed; ALUctr <= (OP == `ype`)? funct : (OP == `ORi)? `ORfunction : (OP == `BEQ)? `SUBfunction : `ADDfunction; EtOp <= (OP == `ORi) : `ZEROetend : `SIGNetend; MemWr <= (OP == `Store)? : ; MemtoReg <= (OP == `Load)? : ; RegWr: <= ((OP == `Store) (OP == `BEQ))? : ; RegDst: <= ((OP == `Load) (OP == `ORi))? : ;

53 The Truth Table for the Main Control op 6 Main Control RegDst ALUSrc : ALUop 3 func 6 ALU Control (Local) ALUctr 3 op R-type ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite npc_sel Jump EtOp ALUop (Symbolic) R-type Or Add Add Subtract ALUop <2> ALUop <> ALUop <>

54 The Truth Table for RegWrite op R-type ori lw sw beq jump RegWrite RegWrite = R-type + ori + lw =!op<5> &!op<4> &!op<3> &!op<2> &!op<> &!op<> (R-type) +!op<5> &!op<4> & op<3> & op<2> &!op<> & op<> (ori) + op<5> &!op<4> &!op<3> &!op<2> & op<> & op<> (lw) op<5>. op<5> op<5>.. op<5>.. op<5>.. op<5>..... <> <> <> <> <> op<> R-type ori lw sw beq jump RegWrite

55 PLA Implementation of the Main Control op<5>. op<5> op<5>.. op<5>.. op<5>.. op<5>..... <> <> <> <> <> op<> R-type ori lw sw beq jump RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump EtOp ALUop<2> ALUop<> ALUop<>

56 op 6 Instr<3:26> RegDst Putting it All Together: A Single Cycle Processor busw Main Control RegWr Rd imm6 Instr<5:> 5 5 Rs 5 Rw Ra Rb -bit Registers 6 ALUop RegDst ALUSrc : busb Etender busa EtOp 3 npc_sel ALUSrc Instruction Fetch Unit ALUctr func Instr<5:> 6 Data In ALU Zero Instruction<3:> ALU Control <2:25> WrEn Rs <6:2> MemWr Adr Data Memory ALUctr Rd <:5> 3 <:5> Imm6 MemtoReg

57 Net Address PC Recap: An Abstract View of the Critical Path (Load) Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: - Address valid => Output valid after access time. Ideal Instruction Memory Instruction Address Rd 5 Instruction Rs 5 5 Rw Ra Rb -bit Registers Imm 6 A B Critical Path (Load Operation) = PC s -to-q + Instruction Memory s Access Time + Register File s Access Time + ALU to Perform a -bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew ALU Data Address Data In Ideal Data Memory

58 Worst Case Timing (Load) PC Rs,, Rd, Op, Func ALUctr Old Value -to-q New Value Old Value Old Value Instruction Memory Access Time New Value Delay through Control Logic New Value EtOp Old Value New Value ALUSrc Old Value New Value MemtoReg Old Value New Value RegWr Old Value New Value busa busb Old Value Delay through Etender & Old Value Register Write Occurs Register File Access Time New Value New Value ALU Delay Address Old Value New Value Data Memory Access Time busw Old Value New

59 Drawback of this Single Cycle Processor Long cycle time: Cycle time must be long enough for the load instruction: PC s Clock -to-q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew Cycle time for load is much longer than needed for all other instructions

60 Preview Net Time: MultiCycle Data Path CPI, CycleTime much shorter (~/5 of time)

61 Summary Single cycle datapath => CPI=, CCT => long 5 steps to design a processor. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Control is the hard part MIPS makes control easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Processor Control Datapath Memory Input Output