Where we are CS 4120 Introduction to Compilers Abstract Assembly Instruction selection mov e1 , e2 jmp e cmp e1 , e2 [jne je jgt ] l push e1 call e

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1 0/5/03 Where we are CS 0 Introduction to Compilers Ross Tate Cornell University Lecture 8: Instruction Selection Intermediate code synta-directed translation reordering with traces Canonical intermediate code Abstract assembly code tiling dynamic programming register allocation Assembly code Abstract Assembly Abstract assembly = assembly code w/ infinite register set Canonical intermediate code = abstract assembly code epression trees (e, e ) mov e, e JUMP(e) jmp e (e,l) cmp e, e [jne je jgt ] l CALL(e, e, ) push e; ; call e LABEL(l ) l: Instruction selection Conversion to abstract assembly is problem of instruction selection for a single IR statement node Full abstract assembly code: glue translated instructions from each of the statements Problem: more than one way to translate a given statement. How to choose? 3 Eample 86-6 ISA TEMP(t) TEMP(t) TEMP(fp)? mov %rbp, add $, mov (),t3 add t3, t add (%rbp),t Need to map IR tree to actual machine instructions need to know how instructions work A two-address CISC architecture (inherited from 00, 8008, 8086 ) Typical instruction has opcode (mov, add, sub, shl, shr, mul, div, jmp, jcc, push, pop, test, enter, leave) destination (r,n,(r),k(r),(r,r), (r,r,w),k(r,r,w) ) (may also be an operand) source (any legal destination, or a constant $k) opcode src src/dest mov $,%ra add %rc,%rbz sub %rbp,%esi add %edi, (%rc,%edi,6) je label jmp (%rbp) 5 6

intermediate code = abstract assembly code epression trees (e, e ) mov e, e JUMP(e) jmp e (e,l) cmp e, e [jne je jgt ] l CALL(e, e, ) push e; ; call e LABEL(l ) l: Instruction selection Conversion to

2 0/5/03 AT&T vs Intel Tiling Intel synta: opcode dest, src Registers ra, rb, rc,...r8,r9,...r5 constants k memory operands [n], [rk], [rw*r],... AT&T synta (GNU assembler default): opcode src, dest %ra, %rb, constants $k memory operands n, k(r), (r,r,w),... Idea: each Pentium instruction performs computation for a piece of the IR tree: a tile mov %rbp, add $, mov (),t3 TEMP(t) t3 add t3, t TEMP(t) TEMP(fp) Tiles connected by new temporary registers (, t3) that hold result of tile 7 8 t Tiles mov t, add $, Some tiles TEMP(t) t mov t,t Tiles capture compiler s understanding of instruction set Each tile: sequence of instructions that update a fresh temporary (may need etra mov s) and associated IR tree All outgoing edges are temporaries t t t t CONST(i) mov t, add t, mov $i,(t,t ) 9 0 Designing tiles Only add tiles that are useful to compiler Many instructions will be too hard to use effectively or will offer no advantage Need tiles for all single-node trees to guarantee that every tree can be tiled, e.g. t mov t, add t, t3 t3 More handy tiles lea instruction computes a memory address but doesn t actually load from memory t t lea (t,t ), lea (t,t,k ), t t * f CONST(k ) t (k one of,,8,6)

.. Idea: each Pentium instruction performs computation for a piece of the IR tree: a tile mov %rbp, add $, mov (),t3 TEMP(t) t3 add t3, t TEMP(t) TEMP(fp) Tiles connected by new temporary registers

3 0/5/03 Matching for RISC As defined in lecture, have (cond, destination) Appel: (op, e, e, destination) where op is one of ==,!=, <, <=, =>, > Our translates easily to RISC ISAs that have eplicit comparison result t < t3 NAME(n) cmplt, t3, t br MIPS t, n Condition code ISA Appel s corresponds more directly to Pentium conditional jumps set condition codes < NAME(n) t cmp t, jl n test condition codes However, can handle Pentium-style jumps with lecture IR with appropriate tiles 3 Branches An annoying instruction How to tile a conditional jump? Fold comparison operator into tile t EQ l (l) l (l) test t jnz l cmp t, t je l Pentium mul instruction multiples single operand by ea, puts result in ea (low 3 bits), ed (high 3 bits) Solution: add etra mov instructions, let register allocation deal with ed overwrite MUL t t mov t, %ea mul mov %ea, t t 5 6 Tiling Problem Eample How to pick tiles that cover IR statement tree with minimum eecution time? Need a good selection of tiles small tiles to make sure we can tile every tree large tiles for efficiency Usually want to pick large tiles: fewer instructions instructions cycles: RISC core instructions take cycle, other instructions may take more add %ra,(%rc) mov (%rc),%rd add %rd,%ra mov %ra,(%rc) = ; t ebp: Pentium frame-pointer register mov (%ebp,), t mov t, add $, mov, (%ebp,) 7 8 3

conditional jumps set condition codes < NAME(n) t cmp t, jl n test condition codes However, can handle Pentium-style jumps with lecture IR with appropriate tiles 3 Branches An annoying instruction

4 0/5/03 Alternate (non-risc) tiling Greedy tiling = ; add $, (ebp,) r/m3 r/m3 CONST(k) 9 Assume larger tiles = better Greedy algorithm: starrom top of tree and use largest tile that matches tree Tile remaining subtrees recursively 8 MUL 0 Improving instruction selection Greedy tiling may not generate best code Always selects largest tile, not necessarily fastest instruction May pull nodes up into tiles when better to leave below Can do better using dynamic programming algorithm Timing model Idea: associate cost with each tile (proportional to # cycles to eecute) caveat: cost is fictional on modern architectures Estimate of total eecution time is sum of costs of all tiles Total cost: 5 Finding optimum tiling Goal: find minimum total cost tiling of tree Algorithm: for every node, find minimum total-cost tiling of that node and sub-tree. Lemma: once minimum-cost tiling of all children of a node is known, can find minimum-cost tiling of the node by trying out all possible tiles matching the node Therefore: starrom leaves, work upward to top node Recursive implementation Any dynamic-programming algorithm equivalent to a memoized version of same algorithm that runs top-down For each node, record best tile for node Start at top, recurse: First, check in table for best tile for this node If not computed, try each matching tile to see which one has lowest cost Store lowest-cost tile in table and return Finally, use entries in table to emit code 3

tiles when better to leave below Can do better using dynamic programming algorithm Timing model Idea: associate cost with each tile (proportional to # cycles to eecute) caveat: cost is fictional on

5 0/5/03 Problems with model Modern processors: eecution time not sum of tile times instruction order matters Processors are pipelining instructions and eecuting different pieces of instructions in parallel bad ordering (e.g. too many memory operations in sequence) stalls processor pipeline processor can eecute some instructions in parallel (super-scalar) cost is merely an approimation instruction scheduling needed Finding matching tiles Eplicitly building every tile: tedious Easier to write subroutines for matching Pentium source, destination operands Reuse matcher for all opcodes 5 6 Matching tiles Tile Specifications abstract class IR_Stmt { Assembly munch(); class IR_Move etends IR_Stmt { IR_Epr src, dst; Assembly munch() { if (src instanceof IR_Plus && ((IR_Plus)src).lhs.equals(dst) && is_regmem3(dst) { Assembly e = (IR_Plus)src).rhs.munch(); return e.append(new AddIns(dst, e.target())); r/m3 else if... Previous approach simple, efficient, but hard-codes tiles and their priorities Another option: eplicitly create data structures representing each tile in instruction set Tiling performed by a generic tree-matching and code generation procedure Can generate from instruction set description generic back end! For RISC instruction sets, over-engineering 7 8 Summary Can specify code-generation process as a set of tiles that relate IR trees to instruction sequences Instructions using fied registers problematic but can be handled using etra temporaries Greedy algorithm implemented simply as recursive traversal Dynamic-programming algorithm generates better code, can also be implemented recursively using memoization Real optimization will require instruction scheduling 9 5

(e.g. too many memory operations in sequence) stalls processor pipeline processor can eecute some instructions in parallel (super-scalar) cost is merely an approimation instruction scheduling needed

Administration. Instruction scheduling. Modern processors. Examples. Simplified architecture model. CS 412 Introduction to Compilers

Administration. Instruction scheduling. Modern processors. Examples. Simplified architecture model. CS 412 Introduction to Compilers CS 4 Introduction to Compilers ndrew Myers Cornell University dministration Prelim tomorrow evening No class Wednesday P due in days Optional reading: Muchnick 7 Lecture : Instruction scheduling pr 0 Modern