2.5 & 3D ENABLING TECHNOLOGIES SELECTION BASED ON COO & TECHNOLOGY MATURITY TRADEOFF ANALYSIS ERIC BEYNE

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1 2.5 & 3D ENABLING TECHNOLOGIES SELECTION BASED ON COO & TECHNOLOGY MATURITY TRADEOFF ANALYSIS ERIC BEYNE European 3D Summit January 22-23, 2013 Grenoble

2 OUTLINE 3D Technology Convergence scaling: Technology Directions Scaling: Cost of Ownership analysis Scaling Roadmap ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/2013 2

3 3D TECHNOLOGY READINESS FROM CONFUSION TO CONVERGENCE From: Large variety of applications To: Clear high volume application drivers Large number different technology directions Technology convergence Technology Wafer thinning & Thin wafer processing Chip/wafer stacking & stack packaging Unclear supply chain IC foundry WLP - SAT PCB assembly Improved definition roles front-end; mid-end; back-end Still evolving ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/2013 3

4 3D TECHNOLOGY PROCESS MODULES Front-end FEOL process Via middle BEOL process Mid-end Wafer to carrier Bonding/ Debonding & Wafer thinning Backside reveal & backside passivation Semi-additive RDL, µbump & Cu pillar processes Back-end 3D Stacking (D2D; D2W) ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/2013 4

5 Si wafer FEOL device layer BEOL interconnect wiring intermediate global local FRONT-SIDE APPROACHES Via-first : fabrication of s before FEOL device fabrication (FEOL, Front-End-Of-Line) (BEOL, Back-End-Of-Line) "Via-middle": fabrication s after FEOL device fabrication processing but before BEOL interconnect. "Via-mid BEOL": fabrication s after local BEOL interconnect, before top BEOL interconnect. "Via-last": fabrication of s after BEOL interconnect. ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/2013 5

6 VIA MIDDLE THROUGH-SI-VIA PROCESS "Via-middle": fabrication s after FEOL device fabrication processing but before BEOL interconnect. Si Si Key features : Cu-nail process after FEOL, before of BEOL processing High aspect ratio Cu damascene technique Single litho-step imec POR process: o 5 µm diameter; o 50 µm deep; o Aspect ratio 10 ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/2013 6

7 3D-SIC 5µm, 50µm deep on 300mm Via etch Requirements: No undercut below PMD/STI layer low side-wall roughness: reduce scalloping Precise depth-control: < 1µm WiW variation Accurate etch: Improves liner quality and reliability; Reduces required depth; Allows for CMP-less thin wafer backside process cost reduction ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/2013 7

8 3D-SIC 5µm, 50µm deep on 300mm Via etch Oxide Liner Top PVD Ta Cu barrier Liner PMD STI Si PVD Cu seed anneal & CMP Middle Cu ECD fill Bottom Accurate Within wafer depth Control Conformal Smooth surface Low capacitance Effective barriers: prevent Cu diffusion Void-free bottomup -fill dishing 5µm Anneal to mitigate Cu pumping Limited CMP ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/2013 8

9 CHALLENGES INTEGRATING VIA-MIDDLE IN ADVANCED TECHNOLOGY NODES Vertical scaling 14 nm CMOS Strong scaling of the STI/PMD layer thicknesses: PMD erosion during CMP? Integration with thin ELK dielectric layers on top of Cu? Si Cu ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/2013 9

10 THINNING WAFERS & VIA-REVEAL PROCESS Clear convergence From a large variety of temporary carrier approaches: Laser debond Solvent debond Thermal debond Slide debond Peel debond To a clear preference for a room-temperature; peel debondable carrier systems As a result more equipment and material suppliers are engaging in this technology Leading to cost reduction and performance improvement ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

11 Si Thickness (µm) WAFER THINNING (50µm) AND BACKSIDE PASSIVATION AND CU-NAIL EXPOSURE < 2 µm TTV Radial position on wafer (mm) Cu liner Backside Passivation ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

12 ROOM-TEMPERATURE PEEL DEBONDING Demonstrated full sequence of wafer bonding/ thinning/ backside processing, wafer taping, debonding and cleaning on tape of active CMOS wafers Anne Jourdain ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

13 OUTLINE 3D Technology Convergence scaling: Technology Directions Scaling: Cost of Ownership analysis Scaling Roadmap ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

14 SCALING DIRECTIONS Diameter For capacitance reduction For reduced impact of Cu stress on devices For PVD barrier seed deposition For low resistance (PWR/GND) (or multiple smaller ) Si thickness For capacitance reduction For PVD barrier/seed deposition For process time reduction: etch& plating For hot spot thermal performance For easy die handling Higher aspect ratio ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

15 Relative Stress level KOZ scaling REDUCTION KEEP-OUT-ZONE AROUND BY DIAMETER SCALING 2.0 The KOZ is defined by a maximum induced stress level The KOZ area scales with (Ø 1 /Ø 2 ) 2 : e.g. (5 µm/3µm) 2 = Area -64% ~ (Ø /r) 2 ~ (Ø 1 /Ø 2 ) Distance from center, r (µm) Circum. Stress 5 µm Ø Circum. Stress 3 µm Ø ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

16 ASPECT RATIO DEPENDENT Φ = 1µm 2µm 3µm 4µm 5µm 7µm 10µm 20µm ETCHING AR= POR LAM 2300 Syndion ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

17 APPLICATION: ARDE PROCESS WINDOW Interposer : Etch time approximately etch time x2 for 10x100 Scaled : 3 µm : more cost effective than 2 µm diameter CONFIDENTIAL ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

18 Heat flow direction Die 3 Die 2 Die 1 THERMAL PROPERTIES OF A 3D STACK HOT-SPOT HEAT SPREADING E.g. 3-Die stack: hot spot heating in center die Q cooling Die 3 Die 2 Die 1 Radial, cylindrical, heat spreading in the thin 3D stacked die; T-drop across interface layers (BEOL & interface layers); (K/W) ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

19 Normalized Temperature (K/W) Peak temperature Hot Spot (ºC/W) THERMAL IMPACT OF INTERFACE LAYER Comparison Thermal Measurements and FEM Simulations: 25µm thick stacked die using CuSn µbumps (Equiv. interface resistance R 1 =18 Kmm 2 /W) 25µm thick stacked die using Cu-Cu bonding (Equiv.interface resistance R 2 =0.8 Kmm 2 /W) Temperature Profile 50x50 µm 2 Hot Spot R1 = 18 Kmm 2 /W R2 = 0.8 Kmm 2 /W Peak temperature 50x50 µm 2 hot spot as a function of the Si substrate thickness R1 = 18 Kmm 2 /W R2 = 0.8 Kmm 2 /W Distance from hot spot center (µm) Thickness die (µm) ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

20 3D CHIP-PACKAGE INTERACTION, 3D-CPI DIE STACKING INDUCED STRESS 25 mm Ø bump, 15 µm spacing, 40 µm pitch difference in CTE bump connection and the underfill material shrinkage underfill material during curing Microbump Underfill Top thinned Si die Cool down After assembly Wavy top Si Bottom Si die ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

21 Relative variation Ion current NMOS FET Relative Variation Ion current EXPERIMENTAL VALIDATION 25 µm thick Si die, non-filled underfill Top Si die Bottom Si die Stress extraction position Underfill µbump NMOS array close to µbump Reference Si: w/o NUF NMOS reference array Model (no µbump) µbump Si: with location NUF FEM Model result Mitigation strategy Use of low-cte underfill (filled with e.g. silica part.) Thinner µbump/underfill layers: narrow gaps Use of thicker die > 50µm µbump pitch 200 µm 150 µm 100 µm 50 µm Center Center row row of NMOS of PMOS devices (62µm wide) µm wide) ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

22 OUTLINE 3D Technology Convergence scaling: Technology Directions Scaling: Cost of Ownership analysis Scaling Roadmap ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

23 8% 27% Relative Cost 35% COST STRUCTURE 5X50 PROCESS 180% 160% 140% CMP Cu ECD barrier/seed liner litho + etch 120% Cost structure: 100% 80% CMP 60% 40% 20% 0% 31% 14% 13% Cu ECD B/Seed Liner etch 3D POR 5 µm Ø; 50 µm deep Importance CMP process: removal of different layers, high cost CMP slurry ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

24 8% Relative Cost 13% 35% 49% INTERPOSER : UPSCALING TO 10X100 µm 180% CMP 160% Cu ECD barrier/seed 140% 120% 100% 80% 60% 40% 20% 0% 19% 24% 39% 18% CMP Cu ECD B/Seed Liner etch Interposer 10 µm Ø; 100 µm deep 31% 14% CMP Cu ECD B/Seed Liner etch 3D POR 5 µm Ø; 50 µm deep Cost structure: liner litho + etch Increased etch depth : 2x longer Low Capacitance: thicker liner Slower Cu plating: 3x time Thicker Layers for CMP Appr. 50% higher cost Similar cost breakdown, Higher impact fill ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

25 36% 8% 4% 17% Relative Cost 13% 42% 35% 11% 22% 49% DOWNSCALING TO 3X50 µm 180% 160% 140% 120% CMP CMP Cu ECD barrier/seed liner litho + etch Cost structure: Slightly increased etch time Equal Capacitance: thiner liner New barrier/seed Process Thiner layers: less CMP Similar or lower cost possible 100% 80% 60% 40% 20% 0% 19% 24% 39% 18% Cu ECD B/Seed Liner etch Interposer 10 µm Ø; 100 µm deep 31% 14% CMP Cu ECD B/Seed Liner etch 3D POR 5 µm Ø; 50 µm deep CMP Cu ECD B/Seed Liner etch CVD TiN PVD Cu ECD Cu 3D POR 3 µm Ø; 50 µm deep CMP Cu ECD CVD TiN CVD RuTiN Liner etch ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

26 OUTLINE 3D Technology Convergence scaling: Technology Directions Scaling: Cost of Ownership analysis Scaling Roadmap ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

27 3D- SCALING ROADMAP Reverse scaling for interposer applications 10µm Ø, 100µm deep, AR 10:1 Ø AR Depth POR Today 5µm Ø, 50µm deep AR 10:1 Scaling for 3D-IC applications Ø AR Depth 3µm Ø, 50µm deep AR 17:1 Ø AR Extended scaling W2W applications Depth 2µm Ø, 30µm deep AR 15: Return to POR 5x50µm (driven by cost reduction, ability to assemble on thin interposers & active interposer applications) Minimal fill Ø? Max. depth? In combination with integration on advanced device nodes ERIC BEYNE - SEMI EUROPE - EUROPEAN 3D SUMMIT - 22/01/

28 ACKNOWLEDGMENT Imec 3D Team and 3D System Integration Program Partners LOGIC IDM MEMORY IDM FOUNDRIES FABLESS 3D PROGRAM OSAT EDA MATERIAL SUPPLIERS EQUIPMENT SUPPLIERS Lam RESEARCH 3D SYSTEM INTEGRATION PROGRAM 29

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