Xilinx Spartan -3 XC3S200 FT256AFQ Structural Analysis

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Blake Maxwell
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1 June 18, 2004 Xilinx Spartan -3 XC3S200 FT256AFQ Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Major Findings 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 Isolation 3.8 Wells and Epi 4 SRAM Cell Analysis 4.1 SRAM Plan View Analysis 5 Materials Analysis 5.1 SIMS Analysis of the Dielectrics 5.2 TEM-EDS Analysis of Metal EDS Analysis of ILD 1 and the Pre-Metal Dielectics 5.4 Transistor, Contacts, polycide and STI 5.5 SRP Analysis of the Wells and Substrate

3 Structural Analysis 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions About Chipworks

4 Overview 1 Overview 1.1 List of Figures 2 Device Overview Package Top Package Bottom Plan View Package X-Ray Side View Package X-Ray Die Photograph Die at Metal Die Marking Die Marking Die Corner Die Corner Die Corner Die Corner Pad Ring and Bond Pads Pad Ring and Power Buses Bond Pads 3 Process Analysis General View of the XC3S200 FT256AFQ Die Edge Die Seal Ball Bond to Bond Pad Bond Pad Edge Passivation ILD 7 and ILD TEM Image of ILD ILD TEM Image of ILD 5 Line Dielectric ILD 4 Through ILD 2 Levels TEM Image of ILD Pre-Metal Dielectric Minimum Pitch Metal TEM Section of Metal Minimum Pitch Metal TEM Cross-Section of Metal 7 1-1

5 Overview Metal 7 Ta/TaN Bilayer Minimum Pitch Metal TEM of Minimum Pitch Metal Minimum Pitch Metal TEM of Minimum Pitch Metal Minimum Pitch Metal TEM of Minimum Pitch Metal TEM of Metal 1 Ta/TaN Liner Minimum Pitch Via 6 s and Via 5 s TEM Section of Via Minimum Pitch Via 5 s Through Via 2 s TEM Section of a Via Minimum Pitch Via 1 s Minimum Pitch Contacts to Diffusion Minimum Pitch Contacts to Polycide TEM of Metal 1 to Contact Interface TEM of Contact to Diffusion TEM of Contact to Polycide Minimum Gate Length NMOS Transistor Minimum Gate Lenth PMOS Transistor TEM of Logic Transistor TEM of Thick Gate Oxide TEM of Thin Gate Oxide Minimum Pitch Polycide Minimum Width STI Polycide Over STI Polycide Over Field Oxide TEM of Thick Gate Dielectric SCM Profile of N-Well and P-Well 4 SRAM Cell Analysis T SRAM Cell Dual Port SRAM at Metal SRAM at Metal SRAM at Polycide SRAM Cell at Polycide SRAM Delayered to Diffusion 1-2

6 Overview 5 Materials Analysis SEM Cross-Section Showing Dielectric Levels SIMS Profile Through the Dielectrics TEM Cross-Section of Metal TiN Cap Layer TEM-EDS Spectrum of the TiN Barrier Layer TEM-EDS Spectrum of the Ti Adhesion Layer TEM-EDS Spectrum of the Ta Barrier Layer EDS Spectrum of ILD EDS Spectrum of ILD EDS Spectrum of PMD EDS Spectrum of PMD EDS Spectrum of PMD EDS Spectrum of PMD TEM-EDS Spectrum of the Gate Polycide TEM-EDS Spectrum of Source/Drain Silicide N-Well SRP Plot P-Well SRP Plot 6 Critical Dimensions 7 Report Evaluation 1.2 List of Tables Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Transistor and Polycide Dimensions SRAM Transistor Sizes 1-3

7 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: [email protected] Please send any feedback to [email protected]

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