Data Converter Fundamentals

Transcription

1 Data Converter Fundamentals David Johns and Ken Martin slide 1 of 33

2 Introduction Two main types of converters Nyquist-Rate Converters Generate output having a one-to-one relationship with a single input value. Rarely sample at Nyquist-rate because of need for antialiasing and reconstruction filters. Typically 3 to 20 times input signal s bandwidth. Oversampling Converters Operate much faster than Nyquist-rate (20 to 512 times faster) Shape quantization noise out of bandwidth of interest, post signal processing filters out quantization noise. slide 2 of 33

3 Ideal D/A Converter B in D/A V out V ref defined to be an N-bit digital signal (or word) B in equals 1 or 0 (i.e., b i is a binary digit) b i B in = b b b N 2 N is MSB while is LSB b 1 B in b N Assume is positive unipolar conversion (1) slide 3 of 33

4 Ideal D/A Converter Output voltage related to digital input and reference voltage by V out = V ref ( b b b N 2 N ) = V ref B in Max V out is V ref ( 1 2 N ) Multiplying DAC realized by allowing V ref to be another input signal Ideal DAC has well-defined values (not same for A/D) (2) slide 4 of 33

5 Ideal DAC Converter V out V ref 1 2-bit DAC 3/4 1/2 1/4 V LSB V ref 1 = -- = 1LSB (100) B in and V LSB V ref 2 N 1LSB = N slide 5 of 33

6 Example An 8-bit D/A converter has = 5 V. V ref What is the output voltage when B in = ? B in = = V out = V ref B in = V Find V LSB. VLSB = = 19.5 mv (3) (4) (5) slide 6 of 33

7 Ideal A/D Converter V in A/D B out V ref V ref ( b b b N 2 N ) = V in ± V x (6) where 1 -- V 2 LSB V x 1 < --V 2 LSB (7) slide 7 of 33

8 Ideal A/D Converter V LSB B = 1/4 = 1LSB out V ref /4 1/2 3/4 1 V 01 V V ref 11 V ref V in V ref A range of valid input values produces same digital output word quantization error. No quantization error in D/A converter case. slide 8 of 33

9 Ideal A/D Converter Transitions offset by 0.5V LSB so midpoint are same as D/A case Quantizer Overload Quantization error limited to ± V LSB 2 otherwise quantizer is said to be overloaded. Overloading occurs when input signal is beyond one of the two last transition voltages. In 2-bit example, input should be greater than 1 8 V ref and less than 7 8 V ref V LSB slide 9 of 33

10 Quantization Noise V in A/D B V 1 D/A + V Q Quantization noise V in V V 2 LSB V Q t (Time) 1 --V 2 LSB T t (Time) V Q V 1 V in = V 1 V in V Q or = + (8) slide 10 of 33

11 Quantization Noise V Q V in V 1 V in V 1 V 1 = V in + V Q Quantizer Model Above model is exact approx made when assumptions made about V Q Often assume V Q is white, uniformily distributed number between ± V LSB 2 slide 11 of 33

12 Quantization Noise Average of quantization noise is zero. Power of quantization noise can be shown to equal V Qrms = Each extra bit results in noise power decrease of 3dB Noise power is independent of sampling frequency If assume input signal is a sinusoid of peak amplitude of V ref 2 ( ) V LSB (9) V in rms ( ) SNR = 20 log = 20 V Qrms ( ) SNR = 6.02N db V ref ( 2 2) log V LSB ( 12) slide 12 of 33

13 SNR (db) Quantization Noise 10-bit Best possible SNR ( V pp = V ref ) V in ( db) SNR reaches max when input signal is max (might improve SNR if oversampling used) slide 13 of 33

14 Example A 100-mV pp sinusoidal signal is applied to an ideal 12-bit A/D converter for which V ref = 5 V. Find the SNR of the digitized output signal. First, find max SNR if full-scale sinusoidal waveform of ±2.5 V applied SNR max = = 74 db Since input is only ± 100-mV it is 28 db below full scale, so SNR of digitized output is SNR = = 46 db (10) (11) slide 14 of 33

15 Signed Codes Often need converters for both positive and negative signals signed codes Sign Magnitude Neg numbers simply invert MSB 1 s Complement Neg numbers invert all bits Offset Binary Assign to most negative number and count up 2 s Complement Invert MSB of offset binary case or... Neg numbers are 1 LSB larger than 1 s complement slide 15 of 33

16 Number Normalized number Signed Codes Sign magnitude 1 s complement Offset binary 2 s complement most common when doing signal processing 2 s complement +3 +3/ / / ( 0) ( 0) (100) (111) 1 1/ / / / slide 16 of 33

17 2 s Complement Offset Binary 2 s Complement Each have wrap-around behaviour slide 17 of 33

18 2 s Complement Benefits Addition of both positive numbers is done with simple addition (nothing extra needed) Subtraction of A B done by complementing bits of B and adding LSB into carry-in of adder Can go above max as long as final result is within range (no overflow hardware needed) Example 2+3+(-4) = = = 001 Final result of 1 correct though temp result of -3 obtained slide 18 of 33

19 Performance Limitations For D/A measure, use output voltage levels For A/D measure, use transition points (easier than midpoints) B out V LSB = 1/4 = 1LSB V ref /4 1/2 3/4 1 V 01 V V ref 11 V ref V in V ref slide 19 of 33

20 Offset and Gain Error V out V ref 1 3/4 1/2 1/4 Offset error Ideal Gain error (100) B in slide 20 of 33

21 Offset and Gain Errors

22 Offset and Gain Error D/A converter units of LSB: V out E off( D A) = V LSB A/D converter deviation of V 0 01 from 1 2 LSB 0 0 V 0 01 E off( A D) = V LSB 1 -- LSB 2 With gain error, set offset error to zero V out E gain( D A) = V LSB 1 1 V 1 1 E gain( A D) = V LSB V out V LSB V 0 01 V LSB 0 0 ( 2 N 1) ( 2 N 2) (12) (13) (14) slide 21 of 33

23 Resolution Resolution and Accuracy Number of distinct analog levels n resolve 2 N distinct analog levels. Absolute Accuracy N-bit resolution can Difference between the expected and actual transfer responses includes offset, gain and linearity errors Relative Accuracy After offset and gain errors removed also called maximum integral nonlinearity error A 12-bit accuracy implies that the converter s error is less than the full-scale value divided by 2 12 slide 22 of 33

24 Resolution and Accuracy A converter may have 12-bit resolution with only 10-bit accuracy Another converter may have 10-bit resolution with 12-bit accuracy. Accuracy greater than resolution means converter s transfer response is very precisely controlled better than the number of bits of resolution. Example A two bit D/A (resolution 2-bits) with output levels at 0.0, 1/4, 2/4, 3/4 is ideal (infinite bit accuracy since no errors) slide 23 of 33

25 Integral Nonlinearity (INL) Error V out V ref Integral nonlinearity error (best-fit) 1 3/4 1/2 Integral nonlinearity error (endpoint) 1/ (100) B in slide 24 of 33

26 INL Error After both offset and gain errors removed, integral nonlinearity (INL) error is deviation from a straight line. Can use endpoint or best fit straight lines endpoint more conservative INL plotted for each digital word INL 0.5LSB max INL (100) B in Maximum INL also referred to as relative accuracy slide 25 of 33

27 Differential Nonlinearity (DNL) Error Ideally, each step is 1 LSB away from adjacent level DNL defined as variation in step sizes from 1 LSB (once gain and offset errors removed) Example Max DNL = 0.5 LSB has at least one step size which is either 0.5 LSB or 1.5 LSB As in INL error, DNL plotted for each digital word and max is maximum magnitude. DNL 0.5LSB max DNL (100) B in step size between 00 and 01 is 1.5 LSB step size between 10 and 11 is 0.7 LSB slide 26 of 33

28 INL and DNL

29 INL and DNL

30 3-bit ADC Characteristic

31 INL and DNL

32 Monotonic D/A Converters Monotonicity Where output alway increases as input increases no negative slope in transfer-response Important for some control loop applications If max DNL < 1 LSB, converter is monotonic Can be monotonic and have DNL > 1 LSB If max INL < 0.5 LSB, converter is monotonic Missing Code A/D Converters Similar to monotonic but for A/D converter Increasing analog input skips some digital codes If max DNL < 1 LSB or max INL < 0.5 LSB, no missing codes slide 27 of 33

33 Converter Speed A/D Conversion Time and Sampling Rate Conversion time time for a single measurement Sampling rate max sampling rate (typically inverse of conversion time) Note that converter might have latency due to pipelining D/A Settling Time and Sampling Rate Settling time time for converter to settle to within a specified resolution (typically 0.5 LSB) Sampling rate max rate (typically inverse of settling time) slide 28 of 33

34 S/H

35 Sampling-Time Uncertainty Error due to variations in sampling time V ref Consider full-scale sine wave: V in = sin( 2πf 2 in t) Rate of change is max at zero crossing If sampling time has variation t, then to keep V less than 1 LSB, require that V LSB 1 t < = πf in V ref 2 N πf in Example 250 MHz sinusoidal signal must keep t < 5 ps for 8-bit accuracy Same 5ps for 16-bit accuracy and 1 MHz sinusoid (15) slide 29 of 33

36 Clock Jitter

37 Dynamic Range Ratio of rms value of max amplitude input sinusoid to rms output noise plus distortion Can be expressed as N, effective number of bits SNR = 6.02N db Often a function of freq of input signal (lower SNR as freq increases) more realistic than only using INL and DNL Note, distortion of some converters not a function of input signal level Other converters (such as oversampling), distortion decreases as signal level decreases (similar to other analog circuits) (16) slide 30 of 33

38 3-bit D/A converter, Example V ref = 4V, with following values { : : : : : : : 3.491} 1 LSB Offset voltage is 11 mv resulting in Gain error E gain D A V ref 2 3 = 0.5 V ( ) = = LSB 0.5 E off D A ( ) = ( 2 3 1) = 0.04 LSB 0.5 For INL and DNL errors, first remove both offset and gain errors (17) (18) slide 31 of 33

39 Offset error removed by subtracting LSB Gain error removed by subtracting off scaled values of gain error. Example new value for (scaled to 1 LSB) given by ( 0.04 ) = Offset-free, gain-free, scaled values are { 0.0 : : : : : : : 7.0} INL errors Since now in units of LSBs, given by difference between values and ideal values { 0 : : : : : : : 0} DNL errors difference between adjacent values and 1 LSB { : : : : : : 0.004} (19) (20) (21) (22) slide 32 of 33

40 Effective Number of Bits ENOB = (SNR_DB 1.76) / 6.02

41 Example A full-scale sinusoidal is applied to a 12-bit A/D If fundamental has a normalized power of 1 W and remaining power is 0.5 µw, what is the effective number of bits for the converter? SNR = 6.02N eff In this case, SNR given by resulting in 1 SNR = 10 log = 63 db N eff = = 10.2 effective bits 6.02 (23) (24) (25) slide 33 of 33

42 Input-Output test for DAC

43 Spectral Output Test for DAC

44 FFT Test for ADC

45 Histogram Test for ADC

46 Input/Output Test for ADC

47 Comparison of Tests for ADCs