Chapter 2 Introduction of IC Fabrication

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1 Chapter 2 Introduction of IC Fabrication Hong Xiao, Ph. D. hxiao89@hotmail.com Objectives Define yield and explain its importance Describe the basic structure of a cleanroom. Explain the importance of cleanroom protocols List four basic operations of IC processing Name at least six process bays in an IC fab Explain the purposes of chip packaging Describe the standard wire bonding and flip-chip bump bonding processes

2 Yield To produce Especially for function test after finished all IC process Yield relative to : Engineers skill Environment Used materials Purchased equipment Process Wafer Process Flow Materials IC Fab Metallization CMP Dielectric deposition Test Wafers Masks Thermal Processes Implant PR strip Etch PR strip Packaging Photolithography Final Test Design

3 Fab Cost Fab cost is very high, > $1B for 8 fab Clean room Equipment, usually > $1M per tool Materials, high purity, ultra high purity Facilities People, training and pay Wafer Yield Y = W Wafers Wafers good total Depends on : processing ; handling ; robot function ; alignment and so on

4 Die Yield Y = D Dies Dies good total Depends on : contamination, maintenance Packaging Yield Y = C Chips Chips good total Depends on : bonding quality

5 Overall Yield Y T = Y W Y D Y C Overall Yield determines whether a fab is making profit or losing money How Does Fab Make (Loss) Money Cost: Wafer (8 ): ~$150/wafer* Processing: ~$1200 ($2/wafer/step, 600 steps) Packing: ~$5/chip Sale: ~200 chips/wafer ~$50/chip (low-end microprocessor in 2000) *Cost of wafer, chips per wafer, and price of chip varies, numbers here are choosing randomly based on general information.

6 How Does a Fab Make (Loss) Money Cost: Sale: 100% yield: = $2350/wafer 50% yield: = $1850/wafer 0% yield: = $1350/wafer 100% yield: = $10,000/wafer 50% yield: = $5,000/wafer 0% yield: 0 50 = $0.00/wafer Profit Margin: 100% yield: = $7650/wafer 50% yield : = $3150/wafer 0% yield : = $1350/wafer Question If yield for every process step is 99%, what is the overall processing yield after 600 process steps?

7 Answer It equals to 99% times 99% 600 times = = 0.24% Almost no yield Throughput Number of wafers able to process Fab: wafers/month (typically 10,000) Tool: wafers/hour (typically 60) At high yield, high throughput brought

8 Defects and Yield Y (1 + 1 DA) n Y : Overall yield D : Defect density A : Chip area n : Process Steps To achieve 100% overall yield : defect must be zero for each process For the same defect density and chip size : the more process steps, the lower yield For the same defect density : the larger chip size, the lower yield Yield and Die Size Killer Defects Y = 28/32 = 87.5% Y = 2/6 = 33.3%

9 Illustration of a Production Wafer Die Test die Illustration of a Production Wafer Test Structures Scribe Lines Dies

10 Clean Room Artificial environment with low particle counts Started in medical application for post-surgery infection prevention Particles kills yield IC fabrication must in a clean room Smaller feature size, requires higher grade purity in clean room Clean Room First used for surgery room to avoid bacteria contamination Adopted in semiconductor industry in 1950 Smaller device needs higher grade clean room Less particle, more expensive to build

11 Clean Room Class Class 10 is defined as less than 10 particles with diameter larger than 0.5 µm per cubic foot. Class 1 is defined as less than 1 such particles per cubic foot mm device require higher than Class 1 grade clean room Cleanroom Classes # of particles / ft Class 100,000 Class 10,000 Class 1,000 Class 100 Class 10 Class 1 Class M Particle size in micron

12 Definition of Airborne Particulate Cleanliness Class per Fed. Std. 209E Class Particles/ft µm 0.2 µm 0.3 µm 0.5 µm 5 µm M Effect of Particles on Masks Particles on Mask Film Stump on +PR Hole on PR Film Substrate Substrate

13 Effect of Particle Contamination Dopant in PR Photoresist Screen Oxide Ion Beam Partially Implanted Junctions Particle Makeup Air Cleanroom Structure Fans Makeup Air Equipment Area Class 1000 Process Tool HEPA Filter Class 1 Process Area Equipment Area Class 1000 Process Tool Return Air Raised Floor with Grid Panels Pump, RF and etc.

14 Mini-environment Class 1000 cleanroom, lower cost Boardroom arrangement, no walls between process and equipment Better than class 1 environment around wafers and the process tools Automatic wafer transfer between process tools Mini-Environment Cleanroom Makeup Air HEPA Filter Fans Makeup Air HEPA Filter Class 1000 Process Tool < Class 1 Class 1000 Process Tool Return Air Raised Floor with Grid Panels Pump, RF and etc.

15 Shelf of Gloves, Hair and Shoe Covers Gowning Area Gown Racks Disposal Bins Entrance Wash/Clean Stations Storage Shelf of Gloves To Cleanroom Shelf of Gloves Benches IC Fabrication Process Module Thin film growth, dep. and/or CMP Photolithography Etching PR Stripping Ion Implantation PR Stripping RTA or Diffusion

16 Illustration of Fab Floor Equipment Areas Process Bays Corridor Sliding Doors Service Area Gowning Area Mini-environment Fab Floor Process and metrology tools Emergency Exits Service Area Gowning Area

17 Wet Processes Etch, PR strip, or clean Rinse Dry Horizontal Furnace Heating Coils Wafers Quartz Tube Gas flow Temperature Center Zone Flat Zone Distance

18 Vertical Furnace Process Heaters Wafers Tower Schematic of a Track Stepper Integrated System Wafer Prep Spin Coater Chill Plates Stepper Chill Plates Developer Hot Plates Wafer Movement

19 Cluster Tool with Etch and Strip s PR Strip PR Strip Etch Robot Etch Transfer Loading Station Unloading Station Cluster Tool with Dielectric CVD and Etchback s O 3 -TOES Ar Sputtering PECVD Robot Transfer Loading Station Unloading Station

20 Cluster Tool with PVD s Al Cu Al Cu Ti/TiN Robot Ti/TiN Transfer Loading Station Unloading Station Dry-in Dry-out CMP System Wafer Loading and Standby Post-CMP Clean Rinse Dryer and Wafer Unloading Clean Station Multi-head Polisher Polishing Pad Polishing Heads

21 Process Bay and Equipment Areas Sliding Doors Process Tools Equipment Area Tables For PC and Metrology Tools Process Area Equipment Area Service Area Wafer Loading Doors Test Results Failed die

22 Chip-Bond Structure Microelectronics Devices and Circuits Chip Backside Metallization Substrate Metallization Chip (Silicon) Solder Substrate (Metal or Ceramic) Melt and Condense Metal Wire Wire Bonding Wire Clamp Bonding Pad Bonding Pad Bonding Pad Formation of molten metal ball Press to make contact Head retreat

23 Wire Bonding Bonding Pad Lead Bonding Pad Lead Lead contact with pressure and heat Clamp closed with heat on to break the wire IC Chip with Bonding Pads Bonding Pads

24 IC Chip Packaging Bonding Pad Chip Pins Chip with Bumps Bumps

25 Flip Chip Packaging Bumps Chip Socket Pins Bump Contact Bumps Chip Socket Pins

26 Heating and Bumps Melt Bumps Chip Socket Pins Flip Chip Packaging Chip Socket Pins

27 Molding Cavity for Plastic Packaging Top Chase Molding Cavity Bonding Wires IC Chip Lead Frame Chip Bond Metallization Pins Bottom Chase Ceramic Seal Bonding Wires IC Chip Cap Seal Metallization Layer 2 Ceramic Cap Layer 2 Lead Frame, Layer 1 Pins Chip Bond Metallization

28 Summary Overall yield Yield determines losing money or making profit Cleanroom and cleanroom protocols Process bays Process, equipment, and facility areas Die test, wafer thinning, die separation, chip packaging, and final test

Lecture 30: Cleanroom design and contamination control

Lecture 30: Cleanroom design and contamination control Contents 1 Introduction 1 2 Contaminant types 2 2.1 Particles.............................. 2 2.2 Metal ions............................. 4 2.3 Chemicals.............................