Reduced Instruction Set Computer

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1 Reduced Instruction Set Computer Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay Computer Organization & Architecture Lecture 11 (09 April 2013)

2 Processor Architecture PI Controlle r Control Signals From memory Datapath Status Signals PO To memory 08 Apr 2013 Computer Architecture@IIT Mandi 2

3 Where Does It All Begin? In a register called program counter (PC). PC contains the memory address of the next instruc9on to be executed. In the beginning, PC contains the address of the memory loca9on where the program begins. 08 Apr 2013 Computer Architecture@IIT Mandi 3

4 Where is the Program? Processor Memory Program counter (register) Start address Machine code of program 08 Apr 2013 Computer Mandi 4

5 How Does It Run? Start PC has memory address where program begins Fetch instruction word from memory address in PC and increment PC PC + 4 for next instruction Decode and execute instruction No Program complete? Yes STOP 08 Apr 2013 Computer Architecture@IIT Mandi

6 Datapath and Control Ø Datapath: Memory, registers, adders, ALU, and communica9on buses. Each step (fetch, decode, execute) requires communica9on (data transfer) paths between memory, registers and ALU. Ø Control: Datapath for each step is set up by control signals that set up dataflow direc9ons on communica9on buses and select ALU and memory func9ons. Control signals are generated by a control unit consis9ng of one or more finite- state machines. 08 Apr 2013 Computer Architecture@IIT Mandi 6

7 Datapath for Instruction Fetch 4 Add PC Address Instruction Memory Instruction word to control unit and registers 08 Apr 2013 Computer Architecture@IIT Mandi 7

8 Register File: A Datapath Component Read registers Write register Write data reg 1 reg 2 Registers (reg. file) reg 1 data reg 2 data RegWrite from control 08 Apr 2013 Computer Architecture@IIT Mandi 8

9 Multi-Operation ALU Opera9on select ALU func9on 000 AND 001 OR 010 Add 110 Subtract 111 Set on less than Operation select from control ALU 3 zero overflow result zero = 1, when all bits of result are 0 08 Apr 2013 Computer Architecture@IIT Mandi 9

10 R-Type Instructions Also known as arithme9c- logical instruc9ons add, sub, slt Example: add $t0, $s1, $s2 Machine instruc9on word opcode $s1 $s2 $t0 func9on Read two registers Write one register Opcode and func9on code go to control unit that generates RegWrite and ALU opera9on code. 08 Apr 2013 Computer Mandi 10

11 Datapath for R-Type Instruction opcode $s1 $s2 $t0 function (add) Read register numbers Write reg. number $s1 $s2 $t0 Registers (reg. file) Operation select from control (add) ALU 3 zero overflow result Write data RegWrite from control activated 08 Apr 2013 Computer Architecture@IIT Mandi 11

12 Load and Store Instructions I- type instruc9ons lw $t0, 1200 ($t1) # incr. in bytes opcode $t1 $t sw $t0, 1200 ($t1) # incr. in bytes opcode $t1 $t Apr 2013 Computer Architecture@IIT Mandi 12

13 Read register numbers Write reg. number Write data Datapath for lw Instruction opcode $t1 $t $t1 $t0 16 Registers (reg. file) RegWrite from control activated Sign extend ALU Operation select from control (add) 08 Apr 2013 Computer Mandi 13 3 zero overflow result mem. data to $t0 Addr. Write data MemWrite Read data Data memory MemRead activated

14 Read register numbers Write reg. number Write data Datapath for sw Instruction opcode $t1 $t $t1 $t0 16 Registers (reg. file) RegWrite from control Sign extend ALU Operation select from control (add) 08 Apr 2013 Computer Mandi 14 3 zero overflow result $t0 data to mem. MemWrite activated Addr. Write data Read data Data memory MemRead

15 Branch Instruction (I-Type) beq $s1, $s2, 2 # if $s1 = $s2, advance PC through 2 instruc9ons Note: 16- bits opcode $s1 $s2 2 Can branch within ± 2 1 words from the current instruction address in PC. 08 Apr 2013 Computer Architecture@IIT Mandi 1

16 Datapath for beq Instruction Read register numbers Write reg. number Write data $s1 $s2 Sign extend Registers (reg. file) RegWrite from control Shift left opcode $s1 $s2 2 Operation select from control (subtract) 3 ALU zero overflow PC+4 From instruction fetch datapath result To branch control logic Add Branch target 08 Apr 2013 Computer Architecture@IIT Mandi 16

17 J-Type Instruction j 200 # jump to instruc9on 2, bits opcode 2, bits from PC+4 -bit jump address 08 Apr 2013 Computer Architecture@IIT Mandi 17

18 Datapath for Jump Instruction Branch 4 Add Branch addr. PC+4 1 mux 0 Jump 0 mux 1 4 PC Address Instruction Memory 26 Shift left 2 opcode (bits 26-31) to control 6 28 Instruction word to control and registers 08 Apr 2013 Computer Architecture@IIT Mandi 18

19 0-2 Jump Shift 4 Add RegDst opcode left 2 CONTROL Branch ALU 1 mux 0 0 mux 1 MemtoReg PC Instr. mem. Combined Datapaths Sign ext. 1 mux 0 Reg. File Shift left 2 1 mux 0 ALU ALU Cont. zero MemWrite MemRead Data mem. 0 mux Apr 2013 Computer Architecture@IIT Mandi 19

20 Control Logic Instruction bits opcode Instruction bits 0- funct. Control Logic ALUOp RegDst Jump Branch MemRead MemtoReg MemWrite ALUSrc RegWrite ALU Control 08 Apr 2013 Computer Mandi 20 2 to ALU

21 Control Logic: Truth Table Instr type Inputs: instr. opcode bits RegDst Jump Outputs: control signals Branch MemWrite MemRead RegWrite MemtoReg ALUSrc ALOOp1 ALUOp2 R lw sw X 0 1 X beq X 0 0 X j X 1 X X X X X X X X 08 Apr 2013 Computer Architecture@IIT Mandi 21

22 How Long Does It Take? Assume control logic is fast and does not affect the cri9cal 9ming. Major 9me delay components are ALU, memory read/write, and register read/write. Arithme9c- type (R- type) Fetch (memory read) 2ns Register read 1ns ALU opera9on 2ns Register write 1ns Total 6ns 08 Apr 2013 Computer Mandi 22

23 Time for lw and sw (I-Types) ALU (R- type) 6ns Load word (I- type) Fetch (memory read) 2ns Register read 1ns ALU opera9on 2ns Get data (mem. Read) 2ns Register write 1ns Total 8ns Store word (no register write) 7ns 08 Apr 2013 Computer Mandi 23

24 Time for beq (I-Type) ALU (R- type) 6ns Load word (I- type) 8ns Store word (I- type) 7ns Branch on equal (I- type) Fetch (memory read) 2ns Register read 1ns ALU opera9on 2ns Total ns 08 Apr 2013 Computer Mandi 24

25 Time for Jump (J-Type) ALU (R- type) 6ns Load word (I- type) 8ns Store word (I- type) 7ns Branch on equal (I- type) ns Jump (J- type) Fetch (memory read) 2ns Total 2ns 08 Apr 2013 Computer Mandi 2

26 How Fast Can the Clock Be? If every instruc9on is executed in one clock cycle, then: Clock period must be at least 8ns to perform the longest instruc9on, i.e., lw. This is a single cycle machine. It is slower because many instruc9ons take less than 8ns but are s9ll allowed that much 9me. Method of speeding up: Use mul9cycle datapath. 08 Apr 2013 Computer Architecture@IIT Mandi 26

27 Thank You 08 Apr 2013 Computer Mandi 27

Solutions. Solution 4.1. 4.1.1 The values of the signals are as follows:

Solutions. Solution 4.1. 4.1.1 The values of the signals are as follows: 4 Solutions Solution 4.1 4.1.1 The values of the signals are as follows: RegWrite MemRead ALUMux MemWrite ALUOp RegMux Branch a. 1 0 0 (Reg) 0 Add 1 (ALU) 0 b. 1 1 1 (Imm) 0 Add 1 (Mem) 0 ALUMux is the