Current Limit Versus Energy Limit Based PSE

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1 Current Limit Versus Energy Limit Based PSE Thong Huynh Maxim Integrated Products Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 1

2 Review of PoE+ System Consideration PoE+ System Requirements: System Inter-Operability Allow Safe Maximum Possible Power Delivered from PSE to PD Adhere to the Maximum Current Allowed *: In the Cable In the Connector In the Patch Panel In the LAN Magnetics Backward Compatible w/ 802.3af Legacy Devices Support 180uF capacitor on PD Simplify Compliant Testing *Note: Maximum current value for cable, connector, and patch panel are determined by heating effect which causes by DC/RMS current. Low level transient current that lasted less than a few seconds does not cause significant heating and could be neglected Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 2

3 Review of PoE+ System Consideration PSE Requirements: PD Detection, L1 Classification, Optional L2 Classification Handle Input Power Supply Voltage Transient Protect Port Short Circuit Condition Provide as Much Power as Possible to the PD, Limited only by the Cable Capability PD Requirements: Provide Detection and Classification Signatures Manage Input Ripple Current Handle Load Step Transient Utilize as Much Power as Possible from the PSE When the Application Requires Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 3

4 MOSFET Power Dissipation During Inrush Period for Both PoE and PoE PSEs 57V V DS Vport 0V Ilim (400mA) 26ms t = C dv/i = 180uF x 57V / 400mA = 26 ms peak = 57V x 400mA = 22.8W = 1/2 x peak x t = 1/2 x 22.8W x 26ms = 296.4mJ Energy Dissipated in the MOSFET During Inrush - PoE & PoE+ Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 4

5 Current Limit Based - Input Voltage Transient: PoE PoE+ 57V 57V Vps Vport 50V 7V 44V Ilim min (400mA) 13V 46.8ms Ilim min (820mA) Ilim min (770mA) 12.6ms 25.6ms Icut min (350mA) 50mA Icut min (720mA) 100mA 50mA In PoE+ system, there is plenty of head room to handle input transient and PD load step at the same time Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 5

6 Current Limit Based - MOSFET Power Dissipation During Input Transient for PoE+ PSE V DS 57V Vport 50V Ilim (820mA) 7V 25.2ms t = C dv/i = 180uF x 7V / 50mA = 25.2 ms peak = 7V x 820mA = 5.74W Current Limit Based PSE Limits the Peak Current to 820mA = 1/2 x peak x t = 1/2 x 5.74W x 25.2ms = 72.3mJ Energy Dissipated in the MOSFET During Input Transient and PD Load Step, Allowing 50mA Load Step above PD maximum average current for 50ms - PoE+ Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 6

7 Current Limit Based Output Short Circuit Current Limit Based PSE Limits the Peak Current to 820mA Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 7

8 MOSFET Power Dissipation Calculation 57V V 57V DS V DS Vport Vport 0V Ilim (400mA) 26ms t = C dv/i = 180uF x 57V / 400mA = 26 ms 50V Ilim (820mA) 7V 25.2ms t = C dv/i = 180uF x 7V / 50mA = 25.2 ms peak = 57V x 400mA = 22.8W peak = 7V x 820mA = 5.74W = 1/2 x peak x t = 1/2 x 22.8W x 26ms = 296.4mJ = 1/2 x peak x t = 1/2 x 5.74W x 25.2ms = 72.3mJ Energy Dissipated in the MOSFET During Inrush - PoE & PoE+ Energy Dissipated in the MOSFET During Input Transient and PD Load Step, Allowing 50mA Load Step above PD maximum average current for 50ms - PoE+ MOSFET Power Dissipation Dominates During Inrush Period Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 8

9 Truth or Myth? Current Limit Based Causes Higher Power Dissipation in the Power MOSFET in PoE+ System? Myth The Truth is: Power Dissipation in the MOSFET is Largest During the Inrush Period. This Power Dissipation is the same for PoE and PoE+ Systems, Whether Current Limit or Energy Limit Based is used. This Large Power Dissipation During Inrush is What Has Been Impeding the Integration of the Power MOSFET in the PSE Controller. Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 9

10 Energy Limit Based - Input Voltage Transient Short Cable: Rcable = 1.0Ω (estimated: includes all PSE power path impedances) Input Voltage Transient from 50V to 57V dv/dt maximum = 3.5V/us PD capacitance = 180uF Peak Current Due to dv/dt = 180uF x 3.5V/us = 630A! Peak Current is Limited Only by Rcable = (57V 50V)/1.0Ω = 7A Energy Limit Based PSE Does Not Limit the Peak Current! Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 10

11 Energy Limit Based - Output Short Circuit Short Cable: Rcable = 1.0Ω (estimated: includes all PSE power path impedances) Input Voltage = 57V Maximum Peak Current is Limited Only by Rcable = 57V/1.0Ω = 57A Energy Limit Based PSE Does Not Limit the Peak Current! Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 11

12 Energy Based PSE - Testability Energy Based PSE Dictates Complex Model for Testing Graph is from the Vport Ad-Hoc presentation Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 12

13 Current Limit vs Energy Limit for PoE+ PSE Current Limit Energy Limit Advantages/Problem MOSFET Power Dissipation During Inrush 246.4mJ 246.4mJ Same Peak Current During Input Transient short cable 820mA (920mA Maximum) 7A Current is guaranteed to be limited High current peak can saturate and possibly damage the LAN Magnetics Peak Current During Output Short Circuit 820mA (920mA Maximum) 57A Current is guaranteed to be limited High current peak can saturate the LAN Magnetics, possibly damage it and other such as connector and patch panel Testability Simple and same as 802.3af Complex Curve Energy Limit Based PSE Added testing complexity and cost Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 13

14 Conclusion: Energy Limit Based For PoE+ System Energy Limit Based PSE Does Not Limit Peak Current During Input Transient Possible LAN Magnetics Core Saturation and Data Corruption? Energy Limit Based PSE Does Not Limit Peak Current During Output Short Circuit Possible Damage to Connector, Patch Panel, LAN Magnetics? Energy Limit Based PSE Creates Challenges For Compliant Testing Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 14

15 Conclusion: Current Limit Based For PoE+ System Current Limit Based PSE Can Easily Handle Simultaneous Input Voltage Transient and PD s Load Step Current Limit Based Assures PSE Port Current < 926mA Maximum for < 75ms During Input Transient Current Limit Based PSE Assures Port Current < 926mA Maximum for < 75ms During Output Short Circuit Current Limit Based PSE Eases Compliant Testing Current Limit Based is the Recommended Technique to Limit the PSE Port Current in PoE+ System Thong Huynh - IEEE 802.3at Interim Seoul - Sept 07 15

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