5. CMOS Operational Amplifiers Analog Design for CMOS VLSI Systems

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2 Basic op-amp The ideal operational amplifier is a voltage controlled voltage source with infinite gain, infinite input impedance and zero output impedance. The op-amp is always used in feedback configuration. 1

3 Typical feedback configuration V 0 = V 2 Z 4 Z 3 + Z 4 Z 1 + Z 2 Z 1 V 1 Z 2 Z 1 Finite gain effect: Z V 0 = V 4 Z 1 + Z 2 Z 2 V Z 1 + Z 2 Z 3 + Z 4 Z 1 Z 1 A 0 Z 1 The error due to the finite gain is proportional to 1 / A 0. This error must be smaller than the error due to impedance mismatch. 2

4 OTA If impedances are implemented with capacitors and switches, after a transient, the load of the op-amp is made of pure capacitors. The behavior of the circuit does not depend on the output resistance of the op-amp and stages with high output resistance (operational transconductance amplifiers) can be used. 3

5 Transient V i (0 + ) = V in C 1 C 1 + C // C 0 V o (0 + ) = V i (0 + ) C C 0 + C V i () = V in C 1 + C C 1 + C(1+ g m r 0 ) V o () = V i () g m r 0 C 0 g m 4

6 Performance characteristics Actual op-amps deviate from the ideal behavior. The differences are described by the performance characteristics. DC differential gain: It is the open-loop voltage gain measured at DC with a small differential input signal. Typically A d = db. 5

7 Common mode gain: It is the open-loop voltage gain with a small signal applied to both the input terminals. A cm = db. Common mode rejection ratio: It is defined as the ratio between the differential gain and the common mode gain. Typically CMRR = db. 6

8 Power supply rejection ratio: If a small signal is applied in series with the positive (or negative) power supply, it is transferred to the output with a given gain A ps+ (or A ps- ). The ratios between differential gain and power supply gains furnish the two PSRRs. Typically: PSRR = 90 db (DC) PSRR = 60 db (1 khz) PSRR = 30 db (100 khz) 7

9 Input offset voltage: In real circuits if the two input terminals are set at the same voltage the output saturates close to V DD or to V SS. Typically V os = 4 6 mv. Input common mode range: It is the maximum range of the common-mode input voltage which do not produce a significant variation of the differential gain. 8

10 Output voltage swing: It is the swing of the output node without generating a defined amount of harmonic distortion. Equivalent input noise: The noise performances can be described in terms of an equivalent voltage source at the input of the op-amp. Typically v n = nv/hz at 1 khz, in a wide band (1 MHz) it results V RMS. 9

11 Unity gain frequency: It is the frequency where the open-loop gain is zero. It is also the -3 db bandwidth in unity-gain closed loop conditions. Typically f T = 200 MHz. Phase margin: It is the phase shift of the small-signal differential gain measured at the unity gain frequency. A phase margin smaller than 60 causes ringing in the output response. 10

12 Slew rate: It is the maximum slope of the output voltage. Usually it is measured in the buffer configuration. The positive slew rate can be different from the negative slew rate. Typically SR = V/s (lower values for micropower operation). Settling time: The settling time is the time required to settle the output within a given range (usually ± 0.1%) of the final value. Power dissipation: It depends on speed and bandwidth requirements. Typically, for 3.3 V supply, it is around 1 mw. 11

13 Typical parameters of a 0.25 m OTA Feature Value DC gain 80 CMRR 40 Offset 4-6 Bandwidth 100 Slew-rate 3 Settling time: 1 V, C L = 4 pf 300 DC 90 1 khz khz 30 Input referred noise (white) 100 Corner frequency 1 Supply voltage 3.3 Input common mode voltage 1.5 Output dynamic range 2.2 Power consumption 1 Silicon area 2000 Unit db db mv MHz V/s ns db db db nv/hz khz V V V pp mw m 2 12

14 Basic architecture 1st gain stage differential to single-ended converter 2nd gain stage output stage (to reduce the output impedance) Key requirements: absolute stability in unity gain closed-loop conditions when driving maximum load. minimum number of gain stages. 13

15 Two-stage op-amp Key design issues: open-loop differential gain dc offset power supply rejection (PSRR) 14

16 Open-loop differential gain: The gain is obtained by multiplying the gains of the two stages. A v = A 1 A 2 = g m1 (g ds2 + g ds4 ) g m5 (g ds5 + g ds6 ) = = 2 2µ nµ p C ox ( n + p ) 2 W L 1 W L 6 W L 5 W L W L 7 B 1 I Bias At low frequency the gain is inversely proportional to the bias current. 15

17 Common mode dc gain: Applying the same signal to both inputs the circuit becomes symmetrical and can be studied considering half circuit. A CM = A CM1 A CM2 = g ds7 2g m1 g m5 g ds5 + g ds6 CMRR = A v A CM = 2g m1 g m3 g ds7 (g ds2 + g ds 4 ) 16

18 Offset: The offset is composed of two terms: systematic offset random offset The systematic offset can be reduced to zero with a careful design. A necessary condition to have zero systematic offset, is that the currents of M5 and M6 are equal, when the inputs are connected to the same voltage. Assuming all the transistors in saturation this condition is: I Bias ( W L) ( W L) ( W L) ( 6 = I W L) 7 Bias ( W L) ( 5 W L) B B 3 ( W L) ( W L) = 1 ( W L ) ( W L)

19 The random offset is due to the geometrical mismatching and process dependent inaccuracies. When we refer the offset of the second stage at the input terminal we have to divide it by the gain of the first stage. Since the two offsets are uncorrelated we have: V os = 2 + V os2 V os1 The total offset is dominated by the offset of the input stage. A

20 We study the effect of a mismatch between M3 and M4: mirror factor (1 + ) instead of 1. I Bias 2 g m1 V os ( ) = I Bias 2 + g m2 V os1 2 V os1 I 1 g m1 19

21 MOS: I 1 = V V GS1 Th g m1 2 = mv (in saturation) I 1 = nv T = nkt g m1 q (in sub-threshold) BJT: I 1 g m1 26 mv Assuming = 0.01: V os,bjt = 0.26 mv V os,mos = mv 20

22 Power supply rejection: A signal on the positive bias line determines a modulation in the reference current, which, in turn, gives an equal modulation of the currents in M5 and M6, if the condition of the zero systematic offset is fulfilled. 21

23 The spur signal v + n affects the currents of M5 and M6. i n,6 = ( W / L) 6 i n,7 = µc ( + ( W / L) ox V GS,MB V Th )v n 7 a) low frequency: + W / L v o,n,1 = i n,tot W / L ( ) ( ) B ( W / L) ( W / L) ( 5 7 W / L) ( W / L) 4 B g ds6 1 + g ds7 b) high frequency: v o,n,1 = i n,ref ( W / L) 6 W / L ( ) B 1 g m5 22

24 Power supply rejection at low frequency ( v ) 2 o,tot = g ds6 g m5(1 k + ) 2g m3 r ds3 g ds5 + g ds6 ( + v ) 2 n + g ds6 g m5k 2g m3 r ds3 g ds5 + g ds6 ( v ) 2 n 23

25 Effect of external components on PSRR 24

26 Frequency response and compensation A two-stage scheme with poles in the same frequency range needs compensation. A single pole system is always stable. Strategy: Approach the single pole performance by splitting the two poles apart. 25

27 Miller capacitance moves p 1 at lower frequency. Shunt feedback moves p 2 at higher frequency. Small signal equivalent circuit for two-stage op-amp. v 0 v 1 (g 1 + sc 1 ) + (v 1 v 0 )sc c + g m1 v in = 0 v 0 (g 2 + sc 2 ) + (v 0 v 1 )sc c + g m2 v 1 = 0 [ ] v in = g m1 R 1 R 2 g m2 sc c 1+ sr 1 R 2 g m2 C c + s 2 R 1 R 2 C 1 C 2 + (C 1 + C 2 )C c 26

28 The circuit has two poles and a zero in the right half plane. p 1 1 R 1 R 2 g m2 C c p 2 g m2 C c C 1 C 2 + (C 1 + C 2 )C c z = g m2 C c since in practice C c > C 1, C c C 2, g m1 > 1/R 1, g m2 > 1/R 2 it results: p 1 << 1 R 1 C 1 p 2 g m2 C 2 >> 1 R 2 C 2 Assuming p 1 as dominant, the unity gain angular frequency is: 1 T = p 1 A 0 g m1 g m2 R 1 R 2 = g m1 R 1 R 2 g m2 C c C c 27

29 The locations of the second pole p 2 and of the zero with respect to T are derived by considering: p 2 T = g m2 C c g m1 C 2 for stability > 2 to 4 z T = g m2 g m1 The phase shift given by the zero is also negative and can worsen the phase margin. It must be located far from the unity gain frequency. 28

30 if C c > C 2 and g m2 > g m1 The right half-plane worsen the phase margin. In bipolar technology g m2 >> g m1 because the current in the second stage is normally higher than the one in the first stage. 29

31 In CMOS technology g m2 g m1 because they are proportional to the square root of I and W/L; moreover, the transconductance of the input pair must be high in order to reduce their thermal noise contribution. In real situations the obtainable phase margin does not guarantee stability. Eliminating the right half-plane zero: unity gain buffer zero nulling resistor unity gain current amplifier The zero is due to a signal feedforward to a point that is 180 out of phase. 30

32 Solution 1: Eliminate feedforward with source follower Disadvantages: Area Power dissipation Actually it creates a doublet in the feedback path. Potentially not stable. Alternative, a substrate emitter follower may be used. (The bipolar transistor is smaller and has higher g m.) 31

33 Solution 2: Zero nulling resistor The zero position is pushed away with a resistance in series with C c. v 0 v in 1+ sr ( z 1/ g m2 )C c A 0 1+ s p 1 1+ s p 2 32

34 The pole locations are close to the original. The zero is moved depending on R z. z = 1 ( 1/ g m2 R z )C c If R z = 1 / g m2 the zero is moved at infinity If R z > 1 / g m2 the zero is located in the left half-plane Implementation: 1 R z = 1 R n + 1 R p 33

35 1 W = k n R n L n ( V DD V 1 V ) Th,n 1 = k p R p W L p ( V 1 V SS V ) Th,p Choose (W/L) n and (W/L) p such that: W W k n = k p L L and: 1 W = k n R z L n Problem: Supply sensitivity. n ( V DD V ss V Th,n V ) Th,p Since the swing of the node 1 is A 2 less than the output swing, only one transistor with supply independent bias can be used. p 34

36 Solution 3: Unity gain current amplifier v 1 (g 1 + sc 1 ) + g m1 v in v 0 sc c = 0 v 0 (g 2 + sc 2 ) + g m2 v 1 + v 0 sc c = 0 35

37 Slew rate For large input signal: M1, M4 are off so the current I M7 discharges C c through M2. Assuming M5 able to drive the current request by C c, C L and I M6. SR = V = I M7 t C max c 36

38 M2, M5 are off so the current I M7 mirrored by M4 charges C c ; C L and C c are charged by I M6. The smaller of these two limits will hold: I M6 SR + = V + = SR + = V + t C max c + C t L max To have SR + = SR -, a condition can be: = I M7 C c I M7 C c = Since T = g m1 / C c, the SR is I M6 C c + C L SR = I M7 T = ( V GS1 V Th ) T g m1 For T = rad/s, (V GS1 - V Th ) = 300 mv, SR 75.4 V/s. 37

39 Single stage schemes High gain is get with a cascode scheme. Telescopic cascode Mirrored cascode Folded cascode 38

40 Telescopic cascode DC gain A 0 (g m r ds ) 2 low power consumption only one high impedance node: compensated with a capacitance load (if necessary) low output swing reference of the input close to the negative supply two bias lines (V B1, V B2 ) 5 transistors in series 39

41 Mirrored cascode optimum input common mode range only 4 transistors in series improved output swing speed of the mirror higher power consumption V outmax = V B1max + V GS4 - V sat V B1max = V DD - V sat - V GS4 V outmax = V DD - 2V sat V outmax = V GS7 + V sat 40

42 Conventional folded cascode 41

43 Modified folded cascode (improved output swing) 42

44 Two stage amplifier vs. single stage amplifier Two stages: Voltage gain less affected by resistive loading Maximum signal swing Less bussing of bias lines Requires an additional capacitor for frequency compensation More power consumption 43

45 Single stage: No need for additional compensation capacitor Lower power consumption Better CMRR Lower signal swing More bussing of bias lines 44

46 Class AB op-amps Class AB: a circuit which can have an output current which is larger than its DC quiescent current. Two stages amplifier with class AB second stage M6 and M7 act as a level shifter M8 and M9 act as a class AB push-pull amplifier A 2 = g m8 + g m9 g ds8 + g ds9 45

47 The quiescent current in the output stage is bias voltage and technological variation dependent. V DD = V GS8 + V GS6 + V GS9 neglecting the body effect: V DD = V Th,p + 2V Th,n + I 9 = 2 k n L W 6 I 6 + V DD V Th,p 2V Th,n 2 k n L W 2 k n L W 8 I k n L W Typically with V DD = 5 V the numerator is around 1.6 V; if it is assumed V DD = (5 ± 0.5) V and V Th = ± 200 mv, it results that the numerator can change from 0.7 V to 2.5 V; hence, I min = 0.3 I nom ; I max = 2.5 I nom k n 2 k n L W L W 9 6 I 6 9 I 9 46

48 Single stage class AB amplifier (only inverting) In the input pair M1 and M2 operate as source followers and drive the common gate stage M3 and M4. V B = V Th,n + V Th,p + V ov,n + V ov,p for V in = 0 I 1 = I 2 = I Bias for V in > 0 I out = K 8,9 I 1 - K 5,6 I 2 K 8,9 and K 5,6 mirror factors (assumed equal) 47

49 V B +V in = V GS2 +V GS4 = V Th,n +V Th,p + 2 k n W L k p W L 4 I 2 V B V in = V GS1 +V GS3 = V Th,n +V Th,p + 2 k n W L k p W L 1 I 1 It results: I out = K 8,9 (I 1 - I 2 ) = K 8,9 V B V in Until I 1 or I 2 goes to zero, for a larger V in, I out increases quadratically with V in. Small signal gain: A v = 2 G m r out 48

50 G m is the transconductance of the cross coupled input stage g ( m2 V in V ) A = g m4 V A V A = g m2 V in g m2 + g m4 I out = g m4 V A = g m2g m4 g m2 + g m4 V in = G m V in 49

51 Fully differential op-amps The use of fully differential paths in analog signal processing gives benefits on: PSRR dynamic range clock feedthrough cancellation Consider an integrator and its fully differential version: 50

52 Noise from the power supply and clock feedthrough are common mode signals. The output swing is doubled (V max+ - V max- = 2 V max ). Since the noise is unchanged, the dynamic range improves by 6 db. Single ended to differential and double ended to single ended converters are necessary Larger area More bussing of bias lines Common mode feedback is necessary 51

53 The SE/DE and DE/SE blocks increase the complexity and introduce noise. The differential approach is convenient if the differential processor contains more than 4 stages. The feedback around the op-amp control the difference of the input terminal voltages and not their mean value. In turn, there is no control on the output common mode voltage. 52

54 Fully differential two stage OTA 1st stage with gain: two 2nd stages with gain: A 1 = 1 2 g m1 A 2 = g m5 g ds1 + g ds 4 g ds5 + g ds6 53

55 Fully differential single stage OTA 54

56 COMMON MODE FEEDBACK continuous time sampled data Continuous-time common mode feedback 55

57 V B is such that M1 and M2 are in the linear region; (W/L) 1 = (W/L) 2 ; M1 and M2 are like the parallel of two voltage dependent resistances. W I 1 = µc ox ( V + V Th )V DS 1 L 2 V 2 DS 1 W I 2 = µc ox ( V V Th )V DS 1 L 2 V 2 DS 2 I out = I 1 + I 2 = 1 2 µc W ox L 3 ( V B V DS V ) 2 Th With a differential signal I out = cost With a common mode signal: if positive, I out increases if negative, I out decreases 56

58 Fully differential folded cascode with CMFB 57

59 Fully differential folded cascode with CMFB (2) 58

60 Problems: dynamic range linearity Compensation of the non-linearities of the n-channel and p- channel CMFB cell. 59

61 Sampled-data common mode feedback The common mode feedback operates on slowly variable signal. It can be implemented at discrete time intervals. The sampled data feedback is essential for low bias voltage and low power. linearity (mean value with capacitors) low power consumption no limitation to the dynamic range clock signal necessary clock feedthrough effect 60

62 Micro-power op-amps Required in battery operated systems (portable/wearable equipment: pocket calculators, PDA's, digital cameras, ; medical equipment: pace makers, hearing aids, ); Use of MOS transistors in weak inversion; Low current (< 10 A) low slew rate. g m = I D nv T g ds = I D A v = B g m1 g ds6 + g ds8 = B nv ( T n + ) p high dc gain (A v 60 db) 61

63 Dynamic biasing of the tail current Basic idea: Generate I 1 - I 2 and increase the current in the differential stage by k I 1 - I 2. 62

64 Since i 1 i 2 = g m (v in + v in ) g m = I D nv T I D = I B + ki 1 i 2 i 1 i 2 = ( I B + ki 1 i ) v in + v in 2 nv T The current increase becomes significant when: Typical performance: DC gain 95 db f t 130 khz SR 0.1 V/s I B 0.5 A 2.5 A I tot k v in + v in nv T > 1 63

65 Class AB single stage with dynamic biasing For maximum output swing V BIAS-p and V BIAS-n must be as close as possible to the supply voltages. 64

66 During the slewing the current source of the output cascodes can be pushed in the linear region, hence loosing the advantage of the AB operation. The problem is solved with the dynamic biasing: 65

67 Noise The noise of an operational amplifier is described with an input referred voltage source v n. The spectrum of v n is made of a white term and 1/f term. v n is due to the contributions, referred to the input, of the noise generators associated to all the transistors of the circuit (assumed uncorrelated). 66

68 Consider the input stage of a two stage op-amp. The output noise voltage is given by: 2 v n,out [ ] = g 2 m1 (v 2 n1 + v 2 n2 ) + g 2 m3 (v 2 n3 + v 2 n 4 ) 1 g ds2 + g ds4 2 67

69 We assume g m1 = g m2 ; g m3 = g m4 (we assume the noise source of M5 does not contribute) moreover since usually W 1 = W 2 ; L 1 = L 2 ; W 3 = W 4 ; L 3 = L 4 ; v 2 n1 = v2 n2 ; v2 n3 = v2 n4 ; if we refer v 2 n,out to the input, we get: 2 v n,out A = v n,in = v 2 n,out g 2 ds2 + g ds 4 g m1 ( ) 2 = 2 v n1 2 + g 2 m3 g v 2 2 n3 m1 The contribution of the active loads is reduced by the square of the ratio g m3 /g m1 It is worth to remember that g m = 2µC ox W L I v n 2 = 8kT + 3g m K F 1 2µC ox WL 1 f f 68

70 The attenuation by the factor (g m3 /g m1 ) 2 gives, for the white term: 2 v n,in,w = 2v 2 n1 1+ g m3 = 2v 2 n1 1+ µ ( W / L ) 3 3 g m1 µ ( 1 W / L) 1 and for the 1/f term: 2 K v n,in,1/ f = 2 F K 2 F3L 1 2 µ 1 C ox W 1 L 1 f K F1 L 3 Where K F1 and K F3 are the flicker noise coefficient for transistors M1 and M3. The white contribution of the active load is reduced by choosing (W/L) input >> (W/L) load. The 1/f noise contribution of the active load is reduced by choosing L input < L load. If the above conditions are satisfied the input noise is dominated by the input pair. 69

71 Cascode scheme: The noise is contributed by the input pair and the current sources of the cascode load. 2 v n,in = 2 v 2 n1 + g m4 g m1 2 2 v n 4 70

72 Folded cascode scheme: The noise contributed by the same source as in the cascode and by the current source M2. 2 v n,in = 2 v 2 n1 + g 2 m2 v 2 n2 + g 2 m5 2 v n5 g m1 g m1 71

73 Two stage op-amp: (feedforward + zero nulling comp.) The noise is modeled with two input referred noise sources: one at the input of the first stage and the other at the input of the second stage. 72

74 In the low frequency range the noise is dominated by v n1. In the high frequency range the noise is dominated by v n2. 73

75 Frequency response: The input referred noise generator is transmitted to the output as a conventional input signal The feedback network around the op-amp must be taken into account. One stage amplifier: The cutoff frequency is: p 1 = -g m /C 0 74

76 Power of noise: We consider only the white term. Single stage amplifier: 2 2 df = v n v n s / p 1 ( ) 8 3 kt 1 = g m1 df ( ) 2 = 1+ 2fC 0 / g m1 8 3 ( 1+ ) kt C 0 Two stage amplifier: we consider only the white term contributed by the noise source of the second stage v n2 ( ) = 21+ g m2 p 2 = C 1 + C 2 kt g m df = v n s / p 2 v n0 v 2 n0 = 4 3 ( 1+ ) C 1 kt + C 2 75

77 Layout Rules: Use poly connections only for voltage signals, never for currents, because the offset RI 15 mv. Minimize the line length, especially for lines connecting high impedance nodes. Use matched structure (necessary common centroid). Respect symmetries (even respect power devices). Only straight-line transistors. Separate (or shield) the input from the output line, to avoid feedback. Shield high impedance nodes to avoid noise injection from the power supply and the substrate. Regular shapes and layout oriented design. 76

78 Stacked layout: C sb = C db = C jb W (d + 2x j ) Structure A: C sb = 1 2 C db = C jb W 2 (d + 2x j ) Structure B: C sb = C db = C jb 2W 3 (d + 2x j ) Capacitances are further reduced if the diffusion area is shared between different transistors. 77

79 Key point: use of equal width transistors Transistors with arbitrary width are not allowed. Placement and routing: If we divide a transistor in an odd number of parallel transistors the resulting stack has the source on one side and the drain on the other side. If we divide a transistor in an even number of parts the resulting stack has source or drain on the two sides. 78

80 Example: Routing into stacks: use of comb connections or serpentine connections. 79

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82 Example: Fully differential folded cascode. 81

83 82