Pipeline Processors. MCA-304 : Advanced Computer Architecture by Dr. Sumit Mittal

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1 Pipeline Processors

2 Reservation Table Each functional evaluation can be represented using a diagram called Reservation Table (RT). It is the space-time diagram of a pipeline corresponding to one functional evaluation. X axis time units Y axis stages Columns represent the evaluation time for a given function Multiple checkmarks in a row, means repeated usage of the same stage in different cycles

3 Reservation Table For first sequence Sa, Sb, Sc, Sb, Sc, Sa called function A, we have Sa A A Sb A A Sc A A

4 Reservation Table For second sequence Sa, Sc, Sb, Sa, Sb, Sc called function B, we have Sa B B Sb B B Sc B B

5 3-Stage Non-Linear Pipeline Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa Sb Sc

6 Function A

7 3-Stage Pipeline : Sa, Sb, Sc, Sb, Sc, Sa Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa Sb Sc A

8 3-Stage Pipeline : Sa, Sb, Sc, Sb, Sc, Sa Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa Sb Sc A A

9 3-Stage Pipeline : Sa, Sb, Sc, Sb, Sc, Sa Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa Sb Sc A A A

10 3-Stage Pipeline : Sa, Sb, Sc, Sb, Sc, Sa Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa A Sb A A Sc A

11 3-Stage Pipeline : Sa, Sb, Sc, Sb, Sc, Sa Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa A Sb A A Sc A A

12 3-Stage Pipeline : Sa, Sb, Sc, Sb, Sc, Sa Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa A A Sb A A Sc A A

13 Function B

14 3-Stage Pipeline: Sa, Sc, Sb, Sa, Sb, Sc Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa Sb Sc B

15 3-Stage Pipeline: Sa, Sc, Sb, Sa, Sb, Sc Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa Sb Sc B B

16 3-Stage Pipeline: Sa, Sc, Sb, Sa, Sb, Sc Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa B Sb B Sc B

17 3-Stage Pipeline: Sa, Sc, Sb, Sa, Sb, Sc Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa B B Sb B Sc B

18 3-Stage Pipeline: Sa, Sc, Sb, Sa, Sb, Sc Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa B B Sb B B Sc B

19 3-Stage Pipeline: Sa, Sc, Sb, Sa, Sb, Sc Output A Input Sa Sb Sc Output B Time Reservation Table Stage Sa B B Sb B B Sc B B

20 Latency Analysis Latency: The number of time units (clock cycles) between two initiations of a pipeline is the latency between them. A latency value k means that two initiations are separated by k clock cycles. Collision: An attempt by two or more initiations to use the same pipeline stage at the same time. Collision implies resource conflicts b/w two initiations in the pipeline. Some latencies cause collision, some not. Latencies that will cause collision are called Forbidden Latencies and the latencies that will not cause collision are called Permissible Latencies.

21 Latency Cycles A latency sequence is a sequence of permissible nonforbidden latencies between successive task initiations. A latency cycle is a latency sequence which repeats the same subsequence indefinitely.

22 Latency Cycle x 1 x 1 x 2 x 1 x 2 x 3 x 2 x 3 x 1 x 1 x 2 x 3 x 1 x 1 x 1 x 2 x 2 x 2 x 2 x 3 x 3 x 3 Cycle Cycle A latency sequence is a sequence of permissible nonforbidden latencies between successive task initiations. A latency cycle is a latency sequence which repeats the same subsequence indefinitely.

23 Example X Y S1 S2 S3

24 Reservation Tables for X & Y S1 S2 S3 X X X X X X X X S1 S2 S3 Y Y Y Y Y Y

25 Forbidden Latencies To detect the forbidden latencies, check the distance between two checkmarks in the same row of the reservation table.

26 X after X S1 S2 S3 X X X X X X X X 2 S1 S2 S3 X1 X2 X1 X2 X1 X1 X2 X1 X2 X1 X2 X1 X2 X1

27 X after X S1 S2 S3 X X X X X X X X 5 S1 S2 S3 X1 X2 X1 X1 X1 X1 X2 X1 X1 X1 X2

28 X after X S1 S2 S3 X X X X X X X X 4 S1 S2 S3 X1 X2 X1 X1 X1 X1 X2 X2 X1 X1 X2 X1

29 X after X S1 S2 S3 X X X X X X X X 7 S1 X1 X1 X2 X1 S2 S3 X1 X1 X1 X1 X1

30 Collision Vector Combined set of permissible and forbidden latencies. Forbidden Latencies: 2, 4, 5, 7 Collision vector C = (C m, C m-1,, C 2, C 1 ), m <= n-1 n = number of column in reservation table The value of Ci = 1 if the latency i causes a collision; Ci = 0 if the latency i is permissible. Collision Vector =

31 Y after Y S1 S2 S3 Y Y Y Y Y Y Y Y Y Y S1 S2 S3 Y Y Y Y Y Y Y Y

32 Y after Y S1 S2 S3 Y Y Y Y Y Y Y Y Y Y S1 S2 S3 Y Y Y Y Y Y Y Y

33 Collision Vector Forbidden Latencies: 2, 4 Collision vector C = (C m, C m-1,, C 2, C 1 ), m <= n-1 n = number of column in reservation table C i = 1 if latency i causes collision, 0 otherwise Collision Vector =

34 Collision Vector Reservation Table x x x x x x C = (??...??)

35 Exercise Find the collision vector A X X X B X X C X X D X

36 State Diagram State diagrams can be constructed to specify the permissible transitions among successive initiations. The collision vector, corresponding to the initial state of pipeline at time 1, is called the initial collision vector (ICV).

State Diagram The next state of the pipeline at time t+p can be obtained by using a bit-right shift register Initial CV is loaded into the register. The register is then shifted to the right.

37 State Diagram The next state of the pipeline at time t+p can be obtained by using a bit-right shift register Initial CV is loaded into the register. The register is then shifted to the right. When a 0 emerges from the right end after p shifts, p is a permissible latency. When a 1 emerges, the corresponding latency should be forbidden latency. Logical 0 enters from the left end of the shift register. The next state after p shifts is obtained by bitwise-oring the initial CV with the shifted register contents.

38 Right Shift Register The next state can be obtained with the help of an p-bit shift register 0 latency. 1 Collision 0 Safe to allow an initiation Each 1-bit shift corresponds to increase in the latency by 1.

39 The Next State The next state is obtained by bitwise ORing the initial collision vector with the shifted register C.V. = (first state) C.V. 1-bit right shifted initial C.V OR

40 State Diagram for X * 6

41 Group Activity S1 X X S2 S3 X X a. What are the forbidden latency? b. Draw the state transition diagram. c. List all the simple cycles and greedy cycles. d. Determine the minimal average latency (MAL). e. Determine the throughput of this pipeline.

CS521 CSE IITG 11/23/2012

CS521 CSE IITG 11/23/2012 CS521 CSE TG 11/23/2012 A Sahu 1 Degree of overlap Serial, Overlapped, d, Super pipelined/superscalar Depth Shallow, Deep Structure Linear, Non linear Scheduling of operations Static, Dynamic A Sahu slide