Interconnection Network Design

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1 Interconnection Network Design Vida Vukašinović 1 Introduction Parallel computer networks are interesting topic, but they are also difficult to understand in an overall sense. The topological structure of these networks has elegant mathematical properties, and there are deep relationships between these topologies and the fundamental communication patterns of important parallel algorithms. In this paper we would like to provide a holistic understanding of parallel computer networks and its topologies. Basic Definitions We would firstly provide a set of basic definitions that underlie all networks. Formally, a parallel machine interconnection network is a graph, where the vertices V are processing hosts or switch elements connected by communication channels C V V. A channel is a physical link between host or switch elements, including a buffer 1 to hold data as it is being transferred. It has a width w and a signaling rate f = 1 τ (for cycle time τ), which together determine the channel bandwidth b = wf. The amount of data transferred across a link in a cycle is called a physical unit, or phit. Switches connect a fixed number of input channels to a fixed number of output channels. This number is called the switch degree. Hosts typically connect to a single switch but can be multiply connected with separate channels. Massages are transferred through the network from a source host node to a destination host node along a path, or route, comprised of a sequence of channels and switches. A network is characterized by its topology, routing algorithm, switching strategies and flow control mechanism. The topology is the physical interconnection structure of the network graph. The routing algorithm determines which routes messages may follow through the network graph. In a parallel machine, we are only concerned with the routes from a host to a host. The routing algorithms restricts the set of possible paths to a smaller set of legal paths. There are many different routing algorithms which are offering different performance tradeoffs. The switching strategy determines how the data in a message traverses its route. There are basically two switching strategies. In circuit switching, the path from the source to the destination is established and reserved until the message is transferred over the circuit. In packet switching the message is broken into a sequence of packets. Each packet contains routing and sequencing information as well as data. Packets are individually routed from the source to the destination. 1 Buffer is a temporary location to store or group information in hardware or software. Buffers are used whenever data is received in sizes that may be different than ideal size. Bandwidth refers to how much data is transmitted over a given period of time. It is measured in bits per second in digital devices and in Hertz in analog devices. 1

3 Figure : Store-and-forward and cut-through routing for packet-switched networks. A four-flit packet traverses three hops from source to destination under store-and-forward and cut-through routing. Cut-through achieves lower latency by making the routing decision (gray arrow) on the first flit and pipelining the packet through a sequence of switches. Store-and-forward accumulates the entire packet before routing it toward the destination. where b is the raw bandwidth of channel and is the additional routing delay per hop. With circuit switching, we expect a delay proportional to h to establish the circuit. After this time, the data should move along the circuit in time n b plus an additional small delay proportional to h. Thus, the unloaded latency in units of the network cycle time τ for an n-byte message traveling distance h in a circuit-switched network is T CS (n, h) = n b + h. In this case, the setup and routing delay is independent of the size of the message. Thus, Circuit switching is traditionally used in telecommunications networks since the call setup is short compared to the duration of the call. It is also possible to retain packet switching and reduce the unloaded latency from that storeand-forward routing, where the delay is the product of the routing distance and the occupancy for the full message. A long message can be fragmented into several small packets, which flow through the network in a pipelined fashion. In this case the effective routing delay is proportional to the pocket size rather than the message size. This is the approach adopted for traditional data communication networks such as the internet. In parallel computer networks, the idea of pipelining the routing is carried much further. With packet switched, cut-through routing, the switch makes its routing decision after inspecting only the first few phits of the header and allows the remainder of the packet to cut-through from the input channel to the output channel, as indicated by Figure. In this case, the transmission of even a single pocket is pipelined. For cut-through routing, the unloaded latency has a form similar to the circuit switch case, although the routing coefficient may differ. T ct (n, h) = n b + h With cut-through routing a single message may occupy the entire route from the source to the destination, much like circuit switching. The head of the message establishes the route as it moves toward its destination, and the route clears as the tail moves through. Of course, the reason that networks are so interesting is that they are not simple pipeline but a big system of many pipelines. The whole motivation for using a network rather than bus is to allow multiple data transfers to occur simultaneously. This means that one message flow 3

7 degraded performance in the presence of a single fault link. the network is easily laid out with O(N) space using only short wires, as indicated by Figure 4. Figure 4: Linear and ring topologies. Although these one-dimensional networks are not scalable in any practical sense, they are an important building blocks conceptually and in practice. 5.3 Multidimensional Meshes and Tori A d-dimensional array consists of N = k d 1 k d... k 0 nodes, each identified by its d-vector of coordinates (i d 1, i d..., i 0 ), where 0 i j k j 1 for 0 j d 1. Figure 5 shows the common cases of two and three dimensions. For simplicity we will assume the length along each dimension is the same, so N = k d (k = d N). This is called a d-dimensional k-ary mesh. Each node is a switch addressed by a d-vector of radix k coordinates and is connected to the nodes that differ by one in precisely one coordinate. The node degree varies between d and d (nodes in the middle have full degree and the corners have minimal degree). Figure 5: Mesh, torus and cube topologies. For a d-dimensional k-ary torus, every node has degree d (in the bidirectional case) and is connected to nodes differing by one (mod k) in each dimension. The d-dimensional k-ary unidirectional torus is a very important class of networks, often called a k-ary d-cube, employed widely in modern parallel machines. To define the routes from node A to node B in a d-dimensional array, let R = (b d 1 a d 1, b d a d,..., b 0 a 0 ) be the relative address of B from A. A route must cross r i = b i a i links in each dimension i, where the sign specifies the appropriate direction. In general, we may view the source and destination points as corners of subarray and follow any path between the corners that reduces the relative address from the destination at each hop. The diameter of the mesh is d(k 1). The average distance is simply the average distance in each dimension, roughly d 3k. If k is even, the bisection of a d-dimensional k-ary array is kd 1 bidirectional links. This is obtained by simply cutting the array in the middle by a (hyper)plane perpendicular to one of the dimensions. (If k is odd, the bisection may be a little bit larger.) It is clear that a two-dimensional mesh can be laid out with O(N) space in a plane with short wires and three-dimensional mesh in O(N) volume in free space. 5.4 Trees In meshes, the diameter and average distance increases with the dth root of N. Many other topologies exist where the routing distance grows only logarithmically. The simplest of these is a tree. A binary tree has degree 3. Typically, trees are employed as indirect networks with hosts as the leaves, so for N leaves the diameter is log N. In this case, we may treat the binary address of each node as a d = log N bit vector specifying a path from the root and so on down the levels of 7

9 Figure 7: Butterfly. The butterfly appears to be a qualitatively more scalable network than meshes and trees because each packet crosses log N links and there are N log N links in the network, so on average it should be possible for all the nodes to send messages anywhere all at once. The second problem is that even though the butterfly is thought to have enough links, the topology of the butterfly will not allow an arbitrary permutation of N messages among the N nodes to be routed without conflict. A path from an input to an output blocks the paths of many other input/output pairs because there are shared edges. However, if two butterflies are laid back to back so that a message goes forward through one and in the reverse direction through the other, then for any permutation there exists a choice of intermediate positions that allows a conflict-free routing of the permutation. This back-to-back butterfly is called a Benes network (Benes 1965; Leighton 199) and it has been extensively studied because of its elegant theoretical properties. It is often seen as having little practical significance because it is costly to compute the intermediate positions and permutations has to be known in advance. On the other hand, there is another interesting theoretical result that says that on a butterfly any permutation can be routed with high probability by first sending every message to a random intermediate node and then routing the messages to the desired destination (Leighton 199). These two results come together in a very nice practical way in the fat-tree network. Figure 8: Benes network and fat-tree. A d-dimensional k-ary fat-tree is formed by taking a d-dimensional k-ary Benes network and folding it back on itself at the high-order dimension, as illustrated in Figure 7. The collection of 9

11 significant cost factor. However, with cut-through routing and a more realistic hardware cost model, the choice is much less clear. If the number of links or the switch degree is the dominant cost, we would minimize the dimension and built a mesh. The assumed communication pattern influences the decision too. If we look at the worst case traffic pattern, we will prefer high dimensional networks where essentially all the paths are short. If we look at patterns where each node is communicating with only one or two near neighbors, we will prefer low dimensional networks since only few of the dimensions are actually used. Basically, as with most aspect of architecture, we have to define the cost model and performance model and then optimize the design accordingly. References [1] D. E. Culler, J. P. Singh, A. Gupta, Parallel Computer Architecture, MK, San Francisco, California,

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