Fixed-Point Numbers. Positional representation: k whole and l fractional digits. x x 1. x k 2. . x 1
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1 Fied-Point Numbers Positional representation: k whole and l fractional digits Value of a number: = ( k 1 k l ) r = Σ i r i For eample: = (10.011) two = (1 2 1 ) + (0 2 0 ) + (0 2 1 ) + (1 2 2 ) + (1 2 3 ) Numbers in the range [0, r k ulp] representable, where ulp = r l Fied-point arithmetic same as integer arithmetic Two s complement properties (including sign change) hold here as well: (01.011) 2 s-compl = ( ) + (1 2 0 ) + (0 2 1 ) + (1 2 2 ) + (1 2 3 ) = (11.011) 2 s-compl = ( ) + (1 2 0 ) + (0 2 1 ) + (1 2 2 ) + (1 2 3 ) = EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 1/22 Radi Conversion for Fied-Point Numbers Convert the whole and fractional parts separatel. To convert the fractional part from an old radi r to a new radi R: Perform arithmetic in the new radi R Evaluate a polnomial in r 1 : (.011) two = Simpler: View the fractional part as integer, convert, divide b r l (.011) two = (?) ten Multipl b 8 to make the number an integer: (011) two = (3) ten Thus, (.011) two = (3 / 8) ten = (.375) ten Perform arithmetic in the old radi r Multipl the given fraction b R, use the whole part as the MSD and the fractional part to repeat the process (.72) ten = (?) two = 1.44, so the answer begins with = 0.88, so the answer begins with 0.10 EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 2/22 1
2 Floating-Point Numbers Useful for applications where ver large and ver small numbers are needed simultaneousl Fied-point representation is not ver good for dealing with ver large and etremel small #s simultaneousl = ( ) two Small number = ( ) two Large number Neither 2 nor / is representable in the format above Floating-point representation is like scientific notation: = = Significand Eponent base Eponent Also, 7E 9 EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 3/22 ANSI/IEEE Stand. Floating-Point Format (IEEE754) Revision (IEEE ) is available. 8 bits, bias = 127, 126 to 127 Short (32-bit) format 23 bits for fractional part (plus hidden 1 in integer part) Short eponent range is 127 to 128 but the two etreme values are reserved for special operands (similarl for the long format) Sign Eponent 11 bits, bias = 1023, 1022 to 1023 Significand 52 bits for fractional part (plus hidden 1 in integer part) Long (64-bit) format Two ANSI/IEEE standard floating-point formats. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 4/22 2
3 Short and Long IEEE 754 Formats: Features Some features of ANSI/IEEE standard floating-point formats Feature Single/Short Double/Long Word width in bits Significand in bits hidden hidden Significand range [1, ] [1, ] Eponent bits 8 11 Eponent bias Zero (±0) e + bias = 0, f = 0 e + bias = 0, f = 0 Denormal e + bias = 0, f 0 represents ±0.f e + bias = 0, f 0 represents ±0.f Infinit (± ) e + bias = 255, f = 0 e + bias = 2047, f = 0 Not-a-number (NaN) e + bias = 255, f 0 e + bias = 2047, f 0 Ordinar number e + bias [1, 254] e [ 126, 127] represents 1.f 2 e e + bias [1, 2046] e [ 1022, 1023] represents 1.f 2 e min ma EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 5/22 Simple Adders Inputs Outputs c s c s HA Inputs Outputs c in c out s c out FA Binar half-adder (HA) and full-adder (FA). s c in S = c in C out = c in + + c in EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 6/22 3
4 Ripple-Carr Adder: Slow But Simple c 32 c out c 31 c 2 c 1 FA... FA FA Critical path s 31 s 1 s 0 c 0 c in Ripple-carr binar adder with 32-bit inputs and output. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 7/22 Carr Propagation EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 8/22 4
5 Carr Look-Ahead Adder uses the concepts of generating and propagating carries C i+1 = i i +c i ( i + i ), i i = g i, i + i =p i Carr Bpass (=skip) Adder -Looks for cases in which carr out of a set of bits is identical to carr in EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 9/22 Design of Fast Adders Carr Select Adder -Don t know carr in: so do both -Use MUX to select the right sum Carr Save Adder -produce the sum and carr bits separatel and add them at the end = (21+4) = 25, = (25+12) = 37 EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 10/22 5
6 Combined Addition/ Subtraction I. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 11/22 Two s-complement Addition and Subtraction k / c in Adder k / ± k / Add Sub k / or c out Binar adder used as 2 s-complement adder/subtractor. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 12/22 6
7 Combined Addition/ Subtraction II. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 13/22 Combined Addition/Subtraction II. - 4 FAs, 4 XORs, 1 etra control bit. Note: Combined Addition/Subtraction I. - 4 FAs, 8 ANDs, 4 ORs, 2 etra control bits EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 14/22 7
8 Magnitude Comparator EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 15/22 A3=B3? X3A2 B2 EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 16/22 8
9 Binar Multiplier EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 17/22 EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 18/22 9
10 Multiplicand Multiplier Partial products bit-matri Product Shift-Add Multiplication Multiplication of 4-bit numbers in dot notation z EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 19/22 Binar and Decimal Multiplication Eample Position Position z (0) z (0) z (1) z (1) z (1) z (1) z (2) z (2) z (2) z (2) z (3) z (3) z (3) z (3) z (4) z (4) z (4) z (4) Step-b-step multiplication eamples for 4-digit unsigned numbers. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 20/22 10
11 Two s-complement Multiplication Eample Position Position z (0) z (0) z (1) z (1) z (1) z (1) z (2) z (2) z (2) z (2) z (3) z (3) z (3) z (3) ( ) ( ) z (4) z (4) z (4) z (4) Step-b-step multiplication eamples for 2 s-complement numbers. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 21/22 Hardware Multipliers Shift Multiplier Doublewidth partial product z (j) Shift Multiplicand 0 1 Mu Enable Select j c out Adder c in Add Sub Hardware multiplier based on the shift-add algorithm. EE800-lec03_part1 (2010) The Arithmetic/Logic Unit 22/22 11
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