EE 382M VLSI II: Advanced Circuit Design I/O & ESD Design

Transcription

1 EE 382M VLSI II: Advanced Circuit Design I/O & ESD Design Byron Krauter, IBM EE382M VLSI-II Class Notes Foil # 1

2 Outline Logic Requirements Other Complications Transmission Line Behavior Basic CMOS I/O and Receiver Design Actual CMOS I/O and Receiver Design Impedance Matching & Slew Rate Control Mixed Voltages ESD and other extreme conditions Increasing Bandwidth Source Synchronous I/O or Co-transmitted Clock Pipelined Bus or Bus Pumping Dual Data Rate Simultaneous Bi-Directional Pattern Based Driver Compensation EE382M VLSI-II Class Notes Foil # 2 2

3 Logic Requirements EE382M VLSI-II Class Notes Foil # 3

4 Logic Requirements Send 1 s and 0 s chip to chip Can be accomplished with simple inverters?? Chip A Chip B EE382M VLSI-II Class Notes Foil # 4 4

5 Complications Pin Count Limitations Bi-directional signaling Simultaneous switching noise Transmission Line Behavior Limited net topologies work Terminations required Skin effect Dielectric loss Other Noises Reflections Discontinuity noise Crosstalk and connector noise Mixed Voltages ESD and Other Handling Complications EE382M VLSI-II Class Notes Foil # 5 5

6 Transmission Line Behavior EE382M VLSI-II Class Notes Foil # 6

7 But First A Few Words on Common Ground Interconnect Models EE382M VLSI-II Class Notes Foil # 7

8 Example - Two Wires & One Source Twin lead transmission line modeled as a single section and driven by a Thevenin source R source L 11 R wire 0.5*C wire M *C wire L 22 R wire EE382M VLSI-II Class Notes Foil # 8

9 Example - Two Wires & One Source Being concerned with local potentials only (i.e. capacitor potentials) inductances and resistances can be combined R source L 11 R wire L 22 R wire 0.5*C wire M *C wire R source L 11 + L 22-2*M *C wire 2*R wire 0.5*C wire EE382M VLSI-II Class Notes Foil # 9

10 Example - Three Wires & Two Sources When multiple wires form a cutset, treat one wire as a reference lead and fold it into the other wires*. R s1 L 11 R 1 Cutset 0.5*C 1g M 1g 0.5*C 1g R g 0.5*C *C 12 M *C 2g L gg M 2g 0.5*C 2g R s2 L 22 R 2 * Brian Young, Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages EE382M VLSI-II Class Notes Foil # 10

11 Example - Three Wires & Two Sources Resulting loop impedance model for three parallel wires driven by two Thevenin sources mutual resistances R s1 L 11 +L gg -2M 1g R 1 +R g v 1 i 2 R g 0.5*C 1g M 12 -M 1g -M 2g +L gg 0.5*C 1g 0.5*C 12 v 2 0.5*C 12 i 1 R g R s2 0.5*C 1g L 22 +L gg -2M 1g R 2 +R g 0.5*C 2g EE382M VLSI-II Class Notes Foil # 11

12 Transmission Line Behavior On and off chip signals can always be modeled with lumped RLC circuits Wire segments are modeled with π or t segments L, R, C, and G can be frequency dependent But inductance is not always important EE382M VLSI-II Class Notes Foil # 12

13 Transmission Line Behavior Inductance is important when Driver source impedance R s is low R s < Z o where Z o = characteristic impedance of line Driver rise time τ r Line loss is low is fast τ r < 2.5 τ f where τ f = time of flight R << jωl or (R / 2Z o ) << 1 Can be restated for point to point nets as R s C tot < 1/2 R line C line < τ f Wave front decays exponentially with this constant EE382M VLSI-II Class Notes Foil # 13 13

14 When Inductance is Important Nets ring and net delays become unpredictable unless: Net topologies are constrained Point to point nets Periodically loaded nets Near and far end clusters Nets are driven appropriately Not to strong and not to weak Not to fast and not to slow Nets are terminated appropriately Source termination Far end termination Resistance to Vdd or Gnd or any Thevenin Voltage AC termination = RC circuit Active hold clamps Diode or Schottky diode clamps EE382M VLSI-II Class Notes Foil # 14 14

15 Transmission Line Behavior Perfectly source terminated point to point, loss-less net R s = Z o τ f Z o = L C τ f = LC far end V(t) τ f EE382M VLSI-II Class Notes Foil # 15 near end time 15

16 Transmission Line Behavior Under driven point to point, loss-less net R s = 3Z o τ f Z o = L C τ f = LC far end Approximates RC step response V(t) EE382M VLSI-II Class Notes Foil # 16 near end time 16

17 Transmission Line Behavior Over driven point to point, loss-less net R s = 1/3 Z o τ f Z o = L C τ f = LC far end V(t) EE382M VLSI-II Class Notes Foil # 17 near end time 17

18 Reflection and Transmission With incident wave V inc traveling down the line Voltage reflection coefficient Γ v = Z L -Z o Z L + Z o Γ v = 1, Z L = 0, Z L = Z o -1, Z L = 0 Voltage transmission coefficient Τ v = 1 + Γ v = 2Z L Z L + Z o EE382M VLSI-II Class Notes Foil # 18 18

19 Equivalent Circuits Along Line V s R s near end Z o + V inc - Z o along line 2V inc Z o Z discontinuity Z o far end 2V inc Z L EE382M VLSI-II Class Notes Foil # 19 19

20 Discontinuities Along Line R s = Z o 1 V s =1 V s C 1/2 1/2 (1- e -2t/ZoC ) R s = Z o 1 V s =1 V s L 1/2 1-1/2(1- e -2Zot/L ) EE382M VLSI-II Class Notes Foil # 20 20

21 Point to Point Nets Well Behaved Net Topologies R s = Z o τ f Source terminated R s << Z o τ f Far end terminated R term Z o V term EE382M VLSI-II Class Notes Foil # 21 21

22 Well Behaved Net Topologies Periodically Loaded Nets Source terminated: Near end switches last R s = Z eff C L C L C L C L With periodic loading Z eff = L C + nc L τ f = L(C+nC L ) EE382M VLSI-II Class Notes Foil # 22 22

23 Well Behaved Net Topologies Periodically Loaded Nets Far end terminated: Near end switches first R s << Z eff R term Z eff V term C L C L C L C L With periodic loading Z eff = L C + nc L τ f = L(C+nC L ) EE382M VLSI-II Class Notes Foil # 23 23

24 Well Behaved Net Topologies Near end (or Star) cluster R s = Z o /N EE382M VLSI-II Class Notes Foil # 24 24

25 Far-end cluster Well Behaved Net Topologies R s = Z o /N Z o /N EE382M VLSI-II Class Notes Foil # 25 25

26 Well Behaved Net Topologies Double far-end terminated bus R s << Z o V term V term C L C L C L C L C L EE382M VLSI-II Class Notes Foil # 26 26

27 EE382M VLSI-II Class Notes Foil # 27 Ideal Transmission Lines 27 γ = Z = L C ω LC I(z) V(z) t i L z V t V C z i = = t V LC z V = Steady State Solution: ]) V [V 1 ( Re I ] V [V Re V ) ( ) ( ) ( ) ( e e e e t z j t z j t z j t z j Z ω γ ω γ ω γ ω γ = + = where Ideal Telegrapher s Equation

28 Transmission Lines with Loss Z(ω) = Z( ω) = Z jωl + R jωc EE382M VLSI-II Class Notes Foil # 28 j γ (ω) = (jωl + R) jωc L C (1 - j R/2ω L) jω LC (1 - j R/2ω L) R R j γ ( ω) = ω LC + 2ω C Z 2 Z

29 Waveforms Along a Low Loss Line R s << Z o V s τ f where τ f = length / velocity With complex impedance & complex propagation constant high speed wavefront decays exponentially & distorts 1 (1- e -R*length/2Zo ) EE382M VLSI-II Class Notes Foil # 29 29

30 Distortionless Transmission Line Oliver Heaviside (1887) G / C = R / L Z(ω) = = L C jωl + R jωc + G j γ (ω) = (jωl + R)(jωC + G) = LC ( jω + R /L) EE382M VLSI-II Class Notes Foil # 30 30

31 Waveforms Along a Distortionless Line R s << Z o V s τ f where τ f = length / velocity With real impedance and complex propagation constant high speed wavefront decays exponentially but without distortion 1 (1- e -R*length/Zo ) EE382M VLSI-II Class Notes Foil # 31 31

32 Basic CMOS I/O and Receiver Design EE382M VLSI-II Class Notes Foil # 32

33 Bidirection CMOS I/O Buffer enable data Pad data 0 1 enable Hi Z 1 Hi Z EE382M VLSI-II Class Notes Foil # 33 33

34 CMOS I/O Receiver Any two input gate that Has good noise immunity Provides on-chip control when off-chip inputs float Example: two input nand data Pad enable out data 0 1 enable X 1 X EE382M VLSI-II Class Notes Foil # 34 34

35 Actual CMOS I/O and Receiver Design EE382M VLSI-II Class Notes Foil # 35

36 Actual CMOS I/O Design Output Impedance Control Slew Rate Control Mixed Voltage Designs Input Design for Higher Voltages Output Design for Higher Voltages Dual Power Supplies Floating Well Designs Open Source Signaling Other Circuits Differential I/O Circuits Hysteresis Receivers ESD Circuits EE382M VLSI-II Class Notes Foil # 36 36

37 Output Impedance Control Device resistances are too variable for source termination Devices are non-linear Variations due to Vdd, Temp, and process variations alone are >2X in linear region! Output stages must be designed to reduce this variation On-chip resistors designs Logically tunable designs EE382M VLSI-II Class Notes Foil # 37 37

38 Impedance Control Using On-Chip Resistors Given a precise on-chip resistor, this design provides the best impedance control enable data Pad EE382M VLSI-II Class Notes Foil # 38 38

39 Tunable Impedance Control Stacked device settings can be preset or dynamically controlled p1 p2 p3 enable data Pad n1 n2 n3 EE382M VLSI-II Class Notes Foil # 39 39

40 Slew Rate Control Output stage slew rate is controlled to reduce noise Cross talk noise Simultaneous switching noise Reflections at discontinuities Slew rate control is accomplished by controlling the predriver delay and/or pre-driver strength EE382M VLSI-II Class Notes Foil # 40 40

41 Slew Rate Control Output stage is divided and pre-drive signal is designed to sequentially arrive at the different sections δ δ enable data Pad δ δ EE382M VLSI-II Class Notes Foil # 41 41

42 Slew Rate Control & Impedance Control Pre-driver design might even permit crossover currents to guarantee impedance even during switching δ δ enable data Pad δ δ EE382M VLSI-II Class Notes Foil # 42 42

43 Feedback Slew Rate Control I/O Buffer enable Pad data (Motorola 68332, McDermott, Carter) EE382M VLSI-II Class Notes Foil # 43

44 Mixed Voltage Designs Needed when chips have different supply voltages Low voltage circuits can be damaged by high voltage inputs High voltage circuits suffer delay & noise problems when receiving low voltage signals Vdd1 Bi-directional I/O Buffers Vdd2 newer technology older technology Vdd1 < Vdd2 EE382M VLSI-II Class Notes Foil # 44 44

45 Input Design for Higher Voltages Modifications for gate oxide & ESD protection Receiving Same Level Receiving Higher Level Pad ESD Diodes Pad ESD Diodes EE382M VLSI-II Class Notes Foil # 45 change beta ratio 45

46 Pass Gate Behavior nfet and pfet pass gates can be used to limit voltages 0 V dd V 1 V 1 -V tn V dd V 1 0 V 1 -V tp EE382M VLSI-II Class Notes Foil # 46 46

47 Dual Supply Designs Separately power I/O circuits at a lower voltage No additional process steps required Extra design to avoid performance penalty ESD & simultaneous switching noise compromised Vdd1 Bi-directional I/O Buffers Vdd1 Vdd2 newer technology older technology EE382M VLSI-II Class Notes Foil # 47 47

48 Output Stage at a Lower Voltage Slow rising delay due to low overdrive on pfet Reduced drive = reduced noise immunity on nand receiver Vdd2 Vdd1 Vdd1 or Vdd2 enable data ESD Diodes Pad inhibit EE382M VLSI-II Class Notes Foil # 48 48

49 Output Stage at a Lower Voltage Improve rising delay with nfet pull up Change p/n beta ratio on nand to lower switch point 1.8 Volts 1.2 Volts 1.2 or 1.8 Volts enable data ESD Diodes Pad inhibit change beta ratio EE382M VLSI-II Class Notes Foil # 49 49

50 Dual Supply Designs Separately power the I/O circuits at a higher voltage More complicated circuits ESD & simultaneous switching noise compromised 1.2 Volts 1.8 Volts Bi-directional newer technology I/O Buffers 1.8 Volts older technology EE382M VLSI-II Class Notes Foil # 50 50

51 Output Stage at a Higher Voltage Slow rising delay due to low overdrive on pfet Reduced drive = reduced noise immunity on nand receiver Vdd2 Vdd1 Level Shifter Vdd2 enable data Vbias Pad Vdd1 EE382M VLSI-II Class Notes Foil # 51 51

52 Floating Well Designs Enabled output stage sends lower voltage - Vdd1 Disabled output stage tolerates higher voltage - Vdd2 Vdd1 Vdd1 enable data Vdd1 Pad Vdd1 EE382M VLSI-II Class Notes Foil # 52 52

53 Open Drain Signaling Avoids complexity of multiple chip power supplies Off-chip termination resistors pull net up On-chip nfet devices pull net down Increases transmission line design complexity Wired OR functionality Driving Chip V tt V tt C L C L C L C L C L EE382M VLSI-II Class Notes Foil # 53 53

54 Other Circuits Differential I/O Circuits Reduces simultaneous switching noise Improves receiver common mode noise immunity Receives smaller signal levels Pseudo to full differential possible Hysteresis Receivers High noise immunity Excellent for low-speed asynchronous test & control signals Hold Clamps EE382M VLSI-II Class Notes Foil # 54 54

55 Differential Output Buffers Pseudo Differential Outputs out out Differential Outputs Vdd out out Vbias EE382M VLSI-II Class Notes Foil # 55 55

56 Differential Transmission Lines Pseudo = two lines Z o Z o Differential = coupled pair coupled Z eff < Z o Z eff < Z o EE382M VLSI-II Class Notes Foil # 56 56

57 Differential Far End Termination Pseudo Differential Termination V tt R= Z o V tt R= Z o Differential Termination R = 2 Z o EE382M VLSI-II Class Notes Foil # 57 57

58 Differential Receivers Pseudo Differential Receiver out out Differential Receiver Vdd out out Vbias EE382M VLSI-II Class Notes Foil # 58 58

59 Self Biased Differential Receiver Combines best of nfet and pfet differential receivers Vdd Vdd P bias out out out out N bias EE382M VLSI-II Class Notes Foil # 59 59

60 Self Biased Differential Receiver Combines best of nfet and pfet differential receivers Rail to rail output swing Excellent common mode noise rejection Vdd out or reference (Bazes, JSSC 91) EE382M VLSI-II Class Notes Foil # 60 60

61 Hysteresis Input Receivers Separates rising & fall edge dc transfer curves weak feedback inverter Pad V in V out inhibit Pad V in Vout V out falling rising and only V in EE382M VLSI-II Class Notes Foil # 61

62 Hold Clamps Weak clamps hold tri-stated source terminated nets Pad weak feedback inverter V dd I/O Stronger clamps will actively terminate the net Can be slower than passive termination schemes EE382M VLSI-II Class Notes Foil # 62

63 ESD Design Pins subjected to ESD (electrostatic discharge) events during test & handling Over-voltages can also occur during functional operation System power-on Hot-plugging ESD discharge can occur between any two pins I/O to I/O I/O to Vdd or Gnd Pins are measured against standard ESD tests Human body model Machine model Charged Device Model ESD performance depends on many parameters other circuits don t care about EE382M VLSI-II Class Notes Foil # 63 63

64 ESD Circuits Non-breakdown based circuits Diodes Bipolar Junction Transistor MOS FET Primary ESD Circuit in CMOS Designs Breakdown based circuits Thick Field Oxide Device SCR (silicon controlled rectifier) Most Diode Circuits are really Bipolar Circuits EE382M VLSI-II Class Notes Foil # 64 64

65 Dual Diode ESD Circuits Single Supply Design Mixed voltage design ESD Diodes Pad Pad ESD Diodes EE382M VLSI-II Class Notes Foil # 65 65

66 FET ESD Circuits: non-breakdown mode ESD Diodes Pad nfet in diode configuration EE382M VLSI-II Class Notes Foil # 66 66

67 FET ESD Circuits: breakdown mode ESD Diodes Pad second breakdown nfet protects by clamping voltage after device snapback I V gs > V t V snapback EE382M VLSI-II Class Notes Foil # 67 67

68 Diode ESD Circuits fet devices are parasitic npn & pnp bipolar circuits vertical pnp device to substrate horizontal npn device to guard rings (before trench isolation) low vdd to gnd impedance to due on-chip capacitance provide additional discharge paths ESD Diodes Pad ESD bipolar devices Pad EE382M VLSI-II Class Notes Foil # 68 68

69 Parasitic Bipolar Circuits fet devices are parasitic npn & pnp bipolar circuits vertical pnp device to substrate EE382M VLSI-II Class Notes Foil # 69 69

70 ESD Test Models Human Body Model Requirements 2-4 kvolts Positive or negative discharge between any two pins V HBM R = 1.5 KΩ DUT C = 100 pf i peak = V HBM /1500 i(t) t = 2-10 nsec EE382M VLSI-II Class Notes Foil # 70 time 70

71 ESD Test Models Machine Model Requirements Volts Positive or negative discharge between any two pins L = μh V MM R < 8.5 Ω DUT C = 200 pf EE382M VLSI-II Class Notes Foil # 71 71

72 ESD Performance Factors Diode symmetry is important Bipolar conduction increases with temperature Hot spots conduct more, heat up more, conduct more, and finally burn out Layout corners are rounded to reduce electric fields Decoupling capacitance needed between all supplies Functional performance requirements impose ESD size & load capacitance constraints Parasitic bipolar effects abound Breakdown clamps don t scale EE382M VLSI-II Class Notes Foil # 72 72

73 Increasing Bandwidth EE382M VLSI-II Class Notes Foil # 73

74 Common Clock Transfers Chip to chip transfers controlled by common bus clock Equal length card routes to each chip & on-chip PLL s minimize clock skew Chip A PLL PLL Chip B EE382M VLSI-II Class Notes Foil # 74 clock source 74

75 Common Clock Transfers Cycle time to meet setup time max(t clk - A +T Aclk +T drive + T tof + T receive + T setup ) - min(t Bclk -T clk - B ) < T cycle Chip A T drive T tof T receive Tsetup PLL T Aclk PLL T Bclk Chip B T clk - A T clk - B EE382M VLSI-II Class Notes Foil # 75 clock source 75

76 Source Synchronous I/O Send source clock with source data Resolve clock phase differences with τ 1, τ 2, & τ 3 Chip A Chip B τ 3 PLL τ 1 τ 2 PLL EE382M VLSI-II Class Notes Foil # 76 clock source 76

77 Bus Pumping With T tof > T cycle, multiple bits are present on the wire Chip A Chip B τ 3 PLL τ 1 τ 2 PLL EE382M VLSI-II Class Notes Foil # 77 clock source 77

78 Dual Data Rate Conventional source synchronous design Data launched & captured on single clock edge Clock switches at f Maximium data rate = 1/2 * f Dual data rate - if clock can switch at f, why not data? Data is launched & captured on both clock edges Clock switches f Maximum data rate = f Conventional Dual Data Rate Clock Data EE382M VLSI-II Class Notes Foil # 78 78

79 Simultaneous Bidirectional Signaling Two chips send & receive data simultaneously on a point to point net Waveforms superimpose on the transmission line Each chip selects it s receiver reference voltage based on the data it sent Sending data is subtracted from total waveform Chip A Chip B 3/4 V dd 1/4 V dd 3/4 V dd 1/4 V dd EE382M VLSI-II Class Notes Foil # 79

80 Pattern Based Driver Compensation Incident waveforms along a long-lossy lines attenuate Slow RC like response to final level R s = Z o V s τ f where τ f = length / velocity With complex impedance and propagation constant high speed wavefront decays exponentially 1/2 (1- e -R*length/2Zo ) EE382M VLSI-II Class Notes Foil # 80

81 Pattern Based Driver Compensation Adjust driver strength based on bits sent in earlier cycles Example: When driving low to high Drive harder if previous bits sent = 00 Drive weaker if previous bits sent = 10 Without Compensation Receiver Switch Point With Compensation EE382M VLSI-II Class Notes Foil # 81 Drive harder

82 Increasing Bandwidth Preceding techniques cannot be achieved through clever circuit design alone Requires good packaging technology & net design Good termination Minimal capacitive & inductive discontinuities Low cross-talk Low simultaneous switching noise EE382M VLSI-II Class Notes Foil # 82

83 SerDes Architecture EE382M VLSI-II Class Notes Foil # 83

84 PCI-Express Interface EE382M VLSI-II Class Notes Foil # 84