New power semiconductor technologies challenge assembly and system setups

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1 New power semiconductor technologies challenge assembly and system setups Rich Pell - April 16, 2012 The increase of power density and performance at simultaneously decreasing cost is a constant trend in the power semiconductors world. It is widely accepted that this trend will continue into the foreseeable future, especially with new semiconductor materials. Silicon (Si), and such new materials as silicon carbide (SiC) and gallium nitride (GaN) devices aim for higher current densities that require higher operating temperatures of up to 200 C and above. Today's assembly technologies, however, cannot cope with the much higher load and temperature cycling capabilities. Another trend common to all of the materials is to switch faster to reduce losses and increase current capability. A tremendous potential of achieving approximately 7x lower switching losses lies in this direction. This article will look at the challenges to assembly and system setups with respect to low inductive interconnect technology. Basic power principles The driving force behind increased power density and performance at a lower cost originated from the semiconductor side of the equation, with the challenge of further innovation posed to, and a respective response from, package and assembly technologies. New system setups resulted, delivering new capabilities at ever shrinking volume and power losses. This looks similar to a basic principle, which has its correspondence in the universe entropy. There is only the way of growing entropy in a closed system: E. (1) In a not very strong scientific sense, this is also true for power semiconductors: Where: p/c (2) p = performance (with respect to advantage in terms of money) c = device cost At each step in performance there is an application where the step represents an advantage in a system and also in terms of money. If this performance improvement implicates higher cost, then the advantage has to compensate for the expense. Another alternative is only to reduce cost at everconstant performance this, however, results in stagnation and can be sustained only for a time.

2 The power devices shrink path Following this principle the power semiconductors experienced a very strong reduction in size and volume at ever-invariant current and voltage capabilities per device (See Figure 1.) Figure 1. On-state losses of 1200V-75A IGBT generations at constant switched power [1] Today, insulated gate bipolar transistors (IGBTs) are working for the same 1200V/75A and switching 100kW just as the first generation IGBT did, but doing so on two-fifths of the area previously required. A much greater shrink was possible with unipolar devices (See Figure 2.). Since 1993, 600V MOSFETs experienced a reduction by a factor of 10 in specific R on *A, which means that for the same R on a tenth of the previously used active area is used today. Figure 2. Active area-specific R on *A of 600 V MOSFET generations [2] This performance improvement was possible with silicon by applying increasingly better compensation technologies, and was true for unipolar and bipolar devices as well. This will be shown in the next section.

3 PHYSICAL MATERIAL CHALLENGES AND SOLUTIONS The compensation principle--mosfet bipolar devices In a normal power MOSFET with vertical current flow, on resistance is primarily determined by the MOSFET's blocking voltage and the doping and thickness of its drain region. From this dependency a simple relation with R on can be deduced [3]: R on ~ Vbr 2,5 (3) This means that for a given blocking voltage, a limit in R on naturally occurs. This limit is true for all materials at material-inherent levels. As long as there is homogenous doping in the material this relation describes the reality that for many years has not been overcome. However, as soon as there are doping concentrations distributed in columns of alternating n and p doping, which are close enough to each other to compensate by the respective depletion layer at increasing voltages below the critical breakdown field, then the relation changes to a pure proportionality: R on ~ Vbr. (4) The compensation principle is shown in Figure 3 for a CoolMOS device [4]. Figure 3. Compensation principle in CoolMOS device: On-state, the higher doped columns act as a 'short' across the drift region; Off-state, with applied VDS, the space charge region extends across the entire epi-layer => no free carriers => high breakdown voltage. In the on state the highly doped n-columns act as a very low-ohmic conductor, in the off state the paralleled n- and p-doped columns are fully depleted and the volume acts as an intrinsic (when p- and n-charges are equal) region with a rectangular field curve. The two relations (3) and (4) are shown as the solid and dotted border lines in Figure 4, together with real existing devices for Si-, SiC-, GaN-MOSFETs, and bipolar IGBTs (at rated current).

4 Figure 4. R on *A relation with designed blocking voltage of Si-, SiC- and GaN-MOSFET and JFET devices as well as for bipolar IGBT device (at rated current). What can be observed is that the relation (4) is roughly valid for all compensation devices. In that sense, the bipolar IGBT is also counted as a compensation device, as shown in the on state, holes and electrons are ideally compensated in the plasma. The solid (red) limit line for Si devices in Figure 4 is clearly overcome by CoolMOS and low-voltage MOSFETs (SFET devices), but also by IGBTs that follow straight to the dashed (red) limit line of 16µm pitch devices. Given SiC devices, the green limit line represents a shift by a constant factor of the Si line. Existing SiC JFET devices are still a factor of 5 from the limit, showing their potential even without compensation, and newly reported (lateral) GaN devices are even further away from the ideal computed limit of lateral devices (solid blue line). New materials challenges Using Figures 1 and 2 combined with the above discussion, it can easily be deduced that the shrink path of semiconductor power devices has been in place for a long time and, even with Si-devices, this path will continue be followed (Nakagawa line [6], and solid brown in Figure 4). With increasingly higher current densities in Si and even more in SiC or GaN devices, 200 A/cm 2 for 1200V Si, double or 3x with SiC, and even higher with GaN, problems are growing faster than they can be handled with existing assembly and interconnect technologies. These problems include: Low impedance interconnects (ohmic and inductive) Higher thermal resistance and lower thermal capacitance per chip demanding higher chiptemperature and better thermal interconnects

5 The need to handle higher current densities per package The same heat flow coming from smaller footprints to be removed into the ambient environment Improved semiconductor capabilities could be used for lower dissipated power to the ambient, however this path is, was, and will be followed given that Formula (2) is valid in this world. SHRINKING DEVICES PACKAGES Shrink path of packages During the past 25 years, several package standards for high-power bipolar switches were created, most importantly the 34-mm and 62-mm standards. The first attempts were with 2x 50A switches within the 34-mm standard and 2x150A for 62mm. Next steps with new chip generations involved the increase of current in existing packages. This path is shown in Figure 5, with questions shown as to future prospects. Figure 5. Possible power Output of an Inverter using V 62 mm half-bridge modules over the years. Another way of shrinking is to reduce package size and implement the same current into the smaller footprint as shown in Figure 6.

6 Figure 6. Shrink path of modules with same current (power output) in a smaller footprints. Thermal conditions improvement Given the chip and package miniaturization, an improvement in the thermal conditions was always an active guideline when using the smallest possible footprint. The higher current capability of the semiconductors connected with lower losses (on-state and switching) does not fully compensate for this. Several attempts were made in the past to create packages to ensure the full current capability of the chips, including: The use of isolation materials with better TCs, Using thinner isolation materials (fulfilling the save isolation needs) Fluid cooling (water, water shower, heat pipe) Connecting a cooler directly to DBC Using 2-side cooling Employing better interconnect technology Exploiting current at higher chip operating temperatures All of these methods are already in use today, however all of them have constraints and cannot be implemented in all applications. Several can be developed to ensure better performance in the future. The higher chip operating temperature Tjop is a promising path to achieve higher output power with smaller chips. This concept was discussed in a keynote presentation at PCIM'08 [7]. The capability in an air-cooled system for an existing package is shown in Figure 7. Without any change in interconnect technologies, an increase in Tjop from 150 C to 200 C enables a 40% increase in power dissipation and thus in output power.

7 Figure 7. Potential of higher-power density with higher Tjop in an air-cooled system (EconoPACK). This higher Tjop can be reached with Si Chips already and it is even easier with new SiC material, however a restriction is the power cycle lifetime of interconnects [7]. The earlier in the process the temperature swing takes place, bond wires interrupt the connection. A Tjop increase from 150 to 200 C would mean an improvement in cycling capability of the system by a factor of 10. New interconnect technology on the top and back of chips is required to reach this improvement [7]. Low-impedance connections The higher the current density in chips, the higher the current per bond wire and the greater the problems with cycling capability and with di/dt in the resulting parasitic inductance. Of course one can use more wires as long if there is sufficient room to place them, however this limit is easily reached, especially at lower voltage classes. In higher voltage classes, the problem with high inductive connections and especially high stray inductance in the system, is that they lead to severe voltage overshoot and oscillations such as those shown in Figure 8. Figure 8. IGBT turn-on and the impact of parasitic inductance on reverse recovery in a 1200A/3 3kV module using a diode with low tail charge.

8 High inductance drives higher overshoot voltage with a deeper reach into the plasma zone of the diode and removing charge too early, which is missing afterwards in the tail phase leading to high voltage overshoot and strong oscillations. Using a diode with higher tail charge helps, but this will increase losses, as shown in Figure 9 where losses are doubling. Figure 9. IGBT turn-on: Compensating high stray inductance with high diode tail charge whereby the losses are doubling (lower pink line). Of course, it is always possible to reduce oscillations by having slower switching devices with high tail charge, high Miller capacitance, and large gate resistors, etc. All of these measures lead to higher losses in the device, making the problem of removing heat from the semiconductor even more difficult. During turn-off the stray-inductance provides a high voltage overshoot along the switching device as shown in Figure 10. Figure 10. IGBT turn-off under different parasitic inductance (3.3kV/1200A-module). Overshoot voltage limits usable voltage region and increases losses. Overshoot voltage limits the usable operating voltage, which is normally compensated for by using a higher voltage class of devices, which leads to higher cost and higher losses. Using a negative

9 feedback loop helps to keep better control of oscillations and overshoot, however in most cases it also accounts for increased loss. The only and best way to reduce losses and oscillations under all operating conditions is to reduce stray inductance on much lower levels as in today's common modules and system setups. Switching improvements The need for modules and system setups with substantially lower impedance is a result of new generations of Si devices spanning all voltage classes. Of course, the combination of low voltage and high current requirements creates even greater pressure for low inductive module and system setups. This is especially true in such applications as hybrid and full electric car inverter setups with DC-link voltages up to 450 V and max currents in the region of 600 Amperes. In this case, the blocking voltage of a 600 V device is rapidly reached if the module and system setup is not designed so that stray inductance is below 25 nh (switching 600A in 100ns still produces a 150V peak). Again, a solution is to use higher-blocking devices and/or slower switching with a resulting price tag of increased stationary and dynamic losses. Tremendous improvement in turn-on losses and voltage overshoot may be achieved by using SiC diodes in the place of bipolar diodes. The reverse recovery charge is reduced to only a very small capacitive charge of the depletion layer of the diode, resulting in a reduction of turn-on losses (in the IGBT and diode) as shown in Figure 11. Figure 11. Comparison of simulated total switching losses of 1200V / 150A IGBTs with varied stray inductance for standard IGBT with Si-pn-diode (left group, blue bar), standard IGBT with SiC Diode (left group, purple) and with a future fast switching hypothetical IGBT with SiC diode (left group, light yellow). In this figure a switching loss comparison (Eon+Eoff) is simulated for a standard device combination of IGBT + bipolar diode, shown in the left group, blue bar), with a pair of IGBT + SiC diode, left group, purple bar, based on a 1200V/150A device with a 100 nh total stray inductance (corresponding to the 25 nh for current in a region of 600 A). The 20% reduction in total loss comes

10 from lower turn-on losses given the missing reverse recovery charge in a SiC diode (Also see [8]). In the Figure 11 configuration, the IGBT can be optimized much better for fast switching (at constant Vcesat) turn-on and turn-off, which is shown for a hypothetic device by the light yellow bar in the left group of Figure 11, resulting in 40% of total loss of the standard. These losses can be further reduced with smaller stray inductances in conjunction with a surplus vertical device optimization (OVS), resulting in less stored charge with another 40% loss reduction. At such low stray inductances of 50 nh for 150A, which corresponds to 7.5 nh for 1000A, it is no longer necessary to use a 1200V-blocking device for an application with a max DC-link voltage of 800V. If the device is constructed for a blocking voltage of only 1000V, losses can be reduced again by a surplus 40%, with a potential of reducing the switching losses by a factor of more than seven. Figure 12. Turn-off waveforms of simulated IGBT diode combination of Figure 11 showing the potential of optimization for fast switching with very low stray inductance. All of these optimizations can fully exploit the potential of such SiC active switches as JFET or MOSFET, or eventually GaN devices, always keeping in mind Formula (2). Outlook As previously discussed, the potential of such new semiconductor materials as SiC or GaN provide faster switching and very low R on *A capability with no threshold for IGBT and bipolar diodes. While they also provide an advantage in higher temperature capabilities, this is unfortunately still unusable, as there is no assembly technology available to fully exploit a 200 C capability of Si or a higher temperature capability of SiC or GaN.

11 To take full advantage of the improved electrical properties requires thermal and electrical assembly technologies that feature very low stray inductances with a 10x to 20x better load-cycling capability at a higher temperature swing. This same improvement path is also necessary for future Si devices. A great advantage can be gained using an integrated diode in a SiC JFET configuration with same performance as a SiC Schottky diode. This configuration would allows SiC to soon penetrate applications where Formula (2) pays off earlier, whereby higher usable current density can be used for a smaller module footprint, leading to higher power output in special applications. Acknowledgements This work took advantage of many measurements and simulations run in industrial and multimarket groups within Infineon Technologies. Especially I would like to gratefully acknowledge many enlightening discussions with F. Pfirsch and T. Raker on their simulations, and with R. Bayerer on the future prospects of assembly and packaging technology. About the Author: Dr. Gerhard Miller has been Head of Technology & Innovations Power in the Industrial and Multimarket Division at Infineon since 2008 and is responsible for SiC and IGBT/Diode technologies. Miller studied electrical engineering, specializing in electrical and semiconductor physics at the TU Munich. Dr. Miller is also involved in several fundamental patents and publications. References: [1] T.Laska, G.Miller et al: Short Circuit Properties of Trench-/Field-Stop-IGBTs - Design Aspects for a Superior Robustness, IEDM'03, Cambridge; and internal communication [2] G. Miller: Future Trends in High Power Semiconductors, ECPE workshop on "Research Challenges and Visions on Megawatt Power Electronics and Smart Grids', March 5th-6th, 2009, Zu rich, Switzerland [3] B.J. Baliga: Power Semiconductor Devices, PWS Publishing Company, 1995, p. 373 [4] A. Schlögl, G. Deboy et.al.: Properties of the New Compensation Devices (CoolMOS) between 420K and 80K the Ideal Device for Cryogenic Applications; ISPSD'99 [5] G. Miller: Panel discussion on future of power devices, ISPSD'05 Santa Barbara, USA [6] Nakagawa : Theoretical investigation of silicon limit characteristics of IGBT, ISPSD'06, Naples, s. 1-2 [7] R. Bayerer: Higher Junction Temperature in Power Modules a demand from hybrid cars, a potential for the next step increase in power density for various Variable Speed Drives, PCIM'08 Nuremberg [8] F. Pfirsch: Idealer Leistungsschalter unter dem Aspekt beliebig verkleinerbarer Streuinduktivitäten; 35. Kolloquium Halbleiter-Leistungs-Bauelemente und ihre systemtechnische Anwendung, Freiburg Okt 2006