Sense Amplifier for SRAM

Transcription

1 Sense Amplifier for SRAM Professor : Der-Chen Huang SoC Lab

2 Outline SRAM Structure Sense Amplifier Introduction Voltage-mode Current-mode Traditional Voltage-Mode Sense Amplifier Current-Mode Sense Amplifier 2

3 Elementary SRAM Structure Address Write Read Address Register Row Decoder Column Decoder SAen R/W WL Ysel Pre-charge Circuit Write Circuit Memory Cell Array Select Circuit Sense Amplifier Input Register IE Output Buffer Data_In Data_Out OE 3

4 SRAM 6T Cell SRAM 6T Cell structure 4

5 SRAM 6T Cell Read operation 1st step BL & BL = 1 Word line = 1 2nd step BL = 0 =1 X=0 Y=1 =1 =0 =1 5

6 SRAM 6T Cell Write operation =1 X=0 Y=1 X=1 Y=0 =1 =0 =1 =0 (a) Before write (b) After write 6

7 Sensing Amplifier Design Objective and Classification Design Objective[3] Minimum sense delay Required amplification Minimum power consumption Restricted layout area High reliability and tolerance Classification[1][3] Circuit Types Operation Mode Differential Voltage-mode Nondifferential Current-mode 7

8 Bit-line Model[1] Vdd Bit-line load R R R R Vo Memory Cell Ii RB C C C C RL io Bit-line Memory Cell Model Bit-line RC Model Sense Amplifier Model RC-line To Sense Amplifier 8

9 Bit-line Model R R R R Vo Ii RB C C C C RL io Memory Cell Model Bit-line RC Model Sense Amplifier Model I i is the output current of the driving source, i.e. memory cell. R B is the output resistance of the bit-line load in parallel with the drain resistance of the access transistor, which is the output device of the memory cell. The infinite RC ladder structure represents the interconnect line. The total resistance and capacitance of the line is given by R T and C T. The output of the line is terminated by resistor R L. 9

10 Bit-line Model R R R R Vo Ii RB C C C C RL io Memory Cell Model RC delay Bit-line RC Model Sense Amplifier Model δ t RT RB RL RC T T RL = + RBCT 2 RB + RT + RL RB+ RT + RL 10

11 Delay for Voltage-Mode For voltage-mode signals, R L is infinite and the output signal is the open-circuit voltage V o. RC delay RT RB+ + RL RC T T 3 RL δ t = + RBCT 2 RB + RT + RL RB+ RT + RL δt v RC = R RT T T B 11

12 Delay for Current-Mode For current-mode signals, R L is ideally zero and the output signal is the short-circuit current i o. RC delay RT 0 RB+ + RL 0 RC T T 3 RL δ t = 0 + RBCT 0 2 RB + RT + RL RB+ RT + RL δt i RT RB RC T T + 3 = 2 RB+ RT 12

13 Example Eample from [1], when RB = 2500Ω RT=250Ω CT=2pf Voltage-mode δ tv = 5.25ns Current-mode δ ti = 0.235ns 13

14 Traditional Voltage-mode Sense Amplifier Traditional Difference Amplifier[3] Full Complementary Positive-Feedback Sense Amplifier[2][3] Enhanced Positive Feedback Sense Amplifier [4] 14

15 Traditional Voltage-mode Sense Amplifier Traditional Difference Amplifier 1 W IMP 1 = k ( V V) 2 ' 2 n gs t L MP1 1 W IMP2 = k ( V V) 2 ' 2 n gs t L MP2 Current mirror MP1 & MP2 have the same Vgs IMP1 IMP2 0 I I MP2 MP2 MP1 W L = W L MP1 1= =0 1= SE = 1, Sense mode SE = 0, Standby mode 15

16 Traditional Voltage-mode Sense Amplifier Full Complementary Positive Feedback Sense Amplifier BL BL 1= =0 V V e o () t = o (0) i ( gmr 1) t RC SE = 1, Sense mode SE = 0, Standby mode 16

17 Traditional Voltage-mode Sense Amplifier Enhanced Positive Feedback Sense Amplifier Decouple device: avoid the effect of the bit-line capacitance 1 0 SE = 1, Sense mode SE = 0, Standby mode 17

18 Current-mode Sense Amplifier Clamped Bit-Line Sense Amplifier[5][6] Simple Four Transistor Sense Amplifier[1] Hybrid Current Sense Amplifier[8][9] New Hybrid Current Sense Amplifier[10] Modified CSA[11] 18

19 Current-mode Sense Amplifier Clamped Bit-Line Sense Amplifier Φ PRE = 1, Pre-charge Φ SA = 1, Sense Positive Feedback Circuit 0 1 Vgs 1 Vgs 2 The ΦPRE signal drives high to turn on M7 & M8, which works to equalize the output node to the same voltage level. I 1 I 2 M5 & M6 are biased in the linear region and provide a low-impedance clamp between the bit line and the ground. 19

20 Current-mode Sense Amplifier Clamped Bit-Line Sense Amplifier Advantages The input nodes of the sense amplifier are low-impedance current sensitive nodes, the voltage swing of the highly capacitance bit lines change small. The output nodes of the sense amplifier are no longer loaded with the bit-line capacitance and the sense amplifier is able to respond very rapidly. M1 ~ M4 works as a cross-coupled latch, its positive feedback effect can improve the driving ability of output nodes. Even the small input difference can be detected and the output can drive to full supply swing. 20

21 Current-mode Sense Amplifier Simple Four Transistor Sense Amplifier I+i I+i At the begin, Ysel are pulled down to gnd. Because DL near to ground level, T1~T4 will work in saturation region. i I i+i c O I+i+i c I+i The gate-source voltage of T 1 will be equal to that of T 3, since their currents are equal, their size are equal, and both transistors are in saturation. V 1 +V 2 i c + V 1 V V V - 2 i c V 1 +V 2 The gate-source voltage of T 2 will be equal to that of T 4, since their currents are equal, their size are equal, and both transistors are in saturation. I 21

22 Current-mode Sense Amplifier Simple Four Transistor Sense Amplifier Advantages In many cases it can fit in the column pitch, avoiding the need for column-select devices, thus again reducing propagation delay. There exists a virtual short circuit across the bit lines, therefore the potential of the bit lines will be equal independent of the current distribution. The sensing delay is unaffected by the bit-line capacitance since no differential capacitor discharging is required to sense the cell data. Discharge current i c from the bit-line capacitors, effectively precharging the sense amplifier. 22

23 Current-mode Sense Amplifier Simple Four Transistor Sense Amplifier Ysel = 0, Sense mode 0 1 I 5 I 5 = I 4 + I 6 Because current mirror effect, I 3 > I 4, so I 5 > I 4. Ysel = 1, Standby mode Because I 1 > I 2, so I 3 > I 4 I 6 I 1 I 3 Current mirror Current Conveyor I 2 I 4 23

24 Current-mode Sense Amplifier Hybrid Current Sense Amplifier 0 1 Positive Feedback Circuit 1 0 Current Conveyor I 1 Vgs 3 Vgs 4 I 2 Biased in the linear region and provide a low-impedanc. 24

25 Current-mode Sense Amplifier New Hybrid Current Sense Amplifier Overcome the pattern-dependent problem of the conventional current conveyor. In conventional current conveyor, after each read operation, the nodes RXP and RXN get floated and there will exist a residual differential voltage between them. The pattern-dependent problem occurs when the same logic value is sequentially read out several times from the same column. CBLSA Current Conveyor 25

26 Current-mode Sense Amplifier S.M. Wang s Sense Amplifier In standby state, pull the bitlines close to the ground level N7 & N8 are turned off to avoid DC current flows in the sense amplifier. Positive N3 Feedback & N4 are turned Circuiton to pull down the drains of the N5 & N6 to low-level. Standby Sensing state SEN = 01 SENB = V gs5 V gs6 I 2 I 1 Biased in the linear region and provide a low-impedance. 26

27 Reference [1] E. Sccvinck, P. J. van Beers, and H. Ontrop, Current-Mode Techniques for High- Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAMs, IEEE Journal of Solid-State Circuits Vol.26 No.4 pp April [2] T. P. Haraszti, High Performance CMOS Sense Amplifiers, United States Patent No. 4,169,233, Sep [3] Tegze P. Haraszti, CMOS Memory Circuits, Kluwer Academic Publishers, [4] V.Kristovski and Y. L. Pogrbeny, New Sense Amplifier for Small-Swing CMOS Logic Circuit, IEEE Trans, On Circuit and Systems, vol. 47, p.p. 573~576, June [5] Blalock, T.N. and Jaeger, R.C., A High-speed Clamped Bit-line Current-mode Sense Amplifier, IEEE J. Solid-State Circuits, vol. 26, no. 4, pp , April [6] Blalock, T.N. and Jaeger, R.C., A subnanosecond clamped-bit-line sense amplifier for 1T dynamic RAMs, Proceedings of VLSI Technology, Systems, and Applications, pp82-86, May

28 Reference (cont.) [7] Chrisanthopoulos, A., Moisiadis, Y., Tsiatouhas, Y. and Arapoyanni, A., Comparative study of different current mode sense amplifiers in submicron CMOS technology, IEE Pro. Circuits, Devices and Systems, vol. 149, no. 3, pp , June [8] P.Y. Chee, P.C. Liu, L. Siek, A high-speed current-mode sense-amplifier for CMOS SRAM's, Proceedings of 35th Midwest Symposium on Circuit and System, vol. 1, pp , Aug [9] P.Y. Chee, P.C. Liu, L. Siek, High-speed hybrid current-mode sense amplifier for CMOS SRAMs, ELECTRONICS LETTERS, vol. 28, no. 9, April [10] Jinn-Shyan Wang, Hong-Yu Lee, A new current-mode sense amplifier for lowvoltage low-power SRAM design, Eleventh Annual IEEE International Proceeding of ASIC, pp , Sep [11] S.M. Wang and C. Y. Wu, Full current-mode techniques for high-speed CMOS SRAMs, IEEE International Symposium on Circuit and Systems, vol. 4, pp.iv580- IV582, May