Bandwidth Enhanced Telescopic OTA

Size: px
Start display at page:

Download "Bandwidth Enhanced Telescopic OTA"

Transcription

1 J. of ctive and Passive Electronic Devices, Vol. 5, Rerints available directly from the ublisher Photocoying ermitted by license only 200 Old City Publishing, Inc. Published by license under the OCP Science imrint, a member of the Old City Publishing Grou Bandwidth Enhanced Telescoic OT Tianwang Li,3,*, Bo Ye 2, Jinguang Jiang and Xingcheng Han 3 Deartment of integrated circuits and communication software, Wuhan University, Wuhan, , China 2 Institute of Microelectronics, Shanghai University of Electronic Power, Shanghai, , China 3 Giantec Semiconductor Inc., Shanghai, 20203, China fully differential bandwidth enhanced telescoic oerational transconductance amlifier is resented in this aer. The unit-gain bandwidth of the roosed OT is enhanced by recycling the tail current. Both the conventional and roosed OTs are designed in 0.8 μm CMOS rocess. Simulation results show that there is a 64% imrovement in the unitgain bandwidth comared to that of conventional telescoic oerational transconductance amlifier. Keywords: OT, full differential, unit-gain bandwidth, circuit simulation, ower consumtion. Introduction Low-ower consumtion is an imortant secification in many electronic systems, such as wireless communication and imaging systems. In these electronic systems, analog integrated circuits consume a large art of the ower. Generally seaking, the OT is the block with the most ower consumtion in analog integrated circuits for many alications, such as DC, filter, and VG etc [ 8]. low ower OT design can save the system ower effectively. There is a tradeoff among seed, ower and gain for OT design. Usually these arameters resent contradictory choices for the OT architecture. There are three kinds of OTs: two stage OT, folded-cascode *Corresonding author: tianwangli@yahoo.com RC08-54 (Li).indd 327 6//200 :48:35 PM

2 328 Tianwang Li et al. VDD Vb M7 I M8 Vb Vb2 M5 M6 Vb2 Von Vbn2 M3 M4 Vbn2 Vo B Vin M M2 Vinn CMFB M0 2I Figure Conventional telescoic OT. transconductance amlifier and telescoic transconductance amlifier. The telescoic amlifier consumes the least ower comared with the other two amlifiers. The conventional telescoic amlifier is shown in Figure. Recently, telescoic amlifier design researches focus on imroving the gain and outut swing [3,4]. ctually, the ower efficiency of the telescoic OT can be imroved by enhancing the unit-gain bandwidth of the telescoic OT. From Figure, the DC current of M7 is the same as that of M. Only the current which flows in the NMOS differential air transistors hels to imrove the bandwidth. It is well known that less current can imrove the load resistors and imrove the gain of the amlifier. This aer rooses a novel telescoic amlifier which can reduce the current of load transistors M5 ~ M7 by introducing an additional PMOS differential air. The gain and bandwidth of the OT are enhanced. In the following sections, the roosed architecture will be shown and discussed in detail. The aer is organized as follows. Section 2 analyzes the gain and frequency resonse of the conventional telescoic OT. Section 3 describes the roosed architecture design. Section 4 shows the simulation results Section 5 resents a summary and conclusions regarding this work. 2 Conventional telescoic OT design The small signal half equivalent circuit of conventional OT is shown in Figure 2. The voltage gain of the conventional OT is given by: RC08-54 (Li).indd 328 6//200 :48:35 PM

3 Bandwidth Enhanced Telescoic OT 329 M3 r C Vo M Vi Figure 2 Small signal half equivalent circuit of conventional telescoic OT. = G R () V m out where G m and R out reresent the transconductance and outut resistor resectively. In Figure 2, r is the PMOS current mirror small signal equivalent resistance, r = gm5 rds5 rds 7. The outut resistor is Rout = r // gm3 rds3 rds. It is well known that the G = g, so () can be shown as m m (( ) ( )) = g g r r // g r r (2) V m m5 ds5 ds7 m3 ds3 ds The frequency resonse of the conventional telescoic OT in Figure is determined rimarily by the outut dominant ole which is given as out = R C + C out ( ) L (3) where and C is the load caacitor and outut arasitic caacitor resectively. The unit-gain bandwidth ω u of the OT in Figure is ω u gm = C + C The non dominant oles are located at node and B in Figure, which are given as L (4) B, gm, = 34 C (5) where g m3,4 is the transconductance of the cascode transistor (M3, M4), C is the total arasitic caacitors at the node or B. From (4), increasing g m can imrove the unit-gain bandwidth of the conventional OT. It is well known that the gm can be increased by enlarging the current 2I in Figure. It means that RC08-54 (Li).indd 329 6//200 :48:37 PM

4 330 Tianwang Li et al. the ower consumtion of OT is also increased. In this aer, we roose a novel architecture by recycling the tail current. The bandwidth of the roosed OT can be imroved significantly without increasing the ower consumtion. 3 roosed fully differential telescoic oerational transconductor amlifier The roosed fully differential telescoic OT is shown in Figure 3. The transistors M0 ~ M8 use the same architecture with the conventional telescoic amlifier as shown in Figure, a PMOS differential air is introduced comared with conventional telescoic amlifier. The tail current of the PMOS differential air is 2 I, here 0. The PMOS differential air injects current into node and B, which hels to imrove the bandwidth of the amlifier. Furthermore, the PMOS differential air does not consume additional ower, and the ower consumtion of the roosed design is the same as the conventional one. The small signal half equivalent circuit is shown in Figure 4. Comared with Figure 2, there is an additional PMOS transistor contributing to Gm in Figure 4. It is easy to get DC gain and unit-gain bandwidth from Figure 4. The DC gain of the roosed OT is (( ) ( )) = ( g + g ) g r r // g r ( r // r ) V m m0 m5 ds5 ds7 m3 ds3 ds ds0 (6) VDD Vb M9 2 I Vb M7 I M8 Vb Vin M0 M Vinn Von Vb2 M5 M6 Vb2 Vo Vbn2 M3 M4 Vbn2 B Vin M M2 Vinn CMFB M0 2I Figure 3 Proosed telescoic OT RC08-54 (Li).indd 330 6//200 :48:38 PM

5 Bandwidth Enhanced Telescoic OT 33 Vi M0 M3 rl C Vo Ml Vi Figure 4 Small signal half equivalent circuit of roosed telescoic OT. The unit-gain bandwidth of the roosed design is g = C + g m m0 ω u + C L (7) The outut dominant ole of the roosed design is given as out = R C + C out ( ) L (8) The non dominant oles of the roosed OT are also located at node and B in Figure 3, which is given as B, gm, = 34 C (9) From (4) and (7), the denominator is C + L C. In the roosed design of Figure 3, the outut arasitic caacitor is reduced because the current flows in the M3~M8 is smaller than that of the conventional OT in Figure. These transistors can be designed by using small size. The numerator in (7) is gm+ gm0 comaring with g m in (4). So the bandwidth of the roosed OT is enhanced without increasing the ower consumtion. For a certain unitgain bandwidth, the ower consumtion of the roosed design can be reduced comaring with the conventional telescoic OT. This will be benefit for imroving the ower efficiency of the analog system. 3 Simulation results Both the conventional and roosed telescoic amlifier are designed and simulated in 0.8 µm CMOS rocess. The load caacitor is 2F and target unitgain bandwidth is 200 MHz. To comare the ower efficiency of the roosed RC08-54 (Li).indd 33 6//200 :48:39 PM

6 332 Tianwang Li et al. design with the conventional telescoic amlifier, an ideal CMFB architecture is used. Two roosed OT simulation results are resented in this aer. The first roosed design uses the same current with the conventional OT, the second roosed design achieves the same unit-gain bandwidth with the conventional OT. The C frequency resonses of the conventional OT and the roosed designs are shown in the Figure 5, Figure 6, Figure 7, resectively. It can be found clearly that the unit-gain bandwidth of the conventional design is 228 MHz, and the unit-gain bandwidth of the roosed OT is 375 MHz. The unit-gain bandwidth of the roosed design is about 64% higher than that of the conventional design. Moreover, the DC gain of the roosed design is 6dB higher than that of the conventional telescoic amlifier. Figure 5 Frequency resonse of the conventional OT. Figure 6 Frequency resonse of the roosed OT RC08-54 (Li).indd 332 6//200 :48:40 PM

7 Bandwidth Enhanced Telescoic OT 333 Figure 7 Frequency resonse of the roosed OT2. Table Performance comarison of conventional OT and the roosed design. Parameter Conventional OT Proosed OT Proosed OT2 UGBW(MHz) Power(µ) Gain(dB) PM(deg) Suly voltage Technology 0.8 µm CMOS The unit-gain bandwidth of the second roosed OT is 224 MHz, which is nearly the same as that of the conventional OT. The ower consumtion of the second roosed design is 300 u, which is 50% smaller than that of the conventional OT. The erformance summary of the designs is summarized in table. 4 Conclusions bandwidth enhanced telescoic oerational amlifier is resented in this aer. The bandwidth of the telescoic OT is imroved by recycling the tail current. Comaring with the conventional telescoic OT, the roosed design can achieve the same unit-gain bandwidth with less current consumtion. It can be widely used for low ower alications RC08-54 (Li).indd 333 6//200 :48:40 PM

8 334 Tianwang Li et al. References [] Liu M., Huang K., Ou Wei., et al. low voltage-ower 3-bit 6 MSPS CMOS ieline DC. IEEE J Solid-State Circuits, 2004, 39, [2] Ming B., Kim P., Bowman F. W, et al. 69 mw 0-bit 80 MSamle/s ieline DC. IEEE J Solid-State Circuits, 2003, 38, [3] Vecchi D., zzolini C., Boni., et al. 00-MS/s Track-and-Hold mlifier in 0.8-µm CMOS. Proceeding of Euroean Solid-State Circuits Conference, 2005, [4] Gulati K, Lee H S. high swing telescoic oerational amlifier. IEEE J Solid-State Circuits, 998, 33, [5] rias J., Boccuzzi V and Qunintanilla L., et al. Low ower ieline DC for wireless LNs. IEEE J Solid-State Circuits, 2004, 39, [6] Ryu S., Ray S., and Song B. et al. 4-b linear caacitor for self-trimming ielined DC. IEEE J Solid-State Circuits, 2004, 39, [7] Shu Y., and Song B. 5-b linear 20-Ms/s ielined DC digitally calibrated with signal deendant dithering. IEEE J Solid-State Circuits, 2008, 43, [8] Lee B., Min B., and Manganaro G., et al. 4b 00MS/s ielined DC with a merged active S/H and first MDC, ISSCC Dig. Tech. Paers, 2008, RC08-54 (Li).indd 334 6//200 :48:40 PM

One-Chip Linear Control IPS, F5106H

One-Chip Linear Control IPS, F5106H One-Chi Linear Control IPS, F5106H NAKAGAWA Sho OE Takatoshi IWAMOTO Motomitsu ABSTRACT In the fi eld of vehicle electrical comonents, the increasing demands for miniaturization, reliability imrovement

More information

Analysis and Design of High gain Low Power Fully Differential Gain- Boosted Folded-Cascode Op-amp with Settling time optimization

Analysis and Design of High gain Low Power Fully Differential Gain- Boosted Folded-Cascode Op-amp with Settling time optimization Analysis and Design of High gain Low Power Fully Differential Gain- Boosted Folded-Cascode Op-amp with Settling time optimization Shubhara Yewale * and R. S. Gamad ** * (Department of Electronics & Instrumentation

More information

MOS Transistors as Switches

MOS Transistors as Switches MOS Transistors as Switches G (gate) nmos transistor: Closed (conducting) when Gate = 1 (V DD ) D (drain) S (source) Oen (non-conducting) when Gate = 0 (ground, 0V) G MOS transistor: Closed (conducting)

More information

ISSCC 2003 / SESSION 13 / 40Gb/s COMMUNICATION ICS / PAPER 13.7

ISSCC 2003 / SESSION 13 / 40Gb/s COMMUNICATION ICS / PAPER 13.7 ISSCC 2003 / SESSION 13 / 40Gb/s COMMUNICATION ICS / PAPER 13.7 13.7 A 40Gb/s Clock and Data Recovery Circuit in 0.18µm CMOS Technology Jri Lee, Behzad Razavi University of California, Los Angeles, CA

More information

Fully Differential CMOS Amplifier

Fully Differential CMOS Amplifier ECE 511 Analog Electronics Term Project Fully Differential CMOS Amplifier Saket Vora 6 December 2006 Dr. Kevin Gard NC State University 1 Introduction In this project, a fully differential CMOS operational

More information

A Virtual Machine Dynamic Migration Scheduling Model Based on MBFD Algorithm

A Virtual Machine Dynamic Migration Scheduling Model Based on MBFD Algorithm International Journal of Comuter Theory and Engineering, Vol. 7, No. 4, August 2015 A Virtual Machine Dynamic Migration Scheduling Model Based on MBFD Algorithm Xin Lu and Zhuanzhuan Zhang Abstract This

More information

HALF-WAVE & FULL-WAVE RECTIFICATION

HALF-WAVE & FULL-WAVE RECTIFICATION HALF-WAE & FULL-WAE RECTIFICATION Objectives: HALF-WAE & FULL-WAE RECTIFICATION To recognize a half-wave rectified sinusoidal voltage. To understand the term mean value as alied to a rectified waveform.

More information

Small Signal Analysis of a PMOS transistor Consider the following PMOS transistor to be in saturation. Then, 1 2

Small Signal Analysis of a PMOS transistor Consider the following PMOS transistor to be in saturation. Then, 1 2 Small Signal Analysis of a PMOS transistor Consider the following PMOS transistor to be in saturation. Then, 1 I SD = µ pcox( VSG Vtp)^2(1 + VSDλ) 2 From this equation it is evident that I SD is a function

More information

Design of a Fully Differential Two-Stage CMOS Op-Amp for High Gain, High Bandwidth Applications

Design of a Fully Differential Two-Stage CMOS Op-Amp for High Gain, High Bandwidth Applications Design of a Fully Differential Two-Stage CMOS Op-Amp for High Gain, High Bandwidth Applications Rajkumar S. Parihar Microchip Technology Inc. Rajkumar.parihar@microchip.com Anu Gupta Birla Institute of

More information

CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS

CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS CHAPTER 10 OPERATIONAL-AMPLIFIER CIRCUITS Chapter Outline 10.1 The Two-Stage CMOS Op Amp 10.2 The Folded-Cascode CMOS Op Amp 10.3 The 741 Op-Amp Circuit 10.4 DC Analysis of the 741 10.5 Small-Signal Analysis

More information

Estimation of Reliability of a Interleaving PFC Boost Converter

Estimation of Reliability of a Interleaving PFC Boost Converter SRBIAN JOURNAL OF LCTRICAL NGINRING Vol. 7, No. 2, November 2010, 205-216 UDK: 621.314.6 stimation of Reliability of a Interleaving PFC Boost Converter Gulam Amer Sandeudi 1, Srinivasa Rao 2 Abstract:

More information

Notes about Small Signal Model. for EE 40 Intro to Microelectronic Circuits

Notes about Small Signal Model. for EE 40 Intro to Microelectronic Circuits Notes about Small Signal Model for EE 40 Intro to Microelectronic Circuits 1. Model the MOSFET Transistor For a MOSFET transistor, there are NMOS and PMOS. The examples shown here would be for NMOS. Figure

More information

IGBT (Insulated Gate Bipolar Transistor) 1 Differences Between MOSFET and IGBT

IGBT (Insulated Gate Bipolar Transistor) 1 Differences Between MOSFET and IGBT IGBT (Insulated Gate Biolar Transistor) 1 Differences Between MOSFET and IGBT 1.1 Structure The IGBT combines in it all the advantages of the biolar and MOS field effect transistor. As can be seen from

More information

EECS 240 Topic 7: Current Sources

EECS 240 Topic 7: Current Sources EECS 240 Analog Integrated Circuits Topic 7: Current Sources Bernhard E. Boser,Ali M. Niknejad and S.Gambini Department of Electrical Engineering and Computer Sciences Bias Current Sources Applications

More information

Simulink Implementation of a CDMA Smart Antenna System

Simulink Implementation of a CDMA Smart Antenna System Simulink Imlementation of a CDMA Smart Antenna System MOSTAFA HEFNAWI Deartment of Electrical and Comuter Engineering Royal Military College of Canada Kingston, Ontario, K7K 7B4 CANADA Abstract: - The

More information

A true low voltage class-ab current mirror

A true low voltage class-ab current mirror A true low voltage class-ab current mirror A. Torralba, 1a) R. G. Carvajal, 1 M. Jiménez, 1 F. Muñoz, 1 and J. Ramírez-Angulo 2 1 Departamento de Ingeniería Electrónica, Escuela Superior de Ingenieros,

More information

A 3 V 12b 100 MS/s CMOS D/A Converter for High- Speed Communication Systems

A 3 V 12b 100 MS/s CMOS D/A Converter for High- Speed Communication Systems JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.3, NO., DECEMBER, 3 A 3 V b MS/s CMOS D/A Converter for High- Speed Communication Systems Min-Jung Kim, Hyuen-Hee Bae, Jin-Sik Yoon, and Seung-Hoon

More information

Chapter 8 Differential and Multistage Amplifiers. EE 3120 Microelectronics II

Chapter 8 Differential and Multistage Amplifiers. EE 3120 Microelectronics II 1 Chapter 8 Differential and Multistage Amplifiers Operational Amplifier Circuit Components 2 1. Ch 7: Current Mirrors and Biasing 2. Ch 9: Frequency Response 3. Ch 8: Active-Loaded Differential Pair 4.

More information

Performance Comparison of an Algorithmic Current- Mode ADC Implemented using Different Current Comparators

Performance Comparison of an Algorithmic Current- Mode ADC Implemented using Different Current Comparators Performance Comparison of an Algorithmic Current- Mode ADC Implemented using Different Current Comparators Veepsa Bhatia Indira Gandhi Delhi Technical University for Women Delhi, India Neeta Pandey Delhi

More information

Cancellation of Load-Regulation in Low Drop-Out Regulators

Cancellation of Load-Regulation in Low Drop-Out Regulators Cancellation of Load-Regulation in Low Drop-Out Regulators Rajeev K. Dokania, Student Member, IEE and Gabriel A. Rincόn-Mora, Senior Member, IEEE Georgia Tech Analog Consortium Georgia Institute of Technology

More information

Selected Filter Circuits Dr. Lynn Fuller

Selected Filter Circuits Dr. Lynn Fuller ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Selected Filter Circuits Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 146235604 Tel (585) 4752035

More information

Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications

Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications Efficient Interconnect Design with Novel Repeater Insertion for Low Power Applications TRIPTI SHARMA, K. G. SHARMA, B. P. SINGH, NEHA ARORA Electronics & Communication Department MITS Deemed University,

More information

Load Balancing Mechanism in Agent-based Grid

Load Balancing Mechanism in Agent-based Grid Communications on Advanced Comutational Science with Alications 2016 No. 1 (2016) 57-62 Available online at www.isacs.com/cacsa Volume 2016, Issue 1, Year 2016 Article ID cacsa-00042, 6 Pages doi:10.5899/2016/cacsa-00042

More information

DESIGNING high-performance analog circuits is becoming

DESIGNING high-performance analog circuits is becoming 2010 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 12, DECEMBER 1998 A High-Swing CMOS Telescopic Operational Amplifier Kush Gulati and Hae-Seung Lee, Fellow, IEEE Abstract A high-swing, high-performance

More information

Systematic Design for a Successive Approximation ADC

Systematic Design for a Successive Approximation ADC Systematic Design for a Successive Approximation ADC Mootaz M. ALLAM M.Sc Cairo University - Egypt Supervisors Prof. Amr Badawi Dr. Mohamed Dessouky 2 Outline Background Principles of Operation System

More information

Digital to Analog Converter. Raghu Tumati

Digital to Analog Converter. Raghu Tumati Digital to Analog Converter Raghu Tumati May 11, 2006 Contents 1) Introduction............................... 3 2) DAC types................................... 4 3) DAC Presented.............................

More information

Monitoring Frequency of Change By Li Qin

Monitoring Frequency of Change By Li Qin Monitoring Frequency of Change By Li Qin Abstract Control charts are widely used in rocess monitoring roblems. This aer gives a brief review of control charts for monitoring a roortion and some initial

More information

DAY-AHEAD ELECTRICITY PRICE FORECASTING BASED ON TIME SERIES MODELS: A COMPARISON

DAY-AHEAD ELECTRICITY PRICE FORECASTING BASED ON TIME SERIES MODELS: A COMPARISON DAY-AHEAD ELECTRICITY PRICE FORECASTING BASED ON TIME SERIES MODELS: A COMPARISON Rosario Esínola, Javier Contreras, Francisco J. Nogales and Antonio J. Conejo E.T.S. de Ingenieros Industriales, Universidad

More information

MODEL OF THE PNEUMATIC DOUBLE ACTING CYLINDER COMPILED BY RHD RESISTANCES

MODEL OF THE PNEUMATIC DOUBLE ACTING CYLINDER COMPILED BY RHD RESISTANCES Journal of alied science in the thermodynamics and fluid mechanics Vol. 3, No. 1/009, ISSN 180-9388 MODEL OF THE PNEUMATIC DOUBLE ACTING CYLINDER COMPILED BY RHD RESISTANCES *Lukáš DVOŘÁK * Deartment of

More information

MAS.836 HOW TO BIAS AN OP-AMP

MAS.836 HOW TO BIAS AN OP-AMP MAS.836 HOW TO BIAS AN OP-AMP Op-Amp Circuits: Bias, in an electronic circuit, describes the steady state operating characteristics with no signal being applied. In an op-amp circuit, the operating characteristic

More information

A 1-GSPS CMOS Flash A/D Converter for System-on-Chip Applications

A 1-GSPS CMOS Flash A/D Converter for System-on-Chip Applications A -GSPS CMOS Flash A/D Converter for System-on-Chip Applications Jincheol Yoo, Kyusun Choi, and Ali Tangel Department of Computer Science & Department of Computer & Engineering Communications Engineering

More information

Monte Carlo Simulation of Device Variations and Mismatch in Analog Integrated Circuits

Monte Carlo Simulation of Device Variations and Mismatch in Analog Integrated Circuits Proceedings of The National Conference On Undergraduate Research (NCUR) 2006 The University of North Carolina at Asheville Asheville, North Carolina April 6 8, 2006 Monte Carlo Simulation of Device Variations

More information

The risk of using the Q heterogeneity estimator for software engineering experiments

The risk of using the Q heterogeneity estimator for software engineering experiments Dieste, O., Fernández, E., García-Martínez, R., Juristo, N. 11. The risk of using the Q heterogeneity estimator for software engineering exeriments. The risk of using the Q heterogeneity estimator for

More information

The CARIOCA Front End Chip for the LHCb muon chambers

The CARIOCA Front End Chip for the LHCb muon chambers LHCb Collaboration LHCb-MUON 2003-009 January 2003 The CARIOCA Front End Chip for the LHCb muon chambers D. Moraes 1, W. Bonivento 2, N. Pelloux 2,W.Riegler 2 1 LAPE-IF/UFRJ, CP 68528 Cidade Univ., BR-21945970

More information

10 BIT s Current Mode Pipelined ADC

10 BIT s Current Mode Pipelined ADC 10 BIT s Current Mode Pipelined ADC K.BHARANI VLSI DEPARTMENT VIT UNIVERSITY VELLORE, INDIA kothareddybharani@yahoo.com P.JAYAKRISHNAN VLSI DEPARTMENT VIT UNIVERSITY VELLORE, INDIA pjayakrishnan@vit.ac.in

More information

COST CALCULATION IN COMPLEX TRANSPORT SYSTEMS

COST CALCULATION IN COMPLEX TRANSPORT SYSTEMS OST ALULATION IN OMLEX TRANSORT SYSTEMS Zoltán BOKOR 1 Introduction Determining the real oeration and service costs is essential if transort systems are to be lanned and controlled effectively. ost information

More information

The fast Fourier transform method for the valuation of European style options in-the-money (ITM), at-the-money (ATM) and out-of-the-money (OTM)

The fast Fourier transform method for the valuation of European style options in-the-money (ITM), at-the-money (ATM) and out-of-the-money (OTM) Comutational and Alied Mathematics Journal 15; 1(1: 1-6 Published online January, 15 (htt://www.aascit.org/ournal/cam he fast Fourier transform method for the valuation of Euroean style otions in-the-money

More information

Wide Band Tunable Filter Design Implemented in CMOS

Wide Band Tunable Filter Design Implemented in CMOS Wide Band Tunable Filter Design Implemented in CMOS W. Matthew Anderson and Bogdan M. Wilamowski Electrical & Computer Engineering Dept. Auburn University, AL 36849 anderwm@auburn.edu, wilambm@auburn.edu

More information

Synopsys RURAL ELECTRICATION PLANNING SOFTWARE (LAPER) Rainer Fronius Marc Gratton Electricité de France Research and Development FRANCE

Synopsys RURAL ELECTRICATION PLANNING SOFTWARE (LAPER) Rainer Fronius Marc Gratton Electricité de France Research and Development FRANCE RURAL ELECTRICATION PLANNING SOFTWARE (LAPER) Rainer Fronius Marc Gratton Electricité de France Research and Develoment FRANCE Synosys There is no doubt left about the benefit of electrication and subsequently

More information

Passive Compensation For High Performance Inter-Chip Communication

Passive Compensation For High Performance Inter-Chip Communication Passive Comenion For High Performance Inter-Chi Communication Chun-Chen Liu, Haikun Zhu and Chung-Kuan Cheng Deartment of Comuter Science and Engineering University of California, San Diego E-mail: ch1084@ucsd.edu,{hazhu,ckcheng}@cse.ucsd.edu

More information

Op-Amp Simulation EE/CS 5720/6720. Read Chapter 5 in Johns & Martin before you begin this assignment.

Op-Amp Simulation EE/CS 5720/6720. Read Chapter 5 in Johns & Martin before you begin this assignment. Op-Amp Simulation EE/CS 5720/6720 Read Chapter 5 in Johns & Martin before you begin this assignment. This assignment will take you through the simulation and basic characterization of a simple operational

More information

A Study of Low Cost Meteorological Monitoring System Based on Wireless Sensor Networks

A Study of Low Cost Meteorological Monitoring System Based on Wireless Sensor Networks , pp.100-104 http://dx.doi.org/10.14257/astl.2014.45.19 A Study of Low Cost Meteorological Monitoring System Based on Wireless Sensor Networks Li Ma 1,2,3, Jingzhou Yan 1,2,Kuo Liao 3,4, Shuangshuang Yan

More information

LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS

LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS LAB 7 MOSFET CHARACTERISTICS AND APPLICATIONS Objective In this experiment you will study the i-v characteristics of an MOS transistor. You will use the MOSFET as a variable resistor and as a switch. BACKGROUND

More information

A 2.4GHz Cascode CMOS Low Noise Amplifier

A 2.4GHz Cascode CMOS Low Noise Amplifier A 2.4GHz Cascode CMOS Low Noise Amplifier Gustavo Campos Martins Universidade Federal de Santa Catarina Florianopolis, Brazil gustavocm@ieee.org Fernando Rangel de Sousa Universidade Federal de Santa Catarina

More information

Here we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices.

Here we introduced (1) basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices. Outline Here we introduced () basic circuit for logic and (2)recent nano-devices, and presented (3) some practical issues on nano-devices. Circuit Logic Gate A logic gate is an elemantary building block

More information

Service Network Design with Asset Management: Formulations and Comparative Analyzes

Service Network Design with Asset Management: Formulations and Comparative Analyzes Service Network Design with Asset Management: Formulations and Comarative Analyzes Jardar Andersen Teodor Gabriel Crainic Marielle Christiansen October 2007 CIRRELT-2007-40 Service Network Design with

More information

Rejuvenating the Supply Chain by Benchmarking using Fuzzy Cross-Boundary Performance Evaluation Approach

Rejuvenating the Supply Chain by Benchmarking using Fuzzy Cross-Boundary Performance Evaluation Approach ICSI International Journal of Engineering and echnology, Vol.2, o.6, December 2 ISS: 793-8236 Rejuvenating the Suly Chain by Benchmarking using uzzy Cross-Boundary erformance Evaluation roach RU SUIL BIDU,

More information

*For stability of the feedback loop, the differential gain must vary as

*For stability of the feedback loop, the differential gain must vary as ECE137a Lab project 3 You will first be designing and building an op-amp. The op-amp will then be configured as a narrow-band amplifier for amplification of voice signals in a public address system. Part

More information

An Introduction to the EKV Model and a Comparison of EKV to BSIM

An Introduction to the EKV Model and a Comparison of EKV to BSIM An Introduction to the EKV Model and a Comparison of EKV to BSIM Stephen C. Terry 2. 3.2005 Integrated Circuits & Systems Laboratory 1 Overview Characterizing MOSFET operating regions EKV model fundamentals

More information

Title: Stochastic models of resource allocation for services

Title: Stochastic models of resource allocation for services Title: Stochastic models of resource allocation for services Author: Ralh Badinelli,Professor, Virginia Tech, Deartment of BIT (235), Virginia Tech, Blacksburg VA 2461, USA, ralhb@vt.edu Phone : (54) 231-7688,

More information

Forensic Science International

Forensic Science International Forensic Science International 214 (2012) 33 43 Contents lists available at ScienceDirect Forensic Science International jou r nal h o me age: w ww.els evier.co m/lo c ate/fo r sc iin t A robust detection

More information

Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors.

Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors. Whites, EE 320 Lecture 30 Page 1 of 8 Lecture 30: Biasing MOSFET Amplifiers. MOSFET Current Mirrors. There are two different environments in which MOSFET amplifiers are found, (1) discrete circuits and

More information

Web Application Scalability: A Model-Based Approach

Web Application Scalability: A Model-Based Approach Coyright 24, Software Engineering Research and Performance Engineering Services. All rights reserved. Web Alication Scalability: A Model-Based Aroach Lloyd G. Williams, Ph.D. Software Engineering Research

More information

LABORATORY 2 THE DIFFERENTIAL AMPLIFIER

LABORATORY 2 THE DIFFERENTIAL AMPLIFIER LABORATORY 2 THE DIFFERENTIAL AMPLIFIER OBJECTIVES 1. To understand how to amplify weak (small) signals in the presence of noise. 1. To understand how a differential amplifier rejects noise and common

More information

THE RELATIONSHIP BETWEEN EMPLOYEE PERFORMANCE AND THEIR EFFICIENCY EVALUATION SYSTEM IN THE YOTH AND SPORT OFFICES IN NORTH WEST OF IRAN

THE RELATIONSHIP BETWEEN EMPLOYEE PERFORMANCE AND THEIR EFFICIENCY EVALUATION SYSTEM IN THE YOTH AND SPORT OFFICES IN NORTH WEST OF IRAN THE RELATIONSHIP BETWEEN EMPLOYEE PERFORMANCE AND THEIR EFFICIENCY EVALUATION SYSTEM IN THE YOTH AND SPORT OFFICES IN NORTH WEST OF IRAN *Akbar Abdolhosenzadeh 1, Laya Mokhtari 2, Amineh Sahranavard Gargari

More information

Design of Low Power One-Bit Hybrid-CMOS Full Adder Cells

Design of Low Power One-Bit Hybrid-CMOS Full Adder Cells Design of Low Power One-Bit Hybrid-CMOS Full Adder Cells Sushil B. Bhaisare 1, Sonalee P. Suryawanshi 2, Sagar P. Soitkar 3 1 Lecturer in Electronics Department, Nagpur University, G.H.R.I.E.T.W. Nagpur,

More information

Piracy and Network Externality An Analysis for the Monopolized Software Industry

Piracy and Network Externality An Analysis for the Monopolized Software Industry Piracy and Network Externality An Analysis for the Monoolized Software Industry Ming Chung Chang Deartment of Economics and Graduate Institute of Industrial Economics mcchang@mgt.ncu.edu.tw Chiu Fen Lin

More information

BJT AC Analysis 1 of 38. The r e Transistor model. Remind Q-poiint re = 26mv/IE

BJT AC Analysis 1 of 38. The r e Transistor model. Remind Q-poiint re = 26mv/IE BJT AC Analysis 1 of 38 The r e Transistor model Remind Q-poiint re = 26mv/IE BJT AC Analysis 2 of 38 Three amplifier configurations, Common Emitter Common Collector (Emitter Follower) Common Base BJT

More information

STATISTICAL CHARACTERIZATION OF THE RAILROAD SATELLITE CHANNEL AT KU-BAND

STATISTICAL CHARACTERIZATION OF THE RAILROAD SATELLITE CHANNEL AT KU-BAND STATISTICAL CHARACTERIZATION OF THE RAILROAD SATELLITE CHANNEL AT KU-BAND Giorgio Sciascia *, Sandro Scalise *, Harald Ernst * and Rodolfo Mura + * DLR (German Aerosace Centre) Institute for Communications

More information

A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

A 1.62/2.7/5.4 Gbps Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.13, NO.3, JUNE, 2013 http://dx.doi.org/10.5573/jsts.2013.13.3.185 A 1.62/2.7/5.4 Clock and Data Recovery Circuit for DisplayPort 1.2 with a single VCO

More information

Simulation and Optimization of Analog Circuits

Simulation and Optimization of Analog Circuits Simulation and Optimization of Analog Circuits (Optimization Methods for Circuit Design) Helmut Graeb graeb@tum.de Institute of Electronic Design Automation Technische Universitaet Muenchen Sizing Rules

More information

Description. 5k (10k) - + 5k (10k)

Description. 5k (10k) - + 5k (10k) THAT Corporation Low Noise, High Performance Microphone Preamplifier IC FEATURES Excellent noise performance through the entire gain range Exceptionally low THD+N over the full audio bandwidth Low power

More information

MEASUREMENT UNCERTAINTY IN VECTOR NETWORK ANALYZER

MEASUREMENT UNCERTAINTY IN VECTOR NETWORK ANALYZER MEASUREMENT UNCERTAINTY IN VECTOR NETWORK ANALYZER W. Li, J. Vandewege Department of Information Technology (INTEC) University of Gent, St.Pietersnieuwstaat 41, B-9000, Gent, Belgium Abstract: Precision

More information

Application Report SLVA051

Application Report SLVA051 Application Report November 998 Mixed-Signal Products SLVA05 ltage Feedback Vs Current Feedback Op Amps Application Report James Karki Literature Number: SLVA05 November 998 Printed on Recycled Paper IMPORTANT

More information

Large-Scale IP Traceback in High-Speed Internet: Practical Techniques and Theoretical Foundation

Large-Scale IP Traceback in High-Speed Internet: Practical Techniques and Theoretical Foundation Large-Scale IP Traceback in High-Seed Internet: Practical Techniques and Theoretical Foundation Jun Li Minho Sung Jun (Jim) Xu College of Comuting Georgia Institute of Technology {junli,mhsung,jx}@cc.gatech.edu

More information

Effect Sizes Based on Means

Effect Sizes Based on Means CHAPTER 4 Effect Sizes Based on Means Introduction Raw (unstardized) mean difference D Stardized mean difference, d g Resonse ratios INTRODUCTION When the studies reort means stard deviations, the referred

More information

Spike-Based Sensing and Processing: What are spikes good for? John G. Harris Electrical and Computer Engineering Dept

Spike-Based Sensing and Processing: What are spikes good for? John G. Harris Electrical and Computer Engineering Dept Spike-Based Sensing and Processing: What are spikes good for? John G. Harris Electrical and Computer Engineering Dept ONR NEURO-SILICON WORKSHOP, AUG 1-2, 2006 Take Home Messages Introduce integrate-and-fire

More information

A MOST PROBABLE POINT-BASED METHOD FOR RELIABILITY ANALYSIS, SENSITIVITY ANALYSIS AND DESIGN OPTIMIZATION

A MOST PROBABLE POINT-BASED METHOD FOR RELIABILITY ANALYSIS, SENSITIVITY ANALYSIS AND DESIGN OPTIMIZATION 9 th ASCE Secialty Conference on Probabilistic Mechanics and Structural Reliability PMC2004 Abstract A MOST PROBABLE POINT-BASED METHOD FOR RELIABILITY ANALYSIS, SENSITIVITY ANALYSIS AND DESIGN OPTIMIZATION

More information

C-Bus Voltage Calculation

C-Bus Voltage Calculation D E S I G N E R N O T E S C-Bus Voltage Calculation Designer note number: 3-12-1256 Designer: Darren Snodgrass Contact Person: Darren Snodgrass Aroved: Date: Synosis: The guidelines used by installers

More information

Re-Dispatch Approach for Congestion Relief in Deregulated Power Systems

Re-Dispatch Approach for Congestion Relief in Deregulated Power Systems Re-Disatch Aroach for Congestion Relief in Deregulated ower Systems Ch. Naga Raja Kumari #1, M. Anitha 2 #1, 2 Assistant rofessor, Det. of Electrical Engineering RVR & JC College of Engineering, Guntur-522019,

More information

Comparing Dissimilarity Measures for Symbolic Data Analysis

Comparing Dissimilarity Measures for Symbolic Data Analysis Comaring Dissimilarity Measures for Symbolic Data Analysis Donato MALERBA, Floriana ESPOSITO, Vincenzo GIOVIALE and Valentina TAMMA Diartimento di Informatica, University of Bari Via Orabona 4 76 Bari,

More information

Managing specific risk in property portfolios

Managing specific risk in property portfolios Managing secific risk in roerty ortfolios Andrew Baum, PhD University of Reading, UK Peter Struemell OPC, London, UK Contact author: Andrew Baum Deartment of Real Estate and Planning University of Reading

More information

A New Programmable RF System for System-on-Chip Applications

A New Programmable RF System for System-on-Chip Applications Vol. 6, o., April, 011 A ew Programmable RF System for System-on-Chip Applications Jee-Youl Ryu 1, Sung-Woo Kim 1, Jung-Hun Lee 1, Seung-Hun Park 1, and Deock-Ho Ha 1 1 Dept. of Information and Communications

More information

Single Supply Op Amp Circuits Dr. Lynn Fuller

Single Supply Op Amp Circuits Dr. Lynn Fuller ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Single Supply Op Amp Circuits Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 146235604 Tel (585)

More information

A 2 Gbps to 12 Gbps Wide-Range CDR with Automatic Frequency Band Selector

A 2 Gbps to 12 Gbps Wide-Range CDR with Automatic Frequency Band Selector JOURNAL OF ELECTRONIC SCIENCE AND TECHNOLOGY, VOL. 10, NO. 1, MARCH 2012 67 A 2 Gbps to 12 Gbps Wide-Range CDR with Automatic Frequency Band Selector Chao-Ye Wen, Zhi-Ge Zou, Wei He, Jian-Ming Lei, and

More information

LOW POWER MULTIPLEXER BASED FULL ADDER USING PASS TRANSISTOR LOGIC

LOW POWER MULTIPLEXER BASED FULL ADDER USING PASS TRANSISTOR LOGIC LOW POWER MULTIPLEXER BASED FULL ADDER USING PASS TRANSISTOR LOGIC B. Dilli kumar 1, K. Charan kumar 1, M. Bharathi 2 Abstract- The efficiency of a system mainly depends on the performance of the internal

More information

An important observation in supply chain management, known as the bullwhip effect,

An important observation in supply chain management, known as the bullwhip effect, Quantifying the Bullwhi Effect in a Simle Suly Chain: The Imact of Forecasting, Lead Times, and Information Frank Chen Zvi Drezner Jennifer K. Ryan David Simchi-Levi Decision Sciences Deartment, National

More information

Modeling and Simulation of an Incremental Encoder Used in Electrical Drives

Modeling and Simulation of an Incremental Encoder Used in Electrical Drives 10 th International Symosium of Hungarian Researchers on Comutational Intelligence and Informatics Modeling and Simulation of an Incremental Encoder Used in Electrical Drives János Jób Incze, Csaba Szabó,

More information

Chapter 6. CMOS Class-E Power Amplifier

Chapter 6. CMOS Class-E Power Amplifier Chapter 6 CMOS Class-E Power Amplifier 6.0 Introduction Last few years have seen an increase in the popularity of the wireless communication systems. As a result, the demand for compact, low-cost, and

More information

DEGREE: Bachelor in Biomedical Engineering YEAR: 2 TERM: 2 WEEKLY PLANNING

DEGREE: Bachelor in Biomedical Engineering YEAR: 2 TERM: 2 WEEKLY PLANNING SESSION WEEK COURSE: Electronic Technology in Biomedicine DEGREE: Bachelor in Biomedical Engineering YEAR: 2 TERM: 2 WEEKLY PLANNING DESCRIPTION GROUPS (mark X) SPECIAL ROOM FOR SESSION (Computer class

More information

High Intensify Interleaved Converter for Renewable Energy Resources

High Intensify Interleaved Converter for Renewable Energy Resources High Intensify Interleaved Converter for Renewable Energy Resources K. Muthiah 1, S.Manivel 2, Gowthaman.N 3 1 PG Scholar, Jay Shriram Group of Institutions,Tirupur 2 Assistant Professor, Jay Shriram Group

More information

High-Speed Electronics

High-Speed Electronics High-Speed Electronics Mentor User Conference 2005 - München Dr. Alex Huber, hubera@zma.ch Zentrum für Mikroelektronik Aargau, 5210 Windisch, Switzerland www.zma.ch Page 1 Outline 1. Motivation 2. Speed

More information

Interconnection Network of OTA-based FPAA

Interconnection Network of OTA-based FPAA Chapter S Interconnection Network of OTA-based FPAA 5.1 Introduction Aside from CAB components, a number of different interconnect structures have been proposed for FPAAs. The choice of an intercmmcclion

More information

ACKNOWLEDGEMENTS. giving me a good opportunity to work in his group at OSU. He has been a constant

ACKNOWLEDGEMENTS. giving me a good opportunity to work in his group at OSU. He has been a constant i ACKNOWLEDGEMENTS First and foremost, I would like to thank my advisor Dr. Un-Ku Moon for giving me a good opportunity to work in his group at OSU. He has been a constant source of guidance and support

More information

Case Study Competition 2013. Be an engineer of the future! Innovating cars using the latest instrumentation!

Case Study Competition 2013. Be an engineer of the future! Innovating cars using the latest instrumentation! Case Study Competition 2013 Be an engineer of the future! Innovating cars using the latest instrumentation! The scenario You are engineers working on a project team that is tasked with the development

More information

Objectives The purpose of this lab is build and analyze Differential amplifiers based on NPN transistors (or NMOS transistors).

Objectives The purpose of this lab is build and analyze Differential amplifiers based on NPN transistors (or NMOS transistors). 1 Lab 03: Differential Amplifiers (BJT) (20 points) NOTE: 1) Please use the basic current mirror from Lab01 for the second part of the lab (Fig. 3). 2) You can use the same chip as the basic current mirror;

More information

On Multicast Capacity and Delay in Cognitive Radio Mobile Ad-hoc Networks

On Multicast Capacity and Delay in Cognitive Radio Mobile Ad-hoc Networks On Multicast Caacity and Delay in Cognitive Radio Mobile Ad-hoc Networks Jinbei Zhang, Yixuan Li, Zhuotao Liu, Fan Wu, Feng Yang, Xinbing Wang Det of Electronic Engineering Det of Comuter Science and Engineering

More information

Objective. To design and simulate a cascode amplifier circuit using bipolar transistors.

Objective. To design and simulate a cascode amplifier circuit using bipolar transistors. ascode Amplifier Design. Objective. o design and simulate a cascode amplifier circuit using bipolar transistors. Assignment description he cascode amplifier utilises the advantage of the common-emitter

More information

Analog signals are those which are naturally occurring. Any analog signal can be converted to a digital signal.

Analog signals are those which are naturally occurring. Any analog signal can be converted to a digital signal. 3.3 Analog to Digital Conversion (ADC) Analog signals are those which are naturally occurring. Any analog signal can be converted to a digital signal. 1 3.3 Analog to Digital Conversion (ADC) WCB/McGraw-Hill

More information

LM741. Single Operational Amplifier. Features. Description. Internal Block Diagram. www.fairchildsemi.com

LM741. Single Operational Amplifier. Features. Description. Internal Block Diagram. www.fairchildsemi.com Single Operational Amplifier www.fairchildsemi.com Features Short circuit protection Excellent temperature stability Internal frequency compensation High Input voltage range Null of offset Description

More information

Figure 1. Diode circuit model

Figure 1. Diode circuit model Semiconductor Devices Non-linear Devices Diodes Introduction. The diode is two terminal non linear device whose I-V characteristic besides exhibiting non-linear behavior is also polarity dependent. The

More information

Step Response of RC Circuits

Step Response of RC Circuits Step Response of RC Circuits 1. OBJECTIVES...2 2. REFERENCE...2 3. CIRCUITS...2 4. COMPONENTS AND SPECIFICATIONS...3 QUANTITY...3 DESCRIPTION...3 COMMENTS...3 5. DISCUSSION...3 5.1 SOURCE RESISTANCE...3

More information

Design of Two-Stage CMOS Op-Amp and Analyze the Effect of Scaling

Design of Two-Stage CMOS Op-Amp and Analyze the Effect of Scaling Design of Two-Stage CMOS Op-Amp and Analyze the Effect of Scaling Amana Yadav Department of Electronics and Communication Engineering, FET-MRIU, Faridabad, Haryana Abstract:- A method described in this

More information

Safety evaluation of digital post-release environment sensor data interface for distributed fuzing systems

Safety evaluation of digital post-release environment sensor data interface for distributed fuzing systems Safety evaluation of digital ost-release environment sensor data interface for distributed fuzing systems 57 th Fuze Conference, Newark, NJ Wednesday, July 30 th, 2014 Oen Session IIIA, 3:20 PM S. Ebenhöch,

More information

A CMOS Clock Recovery Circuit for 2.5-Gb/s NRZ Data

A CMOS Clock Recovery Circuit for 2.5-Gb/s NRZ Data 432 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 3, MARCH 2001 A CMOS Clock Recovery Circuit for 2.5-Gb/s NRZ Data Seema Butala Anand and Behzad Razavi, Member, IEEE Abstract This paper describes

More information

Evaluating AC Current Sensor Options for Power Delivery Systems

Evaluating AC Current Sensor Options for Power Delivery Systems Evaluating AC Current Sensor Options for Power Delivery Systems State-of-the-art isolated ac current sensors based on CMOS technology can increase efficiency, performance and reliability compared to legacy

More information

CHARGE pumps are the circuits that used to generate dc

CHARGE pumps are the circuits that used to generate dc INTERNATIONAL JOURNAL OF DESIGN, ANALYSIS AND TOOLS FOR CIRCUITS AND SYSTEMS, VOL. 1, NO. 1, JUNE 2011 27 A Charge Pump Circuit by using Voltage-Doubler as Clock Scheme Wen Chang Huang, Jin Chang Cheng,

More information

TS321 Low Power Single Operational Amplifier

TS321 Low Power Single Operational Amplifier SOT-25 Pin Definition: 1. Input + 2. Ground 3. Input - 4. Output 5. Vcc General Description The TS321 brings performance and economy to low power systems. With high unity gain frequency and a guaranteed

More information

Storage Basics Architecting the Storage Supplemental Handout

Storage Basics Architecting the Storage Supplemental Handout Storage Basics Architecting the Storage Sulemental Handout INTRODUCTION With digital data growing at an exonential rate it has become a requirement for the modern business to store data and analyze it

More information

Analysis on the Balanced Class-E Power Amplifier for the Load Mismatch Condition

Analysis on the Balanced Class-E Power Amplifier for the Load Mismatch Condition Analysis on the Class-E Power Amplifier for the Load Mismatch Condition Inoh Jung 1,1, Mincheol Seo 1, Jeongbae Jeon 1, Hyungchul Kim 1, Minwoo Cho 1, Hwiseob Lee 1 and Youngoo Yang 1 Sungkyunkwan University,

More information