Modeling Considerations and Performance Estimation of Single Carbon Nano Wall based Field Effect Transistor by 3D TCAD Simulation Study

Transcription

1 Transactions of the Materials Research Society of Japan 35[3] (2010) Modeling Considerations and Performance Estimation of Single Carbon Nano Arkadiusz Malinowski 1,2,3, Masaru Hori 1, Makoto Sekine 1, Wakana Takeuchi 1, Lidia Lukasiak 2, Andrzej Jakubowski 2 and Daniel Tomaszewski 3 1 Nagoya University, C3-1 (631) Furo-cho, Chikusa-ku, Nagoya , Japan Fax: , m_arkadi@nuee.nagoya-u.ac.jp 2 Warsaw University of Technology, Koszykowa 75, Warsaw , Poland 3 Institute of Electron Technology, Al. Lotnikow 32/46, Warsaw , Poland A technology of manufacturing of carbon nano-wall films (CNWs) as well as a methodology for control of their properties are briefly described. Short channel effects (SCEs) are discussed. Single carbon nano-wall field effect transistor (SCNWFET) is proposed and modeling considerations using technology computer aided design (TCAD) software are explained. Device performance estimation and immunity to SCEs are given. Basic electrical characteristics and parameters important for application in integrated circuits are discussed. Key words: graphene, carbon nano-wall, field effect transistor, short channel effects, TCAD modeling 1. INTRODUCTION In order to keep up with the frantic pace imposed by Moore s law, the linear dimension of transistors has been reduced by half every three years. The channel length has been progressively reduced from 10 µm in 1960 s (the sub-micron dimension barrier was overcome in the early 1980 s) to 32 nm in However, further scaling down bulk CMOS into future technology generations will face a number of significant challenges [1]. 2. SHORT CHANNEL EFFECTS A MOSFET device is considered to be short when the channel length is the same order of magnitude as the depletion layer width of the source and drain junction. As the channel length is reduced to increase both the operation speed and the number of components per chip, the so-called short channel effects arise. The SCEs are attributed to two physical phenomena : 1) the limitation imposed on electron drift characteristics in the channel, 2) the modification of the threshold voltage due to the shortening channel length. In particular five different short channel effects can be distinguished : 1) drain-induced barrier lowering (DIBL) and punchthrough, 2) surface scattering, 3) velocity saturation. 4) impact ionization, 5) hot electrons. In order to counteract SCEs in the aggressively scaled gates the channel must receive higher dopant levels, causing threshold voltage to rise and slowing down the transistor. On the other hand high channel doping is inherently entailing random dopant fluctuations (RDF) in the channel area causing manufacturing yield reduction. RDF has been found by Intel as one of the most critical sources of the variation of transistors electrical parameters [2]. This will involve implementation into manufacturing of new structures such as FinFET for specific applications at the 22 nm or 15nm technology generation eventually. FinFET has a very thin Si fin wrapped around by the gate, thus high doping is not required. That way undesired SCEs can be minimized. A related challenge is to sustain scaling of CMOS logic technology to and beyond 16 nm. Although Intel remains on the Moore s Law pace in terms of contacted gate pitch scaling, with a 112.5nm pitch, shrinking is no longer delivering the speed improvements seen in past generations. With smaller dimensions, less material can be deposited to add strain. One approach to sustaining performance gains as CMOS scaling matures in the next decade is to replace the strained silicon MOSFET channel with an alternate material offering a higher quasi-ballistic carrier velocity and higher mobility than strained silicon. Candidate materials include strained Ge, SiGe, a variety of III-V compound semiconductors, and carbon-based materials such as carbon nano tubes (CNTs), graphene, and graphene nano ribbons (GNRs). Promising electrical parameters of CNT and GNR based FETs have been presented in [3] and [4], however they face significant manufacturing issues. The major question that has challenged CNT MOSFET for some time is lack of growth process to control placement, chirality, conductivity, diameter, and energy bandgap. 3. CARBON NANO-WALLS Recently nano-carbon related materials have attracted a lot of interest. Especially, attention has been focused on graphene, a two-dimensional (2D) honeycomb structure of carbon. Graphene makes graphite, when stacked in layers, and carbon nano-walls [5, 6], when standing vertically on the substrate (Fig. 1). Fig. 1. Carbon nano-wall (left), graphene sheets (middle), graphene (right). 669

2 670 Modeling Considerations and Performance Estimation of Single Carbon Nano It has been reported that 2D monocrystalline graphitic films with a thickness of a few atoms exhibit a strong ambipolar electric field such that electrons and holes exist in concentrations of up to cm -2 and with room-temperature mobilities up to cm 2 /Vs [7]. Carbon nano-walls which are graphene sheets standing vertically on the substrate also possess excellent electrical properties such as: high carrier densities, high carrier mobilities and high sustainable current. Thus field effect transistor with carbon nano walls playing a role of channel can be a promising candidate for future generation FET devices. 4. CNWS MANUFACTURING In order to manufacture CNW film for FET devices we used PECVD technique with radical injection based on a mixture of C 2 F 6 with H 2 (Fig. 2) [8]. 5. PROPERTIES AND CONDUCTION CONTROL Since CNW in CNWFET transistor plays the role of a channel, transistor performance will strictly depend on CNW properties. Thus the ability to control CNW electrical properties is crucial. 5.1 Electrical properties In order to control the electrical properties of CNWs additional N 2 gas has to be introduced into the CCP region at flow rates of 1-15 sccm (Table I). Table I. Control of CNW electrical properties by means of nitrogen flow [5]. N 2 flow rate [sccm] Carrier concentration [ cm -3 ] The behavior of carrier concentration is considerably similar to that of N concentration. When N 2 /O 2 gas mixture was used during CNW growth we observed that the carrier and N concentration were almost the same as that of the N 2 CNW grown without the O 2 addition. The electrical properties of CNWs can be controlled by the addition of N 2 /O 2 mixture to the C 2 F 6 /H 2 plasma without deteriorating crystallinity. Fig. 2. Radical Injection Plasma Enhanced CVD System. Our system consists of a parallel-plate VHF (100MHz) capacitively coupled plasma (CCP) region and a surface-wave-excited microwave H 2 plasma (H 2 SWP) as a remote H radical source. C 2 F 6 is introduced into the VHF-CCP region. H 2 is introduced into the microwave SWP region, and H radicals are injected into the VHF-CCP region. The VHF power of the CCP and the microwave power of the SWP can be 270 and 250 W, respectively. Mirror-polished insulating quartz without any catalyst is the substrate used for the growth experiments performed for evaluating the electrical properties of CNW films. During the CNW growth, the quartz substrate is heated using a carbon heater. The surface temperature is approximately 600 C. The flow rates of C 2 F 6 and H 2 are maintained at 50 and 100 SCCM, respectively and the total gas pressure is 160 Pa. Carbon nanowalls obtained by this technique are presented in Fig Conduction CNW manufacturing without any additional gases results in undoped CNW films. The Hall coefficient of the undoped CNW is positive, thus implying p-type conduction. Key factor in future FET transistor application of the graphene layers is the ability to control the conduction type. P-type and n-type transistors are required in order to design CMOS integrated circuits. In the manufactured CNW films with the N 2 addition it has been observed, that the resistivity decreases when the N 2 flow rate increases. The measured Hall coefficient was negative, implying n-type conduction (Table II). Table II. Hall coefficient vs. nitrogen flow [5]. N 2 flow rate [sccm] Hall coefficient [cm -3 C -1 ] When O 2 has been used we observed that it is also possible to control the structure of the CNWs. Oxygen atoms remove impurities thus resulting in highly graphitized CNWs. This is an important issue since the graphene layer is located in the CNWFET channel area responsible for the final device performance. Any impurity can have an effect on output current as well as on maximum operation frequency. Fig. 3. Carbon nano-walls. 6. MODELING AND SIMULATIONS CNWs can be a candidate material for the future MOS devices, however, we need enormous research and development work even for making a test device. In such initial stage of the research, simulation is a powerful tool to steer the experiments. The modeling allows for significant cost reduction while making device evaluation possible, because practical

3 A. Malinowski et al. Transactions of the Materials Research Society of Japan 35[3] (2010) 671 experiments can be reduced to the necessary minimum. It allows also for reduction of the time-to-market period [9] SCE In order to evaluate SCNWFET susceptibility to SCE the voltage dopant transformation (VDT) model has been used [10]. Using the structure parameters we have computed the so called electrostatic integrity (EI) coefficient [11], which is a measure of device susceptibility to short-channel effects. In the case of Double-Gate (DG) MOSFETs it is defined as: EI 2 1 tcnw / 4 tox tcnw / 2 SCNWFET = Lel Lel Lel (1) Fig. 4b) Comparison of SCE in FinFET and SCNWFET in single nanometer regime. L el denotes the electrical (effective) channel length. Other variables in (1) have their standard meaning. The numerical values of the SCE effects are directly proportional to EI coefficient (2). SCE = ε Si 0.64 EI V bi ε ox For calculations the following data has been taken into account: 1) CNW thickness (t CNW ) equals 2nm the same as for fin thickness in FinFET. In case of MOSFET 2nm corresponds to S/D junction depth; 2) CNW dielectric permittivity (ε CNW ) has been assumed as 1.4 and 11.9 for Silicon; 3) in all cases oxide thickness and oxide permittivity (t OX, ε OX ) equals 1nm and 24 respectively; 4) built-in voltage (V bi ) has been assumed 0.9V. (2) Comparison of SCEs in bulk MOSFET, FinFET and SCNWFET is shown in Figs 4a and 4b. It can be observed that field effect transistor with single carbon nano-wall in the channel area is much less susceptible to SCEs than bulk MOSFET or even gate FinFET (Fig. 4a). It can be also stated that nano-carbon transistor technology has a great potential for further scaling down for next technology generations (Fig. 4b) MAXIMUM CUTOFF FREQUENCY We have evaluated SCNWFET theoretical maximum frequency using formula (3) and the data presented in Table III. 1 µ f (3) T = ( V ) 2 GS V TH 2 π L Table III. Data taken during maximum frequency evaluation. Factor Denot. Value Unit Source Electron mobility Channel length Gate-source potential Threshold voltage µ cm 2 /V s Literature L 6 24 nm Assumption V GS 1 V Assumption V TH 0.4 V Calculated using TCAD Results of this evaluation shown in Fig. 5 indicate that CNWFET s high maximum frequency can help ICs to enter THz era according to the Moore s law. Fig. 4a) SCE in bulk MOSFET, FinFET and SCNWFET as a function of gate length. Fig. 5. SCNWFET maximum theoretical frequency as a function of channel length.

4 672 Modeling Considerations and Performance Estimation of Single Carbon Nano During 2009 International Electron Devices Meeting a graphene field effect transistor operating at 50 GHz cutoff frequency has been presented by IBM [12]. Moreover, IBM is confident that 100 GHz transistors should soon be feasible SIMULATION TOOL In order to model and to obtain preliminary evaluation of our project we have chosen integrated modeling environment of Sentaurus Workbench by Synopsys. Sentaurus Workbench is a complete graphical environment for creating, managing, executing, and analyzing the technology computer-aided design (TCAD) simulations [13]. A great advantage of Sentaurus software is the ease of adding new material files as well as implementing user-defined physical models using C++ language MODELLING CHALLENGES Modeling such new and non-standard (non-silicon) devices, even using the latest releases of TCAD software is challenging and faces a lot of problems when standard MOS technology software is used. The main problems we have encountered can be divided into four main groups : 1) Carbon nano-walls representation Sentaurus Structure Editor [11] is not equipped with tools to define shapes like CNWs, 2) Graphene material file there is no material file for graphene in Sentaurus material database, 3) Meshing mesh generator engine has problems with meshing small edges, 4) Transport mechanism there is no proper model for carrier transport mechanism in CNWs. Transport mechanism in graphene sheets differs from mechanism in silicon Carbon nano-wall representation in TCAD Our solution to Carbon nano-wall representation in modeling software is based on a mathematical description of region shapes and approximations by the combinations of the standard shapes provided by Structure Editor (Fig. 6). The final CNW shape is obtained after Boolean operations on other shapes (Fig. 7). Fig. 6. SEM picture of CNWs and approach for their representation in TCAD software. Fig. 7. Carbon nano-wall representation in TCAD software Material file In order to investigate SCNWFET device performance we have created a new graphene material file using the data taken from literature [15, 16] and our measurements and experiments. The reliability of the obtained simulated data depends on material file content. The following data presented in Table IV have been introduced to the material file: Table IV. Graphene material file properties. Parameter Value Unit n i cm -3 N c cm -3 N v cm -3 E g 100 mev E g (W) 75 W -2 mev ε CNW µ e cm 2 /Vs µ h cm 2 /Vs χ CNW 4.5 ev φ CNW 4.55 ev Meshing The problem with meshing carbon nano-walls has been solved by the appropriate approach to TCAD representation of CNWs. CNW is divided into parts depending on the shape in close short range distance. In the next step those different parts are meshed separately using different meshing strategies [17] Transport mechanism Carrier transport mechanism in graphene sheets can be described adequately by using quantum transport (QT) based on Landauer-Buttiker approach and non-equilibrium Green s Function (NEGF). Unfortunately this model of transport is not incorporated in Sentaurus software. For this reason we have used hydrodynamic transport model. This model is used for the calculation of electrical characteristics of MOS transistors with gates scaled into the deep submicron regime [18]. 6.5 SCNWFET MODEL - REALISITC In order to examine carbon nano-walls areas a part of a field-effect transistor, a single carbon nano-wall FET (SCNWFET) model has been prepared as shown in Fig. 8. This approach is based on realistic CNW shapes being

5 A. Malinowski et al. Transactions of the Materials Research Society of Japan 35[3] (2010) 673 manufactured. gate voltage varying from -10 to 10V. One can see, that the device under test is normally on due to insufficient gate control. In the wide range of gate-source voltages there is current flow, especially when the gate-source voltage is zero. Based on those characteristics it is impossible to evaluate V TH voltage. We need a device with better gate control. It means we should be able to change the drain current over a wide range by gate voltage. In particular, we need to be able to turn off the transistor. Thus we need to consider a new device structure. Fig. 8. Idea of FET device based on manufactured CNW. Single carbon nano-wall (pink) is grown on the oxide (brown) forming substrate. Both ends of carbon nano-walls are terminated with golden contacts forming source and drain contacts. The gate dielectric (hafnium oxide) and the gate (poly-si) are surrounding SCNW along its length. In this case SCNW properties are as follows : 1) thickness 2nm (corresponds to 7 graphene sheets), 2) doping level cm -3, 3) type acceptor. 6.6 CNWFET MODEL - IDEAL In order to verify the concept of the CNWFET using the TCAD package, another device structure was designed with the Sentaurus tool. It is illustrated in Fig. 10. In this case we assume that we are able to manufacture a standing graphene sheet in the device channel area with the ideal shape in vertical and horizontal directions. In short range of CNW lengths this is a feasible assumption. It is worthwhile to mention that electrical conduction is carried out along the vertical walls of the device. It is very similar to the well-known FinFET structure [19] Electrical simulation The electrical simulations were carried out using the Sentaurus Device module. Electrical simulation is based on the solution of coupled Poisson and current continuity (for electron and holes) equations. Electrical simulations have been arranged in order to obtain output and transverse characteristics in saturation and non-saturation bias ranges. This approach allows for the extraction of the electrical parameters of the device. The simulated I-V output characteristics are shown in Fig. 9. Fig. 10. Idea of FET device based on ideal CNW for ULSI ICs application Electrical simulation This structure was simulated in the same manner as the previous one. Terminal conditions were as follows: source and substrate are grounded, drain voltage: 1V and 0.05V, respectively and gate voltage varying from 0 to 2V. The electrical transverse characteristics of the CNWFET is shown in Fig. 11. Fig. 9. Simulated SCNWFET output I-V characteristics. These characteristics have been obtained for the following terminal conditions: source and substrate are grounded, drain voltage: 1V and 0.05V, respectively and

6 674 Modeling Considerations and Performance Estimation of Single Carbon Nano Fig. 11. Simulated transverse I-V characteristics of the vertical CNWFET Evaluation of the electrical parameters of the device is presented in Table V. Table V. CNWFET electrical parameters. V DS [V] V TH [V] g m [µs] SS [mv/dec] This device exhibits a correct electrical behavior. Normally it is in the off-state. We observed an excellent subthreshold slope (SS) independent from V DS bias. Moreover, it has an almost ideal output conductance in saturation. Thus, it can be stated, that the concept of CNWFET seems very promising. 7. CONCLUSIONS A new class of carbon-based FET transistors have been found as future successors of MOSFETs and reliable candidate for future ULSI era. CNW excellent electrical properties will allow ICs to enter the THz era in accordance with Moore s law. In our paper we presented possible device performance. We also proposed a technology of manufacturing graphene layers and control of their conduction control. REFERENCES [1] The International Technology Roadmap for Semiconductors 2008 Update [2] Kuhn et al., Intel Technology Journal, Volume 12, Issue 2, 2008, pp [3] R. Martel et al., Appl. Phys. Lett. 73 pp (1998) [4] Yu-Ming Lin et al., Nano Lett., 2009, 9 (1), pp [5] Wu et al., Adv. Mater. (Weinheim, ger) 14, 64 (2002). [6] Hiramatsu et al., Jpn. J. Appl. Phys. 45,5522 (2006). [7] Takeuchi et al., Appl. Phys. Lett. 92, (2008) [8] Hiramatsu et al., Appl. Phys. Lett., Vol. 84, No.23, pp , [9] Arora MOSFET modeling for VLSI simulation, World Scientific Publishing, Singapore (2007) [10] Skotnicki et al., IEEE Trans. on Electron Devices, Vol. 9, 3 (1988) [11] Colinge J. P. (Ed.), FinFETs and Other Multi-Gate Transistors, Springer, 2008 pp. 4-7 [12] International Electron Devices Meeting Dec 7-9, 2009, Baltimore USA, [13] Sentaurus Device User Guide, Version C , June 2009 [14] Sentaurus Structure Editor User Guide, Version C , June 2009 [15] Han et al. PRL 98, (2007) [16] Fang et al. Appl. Phys. Lett. 91, (2007) [17] Sentaurus Mesh Generation Tools User Guide, Version C , June 2009 [18] Roberts et al., Energy-Momentum Transport Model Suitable for Small Geometry Silicon Device Simulation, COMPEL, vol. 9, no. 1, pp. 1 22, [19] Kawasaki, et al., Ext. Abs. the 7th International Workshop on Junction Technology, June 8-9, 2007, Kyoto, Japan, pp. 3-8 (Received April 9, 2010; Accepted July 23, 2010) 8. FUTURE WORKS Modeling such modern semiconductor devices like the presented CNWFET is not a trivial task. It requires new simulation approach. New material files as physical models for carrier transport are required. We will focus on further material file development as well as on optimization of the device structure in Sentaurus software. We will also design the analytical model of the carrier transport based on the Landauer-Buttiker (LB) formalism and non equilibrium Green's function (NEGF). Moreover, our future work will also be focused on manufacturing test structures of carbon nanowall FET devices. In the next step we will perform the measurements of I-V characteristics and extract the electrical parameters. Based on this we will propose a compact model of CNWFET which will allow for IC simulations.