Theoretical Aspects of Fault Isolation on High-Power DC Lines Using Resonant. DC/DC Converters

Transcription

1 Thortical Aspcts of Fault Isolation on High-Powr DC ins Using Rsonant DC/DC Convrtrs Dr Dragan Jovcic, School of Enginring, Univrsity of Abrdn, Abrdn, AB4 3UE, UK Tl d.jovcic@abdn.ac.uk and Profssor Boon Tck Ooi, Elctrical Enginring, McGill Univrsity, Montral, H3A A7, Canada, boon-tck.ooi@mcgill.ca. Abstract This papr invstigats DC fault currnt limiting and intrrupting capability of a multi MW rsonant DC/DC convrtr which is proposd for applications with High oltag Dirct Currnt (HDC systms. Th convrtr can b usd as a DC circuit brakr or as a multifunctional unit: DC transformr, rgulating lmnt and DC circuit brakr. Th study is primarily concrnd with th inhrnt convrtr rsponss, in th first svral millisconds aftr th fault, and prior to any controllr action. A dtaild convrtr dsign is givn to prvnt fault propagation through th convrtr vn for most svr faults on low voltag or high voltag trminals. Th analytical modlling provs that th convrtr will intrnally rduc powr transfr during fault conditions. Th simulation on PSCAD/EMTDC shows that convrtr oprats unintrruptd through most svr faults, th switch turn-off tim is not violatd and inhrnt stabilising proprtis prvnt any ovrvoltag or xtrm currnts. Th convrtr can rspond lik high-impdanc circuit on th unfaultd trminals. Th impact of unbalancd DC lin faults on a bipolar DC systm is also discussd. Th dtaild PSCAD tsts with a MW DC/DC convrtr intrconncting ±44k and ±5k DC lins dmonstrat th ability to prvnt fault propagation vn for most svr DC lin faults. Th intraction with othr HDC convrtrs in cas of faults is also dmonstratd. Indx Trms DC-DC powr convrsion, thyristor convrtrs, High oltag DC transmission.

2 I. INTRODUCTION All th HDC installations worldwid oprat as two trminal systms, but thr has bn significant incntiv for dvlopmnt of multitrminal HDC and HDC tapping []. Th latst HDC basd on SC convrtrs [] has bn applid in a dozn projcts and it is bing studid for dvlopmnt of high-powr DC grids for subsa systms in oil and rnwabl industris. In rcnt yars w hav sn an incrasing numbr and rating of DC powr sourcs, lik ful clls, photovoltaics, wind farms and nrgy storag lmnts that would idally b connctd to DC collcting grids at mdium and high voltag [3,4,5]. Th proposd Europan North Sa Suprgrid and DESERTEC concpt will b basd on high-powr DC ntworks. Th dvlopmnt of multitrminal HDC and DC ntworks will rquir significant furthr advancs in th two ky highpowr componnts: DC Circuit Brakr (CB and DC transformr. A DC circuit brakr nabls isolation of a faultd lin or a unit. A DC transformr can transform DC voltag lvls to maintain optimum costs and losss. Th fault protction is much mor challnging with DC than AC ntworks for th following rasons: thr ar no zro crossings of DC fault currnt, th sris impdanc (with SC basd convrtrs is vry small lading to vry stp ris of fault currnt, 3 intrrupting larg DC currnt causs svr ovrvoltags and 4 th quipmnt is usually mor snsitiv to ovrvoltags and ovrcurrnts. Thr ar no oprational CBs on HDC systms worldwid, xcpt for on vry low powr ground-rturn installation in Japan [6]. Th rsarchd tchnologis for DC CB [4-8] can b groupd in mchanical and solid stat solutions. Th mchanical DC circuit brakrs [6] consist of a convntional AC circuit brakr supplmntd with a paralll rsonant circuit. This solution dmands high ovrrating, but most importantly, it has long oprating tims (-ms and thrfor it will not b suitabl with SC basd HDC. In such long intrval, th fault currnt on SC systms will rach xtrmly high valus which will b byond intrrupting capability of circuit brakrs. Th hybrid topologis combin a mchanical switch with lctronics-drivn rsonant circuit but th oprating tims ar still too long for SC protction [7]. A futur DC ntwork basd on SC will nd som solid-stat DC CB. A singl lctronic switch (a GTO/IGBT may b stratgically locatd at DC lin nds and supplmntd with fast mchanical switchs [4]. Altrnativly th anti-paralll diods ar rplacd with symmtrical GTOs [5]. Ths solutions will hav fast DC fault-isolation capability but thy will hav high costs and losss. Assuming that GTO control raction tim is blow 5ms, bcaus of low sris impdanc with SC HDC systms th currnt will still ris at vry high lvls (abov pu bfor it is intrcptd. IGBT/GTOs typically hav pak intrruption capability of only around % of nominal currnt, and in practic this implis significant ovrrating in normal opration. ocating such switchs at all DC lins would b prohibitivly xpnsiv. A furthr significant issu with fast intrruption of DC fault currnt is th rsulting ovrvoltag [7]. Th DC fault currnt must b intrruptd in short intrval whil

3 th currnt magnitud is within th switch turn-off capability. Th ovrvoltags ar proportional to currnt drivativ and vry high nrgy surg arrstrs ar ndd with all solid-stat circuit brakrs [5,7]. In cass of long DC lins, th nrgy capability of convntional surg arrstrs may not b adquat and supplmntary nrgy dumps may b rquird. With traction drivs, th DC circuit brakr is commonly basd on thyristors which can tak largr fault currnts [8]. Howvr th complxity, costs and ovrrating ar high. Som DC/DC convrtrs will hav capability to limit th magnitud of fault currnt (bcaus of intrnal inductors but in most cass significant switch ovrrating is rquird to cop with fault conditions [5,9]. Th arospac industry studid som potntially usful proprtis of sris rsonant topologis undr fault conditions in th arly 98 s [], but othr drawbacks hav prvntd industry applications. Rcntly, a nw high-powr stp up/down DC/DC convrtr basd on rsonant circuits has bn proposd, and it has bn studid with a 5MW, 4k/8k application []. Th convrtr is capabl of achiving vry high stpping ratios at high powrs, without us of iron cor transformrs. This papr taks th rsonant topologis [] and studis dsign options to provid isolation of DC faults. Th aim is to provid controllabl convrtr opration undr xtrnal DC faults and to limit th intrnal variabls clos to ratd lvls. If thr is no significant ovrcurrnt or ovrvoltag undr faults, th spd of convrtr control action bcoms lss important. Assuming that th convrtr continus normal opration during faults it can b controlld to gradually rduc currnt ovr lonr tim priod, and vntually to bcom blockd to prmanntly isolat th fault. II. CONERTER TOPOOGY AND FAUT STUDIES A. High Powr Bidirctional DC transformr Figur shows th bidirctional vrsion of th high powr DC transformr []. It consists of two rsonant C circuits, back to back connctd and sharing a common capacitor. This topology uss bidirctional switchs and achivs fast powr rvrsal by rvrsing currnts in both circuits (I and I. A unidirctional vrsion would hav half th switchs, and slow powr rvrsal may b possibl with mchanical contactors. In stp up mod, th T and T thyristor pairs ar squntially fird at 5% duty ratio at f s switching frquncy, as shown in Figur. Th inductor crats a rsonanc with C r which nabls c voltag incrasing and zro-currnt turn on and off of T - T. All th switchs should hav rvrs blocking capability but circuit topology provids currnt commutation and thrfor thyristors ar suitabl. Th high voltag circuit rsonanc ( -C r nabls zro currnt switchings of T 5 -T 6. In stp down mod th oprating principl is similar, but T 3 -T 4 and T 7 -T 8 thyristors ar mployd instad. Th maximum oprating frquncy f smax is primarily dpndnt on th minimum turn off tim of low voltag switchs T offmin : 3

4 f s < fs max = /(4Toff min ( Onc f s is known, th principal convrtr dsign quation is: I /( = C f r, ( ( s whr manipulation in th switching frquncy f s, nabls linar control. From ( w conclud that th convrtr powr transfr is dtrmind by C r and f s. Assuming opration at th bordr of discontinuous mod, th inductor is dtrmind: ( / π f C s r (3 Th high voltag switchs ar synchronizd to oprat at th sam frquncy f s, but thr is frdom in choosing firing angl for T 5 -T 8 (α u for stp up and α d for stp down. Th high voltag circuit inductors ( u for stp up and d for stp down ar smallr than and lss critical for th opration. Th inductor for stp down mod, d and th firing angl α d can b dtrmind using th dsign study in []. Th dsign of stp-up inductor u is influncd by th high-voltag faults, as dscribd in sction I. A PI fdback controllr typically manipulats f s to rgulat DC currnt (ithr I or I in a fdback mannr. B. Tsts systm Th tst systm is a high-powr MW DC/DC convrtr intrconncting ±44k and ±5k DC (stpping ratio n=5.7. Such convrtr may b utilizd in conncting a low voltag DC fdr to xisting ±5k HDC lins, as rquird in futur DC ntworks. A dtaild tst systm modl is dvlopd on PSCAD platform and all paramtrs ar in th Appndix. C. Fault studis W invstigat th worst cas zro-impdanc faults at convrtr trminals and ( <. Thr ar four possibl fault scnarios: A. Fault on for stp-up opration ( to transfr. B. Fault on for stp-up opration ( to transfr. C. Fault on for stp-down opration ( to transfr D. Fault on for stp-down opration ( to transfr. 4

5 Considring that th convrtr uss rvrs blocking switchs, th faults A. and D. ar trivial sinc thy ar occurring upstram of th convrtr, and thy will only intrrupt powr transfr through th convrtr. Th faults B. and C. ar known to disturb opration of typical convrtrs and thy will b furthr studid in dtail. If thr is a fault at on of th trminals, th tim-domain convrtr rspons will b undrgoing four squntial stags: Stag. Th initial transint lasting in th ordr of fw ms, (- cycls at around 5Hz switching frquncy. Th intrnal convrtr variabls xprinc pak fault valus, and controllr is inactiv. Stag. Aftr svral cycls, a nw stady-stat opration undr fault conditions is stablishd (if xists. Th stags and dfin th convrtr s natural rspons to faults sinc th controllr will b inactiv in this priod. Stag 3. Considring all dlays in th transducrs, procssing and firing circuits, it is consrvativly assumd that a normal controllr rspons tim will b around -3ms. Aftr this dlay, th controllr can rduc oprating frquncy or intrrupt firing pulss in lin with fault managmnt stratgy [5]. Stag 4. In cas that th fault is prmannt th convrtr will rduc th oprating frquncy to in stag 3, and convrtr is blockd. In stag 4, th off-load mchanical switchs opn and th fault isolation is complt. Th fault controllr dsign is a known concpt [5] and thrfor stags 3 and 4 ar not considrd in this rsarch. Th dsign is primarily concrnd with stags and assuming that th controllr is inactiv, i.. oprating frquncy f s is constant. III. CONERTER DESIGN FOR FAUTS (FAUT C In ordr to provid controllabl opration undr fault conditions, two principal conditions should b mt:. Th circuit-allowd switch turn-off tim (T off for low voltag circuit, and T off for high voltag thyristors should b largr than th minimum turn off tim for th particular switchs. For th mployd Silicon Powr thyristors T offmin =4µs. If this condition is violatd, thr will b unwantd thyristor turn on, c will collaps, and fault will propagat through th convrtr.. Th magnitud of all convrtr variabls should b within th ratd limits for th lctronic componnts. It is crucial to monitor pak switch currnts (I pk and I pk and pak capacitor voltag ( cpk. Figur 3 shows th PSCAD simulation of first two cycls aftr a most svr fault on low voltag sid ( :88k->k. For comparison, th capacitor voltag is shown for th cas of fault ( c and in th cas of no fault ( nf c. Th low voltag circuit conducts in A-D and th high voltag circuit conducts in B-C intrval, howvr dpnding on th circuit conditions point C can occur bfor or aftr point D. Th quations for capacitor voltag c and currnt I in intrval A-B (t A <t<t B can b drivd using th circuit analysis ruls as dscribd in [9,]: 5

6 6 cos( ( t ca c ω = (4 sin( / ( t Z I ca ω = (5 whr ca is th initial valu of c at th instant of rotation. As th first approximation, it can b assumd as ca =-. Th low voltag circuit constants ar /(, / 4 C C Z r = = ω. In th B-D intrval (t B <t<t D both high voltag and low voltag circuits will b conducting implying that thr ar thr dynamic quations. Thy can b solvd in tim domain as discussd in []: sin( cos( t Z I t B cb c ω ω = (6 = cos( sin( t I t Z t I B cb ω ω (7 cos( sin( t I Z t t I B cb = ω ω (8 whr /( (, /( ( 4 r d d r d d C C Z = = ω, and it is assumd that a local tim axis starts at point B (t B <t<t D. If point C falls aftr D, th quations in D-C intrval, ar: sin( cos( ( t I Z t D cd c ω ω = (9 sin( / ( cos( t Z t I I cd D ω ω = ( assuming /(, / 4 C C Z d r d = = ω and a local tim axis (t D <t<t C.

7 Th c zro-crossing and th pak currnt I pk will typically occur at around 9 o, which falls in A-B intrval, sinc high voltag thyristors ar fird typically around α d = o. Thrfor, th turn off tim T off, which is dfind by th nxt c zrocrossing (point H can b calculatd using (4: ( cos ( /( ω T off = / (t A <t<t B ( If rducs, it is vidnt from ( that th turn off tim rducs, howvr this rduction is vry small. In th practical systm in Figur 3, point H marginally movs to th lft. Figur 4 shows th prcntag rduction in turn off tim T off /T off as th function of stpping ratio n= / (3<n<, for a zro-impdanc fault on. It is sn that in th worst cas (low stpping ratio th rduction in T off is only 5%. Normally a much largr margin will b incorporatd whn slcting oprating frquncy in (. Using (5 w dduc that pak currnt I pk will b largr than in no-fault cas I nf pk : nf Ipk = Cr /( 4 > Ipk = ( Cr /(4 (t A <t<t B ( Th largst fault currnt incras, i.. if stpping ratio is n=3, is calculatd to b around 5%, as sn in Figur 4. Th tst systm has n=5.7, and th incras is around % which is consistnt with PSCAD rsults in Figur 3. W can conclud that th switchs will radily tolrat th abov fault currnt lvl during stags and. Using (4 w driv that in A-B intrval th capacitor voltag c is always highr than in no-fault cas nf c : nf < c c < (t A <t<t B (3 Using (3 w also concludd that c undr fault conditions lads th unfaultd voltag curv (although by a small amount. As a consqunc it is clar that cb > nf cb, and this will hav crucial impact in rducing I. Using (4 and (5 w dtrmin th variabls at th instant of firing high voltag thyristors in point B: cb = c (α d, I B =I (α d, which is thn rplacd in (6-(8 to calculat I. It can b radily shown that I will b lowr as rducs. Th abov conclusion can b simply analytically confirmd by xprssing th I drivativ with rspct to voltag using (8: ( cos( ω t di sin( ω t ( ( t cos sin d = d αd d Z Z α (t B <t<t D (4 7

8 Th abov drivativ is always positiv, and thrfor currnt I will b rducing as th voltag rducs. Altrnativly, th sam conclusion can b drivd graphically from Figur 3, considring th surfac ara btwn cr and.in B-C intrval. Th nrgy balanc on inductor d implis that this ara is always symmtrical around and thrfor cb > nf cb implis that I is smallr undr faults. If th convrtr dynamics ar nglctd, w can mploy th basic stady-stat quation (, and assuming high stpping ratio is high (( - /, it is similarly confirmd that currnt I rducs as rducs. This inhrnt stabilising fdback loop is highly important proprty of this convrtr family, sinc it rstricts powr flow into th convrtr during faults. In ordr to study capacitor pak voltag cpk undr faults w nd to solv (4, (6 and (9 in itrativ mannr to dtrmin a balancd oprating point. Howvr w can simplify study considring th xtrm fault condition =, and assuming that I =, as concludd abov. Consquntly, w can us (4 for th whol A-D intrval and w dduc that th pak capacitor voltag cpk will stay unchangd: cpk = cpk nf = c (π=- ca. (5 As sn in Figur 3, whil c marginally incrass in A-B intrval, in B-C intrval I rducs implying that lss nrgy is transfrrd to capacitor C r. and c lowrs. It is vry important proprty that an intrnal stabilizing loop prvnts ovrvoltag undr fault conditions. A furthr consqunc of rducd I in B-C intrval is that th turn off tim in high-voltag circuit (T off actually incrass aftr th fault, nabling bttr commutation margin of high-voltag switchs. Th itrativ mthods ar now applid to (4-( (and vrifid using dtaild PSCAD tsts in ordr to dtrmin th magnitud of th crucial variabls undr faults of varying svrity. Figur 5a shows th valus for th I, cpk and I as th function of voltag. It is sn that th currnt I marginally incrass and th pak capacitor voltag cpk rmains unchangd. Th currnt on unfaultd sid I, proportionally rducs as rducs. Th convrtr bcoms opn circuit on high-voltag sid for xtrm faults on low voltag sid, although it can b dmonstratd currnt I cannot rduc to vn with =. Th vry small valu of I currnt undr = opration can b absorbd by intrnal convrtr losss. 8

9 I. CONERTER DESIGN FOR FAUTS (FAUT B A. Symmtrical fault Figur 6 shows th transint rspons for a high voltag fault ( :5k -> k in stp up mod. Th capacitor voltag wavform is shown for fault cas c and no-fault cas nf c, and it is sn that c will not b affctd until th nxt intrval B-C whn high-voltag thyristors ar conducting. Th sam quations (4-( dscrib th circuit xcpt that both currnts (I and I hav opposit sign. Using (6 it can b nf shown that th wavform for c also lads th unfaultd voltag curv. Consquntly, ca > ca, th voltag ca is closr to undr faults, and this implis that I rducs. Thrfor, th sam intrnal stabilizing mchanism oprats in fault B, which rducs currnt on th opposit trminals. Th pak capacitor voltag cpk also has stabilizing fdback loop that prvnts any ovrvoltag bcaus of rducd powr input through I. It can b obsrvd from Figur 6 that th turn off tim T off actually incrass undr th fault, xcpt in th first cycl immdiatly aftr th fault, whr it is significantly rducd. This first post-fault cycl bcoms crucial for commutation failur and for convrtr dsign. Undr th = faults, th zro-crossing of voltag c will mov to B-C intrval (whn high-voltag switchs ar conducting considring that c is symmtrical around. Thrfor th high voltag circuit paramtrs (C r - u will dfin th turn off tim in th low voltag circuit (T off. Thr ar two dsign options to provid sufficint T off :. Incrasing th firing angl for high voltag thyristors (α u. This simpl approach howvr implis incras in pak capacitor voltag ( cpk and may also lad to stability issus. Simulation studis indicat that a valu of around α u =5-6dg is a good compromis.. Calculating a suitabl u. To simplify study, w assum that influnc of I can b nglctd during th fault =, sinc it has bn provn that I will b rducing. Undr th assumptions I = and =, th quations for th tim intrval to c zro crossing and th pak currnt I pk can b drivd using (: T off = Cr ( αu π ucr π / (6 I pk = cpk Cr /( 4u (7 9

10 Th first trm in (6 is typically small sinc α u is clos to π. Thrfor th allowd turn off tim is approximatly ¼ of th u -C r rsonant cycl. Undr ths assumptions (6 is similar to ( and u should b comparabl siz to. In our tst systm is slctd with a considrabl margin in ( and (3, whras u is chosn to tightly satisfy (6 and thrfor u is calculatd as u.5. Th quation (7 can b usd to stimat th worst cas pak fault currnt I pk. Considring th chosn u =4mH, (7 givs pak currnt around 7.5kA, on approximatly ms half-cycl, which is comparabl to th magnitud obtaind with PSCAD simulation in Figur 6. Typical thyristors will hav pak ovrcurrnt 5-pu spcifid on a ms half-cycl, and thrfor th transint lvl of I pk can b tolratd by thyristors in a short intrval. As a simpl guiding rul, u should b comparabl to, in ordr to provid immunity from worst-cas faults. This larg valu of u will not caus ngativ consqunc during normal stp up opration xcpt for marginally incrasd cpk and rvrs rcovry losss in T 5 -T 6. Howvr, th inductor for stp down opration d should hav much smallr valus. Th valu for d is indpndntly calculatd considring th turn off tim (T off and currnt drivativs (di /dt max in T 7 -T 8 as it is discussd in []. For ths rasons it is rcommnd using two sparat inductors on high-voltag sid, a larg on for stp up and a smallr inductor for stp down mod. In practic, a singl larg inductor can b built, whr th smallr d inductanc is implmntd as a tap on u. Figur 5b shows th convrtr stady-stat variabls for fault B of varying svrity (progrssivly rducd voltag. Th bhavior mirrors that for fault C in Figur 5a. Th currnt on faultd sid (I rmains constant and only for xtrmly low voltags it incrass to around 5p.u. This is a ractiv currnt oscillating in u -C r circuit, which lasts for a short priod until controllr racts in stag 3. Th pak capacitor voltag ( cpk rducs and clarly thr is no dangr of ovrvoltag. In som cass it might b bnficial to hav a singl high voltag inductor. This option will lad to highr pak voltags cpk and lowr oprating frquncy in stp down mod. Th Appndix givs all th data for this dsign option. B. Unsymmtrical faults Th abov studis considr worst-cas pol-pol DC faults, but a pol to ground fault may b mor common in a practical systm. It is assumd that th DC sourcs and ar solidly groundd at cntral points, as it would b common with bi-polar HDC systms. Th rotating capacitor C r uss high-impdanc grounding at th cntr, as shown in Figur. Figur 7 shows th convrtr rspons aftr a zro impdanc fault on positiv pol of ( p :5k->k All th variabl labls hav additional subscript for positiv (p or ngativ (n pol. It is sn that th avrag currnt on unfaultd sid I and powr transfr halv and controllabl opration is maintaind. Th shar of th avrag currnt during th fault is shown in Tabl. Th ground rturn currnt on th unfaultd sid will b 3% of th pr-fault currnt. Bcaus of th thyristor ovrload on th faultd pol and th ground rturn currnt, th bipolar

11 opration should not b allowd, and th positiv pol on trminal should b bypassd. Undr this fault managmnt, th whol systm can continu to oprat at ngativ pols and transfrring half th powr. TABE. CURRENT SHARE AFTER POE TO GROUND FAUT ON P. Currnt I p I n I p I n % of pr-fault valu 57% 36% 67% 66%. INTERNA CONERTER FAUTS Th intrnal convrtr faults can occur bcaus of control systm malfunctioning. Th worst scnario is th cas whr two switchs in th sam branch ar simultanously fird (T and T, lading to short circuit on convrtr trminals. Howvr obsrving Figur it is concludd that such fault would not short th capacitor Cr, and th DC trminals would only b shortd through inductors or. Thrfor powr transfr would b intrruptd but th currnt drivativ would b constraind and th fault could b intrruptd by th nxt DC/DC convrtr ithr on low voltag or high-voltag DC lins. I. INTEGRATION STUDIES A. PSCAD tst systm with an HDC tap A dtaild PSCAD modl for th DC/DC convrtr and th conncting DC systms is dvlopd in ordr to study th impact of non-idal switchs, filtrs, controls and th intractions with th othr HDC convrtrs. Figur 8 shows th MW tst DC/DC convrtr conncting a ±44k DC lin to a larg 5MW, ±5k HDC systm. Th low voltag ±44k, km DC lin trminats with an AC/DC SC convrtr conncting to a 5k AC grid which could rprsnt a local load or a wind farm. Th us of DC transformr btwn HDC and DC fdrs provids following advantags: It lowrs DC voltag thus rducing costs for ±44k SC convrtr and lin, It nabls DC voltag rgulation and thus liminats an AC transformr on 5k grid, and 3 It prvnts fault propagation btwn th main ±5k DC lin and th local ±44k DC lin, which is crucial for th opration of such systm. Th SC convrtr assums a standard -lvl topology with PWM firing control and modulation ratio of [], and all paramtrs ar in th Appndix.

12 B. Control stratgy Th SC controllr rgulats local DC voltag dc using control signal d componnt M d, and th AC voltag ac using q componnt M q. Th DC/DC convrtr includs an innr DC currnt fdback PI controllr and an outr DC powr controllr (tap systm powr. It has bn concludd in prvious sctions (Figur 5a that in stp down opration I rmains constant undr faults. Thrfor in stp down mod, th innr currnt controllr rgulats th xit currnt, I, to avoid conflict btwn normal opration and opration undr faults. Similarly, in stp up opration th innr controllr rgulats xit currnt I. Th currnt rfrnc is mad dpndnt on th trminal voltag (E and E in ordr to rduc convrtr powr undr faults, which is a longr-trm fault managmnt stratgy (stag 3 convrtr rspons, as it is shown in Figur 9. C. Influnc of filtrs It is likly that som filtring will b usd on DC trminals of this DC/DC convrtr. A simpl shunt capacitor and th convntional shunt filtrs (C-typ, hav bn tstd and thy did not impact th abov convrtr proprtis undr th fault conditions. Bcaus of th variabl frquncy opration, a sris inductor in addition to shunt capacitor may b ffctiv in improving quality of DC currnts qually at low or high voltag trminals, as shown by f and C f in Figur 8. A sris inductor will improv th turn off tim by rducing th currnt drivativ, and thrfor u can b rducd, howvr thr is possibility of rsonanc with shunt capacitors which can caus lingring oscillation undr fault conditions. D. Simulation of DC faults Figur shows rsponss for worst cas E fault (E : 5k->k. Th voltag (at th convrtr trminals, in th top graph, rducs at slowr rat than E, and has a positiv valu in th instant whn th nxt high-voltag switch is fird. Thrfor a filtr inductor improvs turn off tim and clarly th dsign of u and filtrs should b coordinatd. In Figur w obsrv that th DC transformr continuously oprats through th E fault without intrnal ovrvoltag on c. It inhrntly rducs currnt on low-voltag sid as prdictd. Th currnt on faultd trminals I shows incras to 5p.u, in only fw pulss. By obsrving th control input f s, it is concludd that th controllr dtcts E voltag rduction and rducs th frquncy within -ms. Sinc oprating frquncy is rducd, th avrag fault currnt in thyristors is rducd and soon th firing gts intrruptd altogthr to isolat th fault. Th ±44k SC convrtr ss th fault on ±5k lins as a gradual load rjction. As it is sn in th lowr graph, th SC convrtr maintains DC voltag with an ovrvoltag of 5% and dos not xprinc any ovrcurrnts.

13 II. CONCUSIONS This papr studis th principls of isolating DC faults using high-powr rsonant DC/DC convrtrs. It is provn that th rsonant DC/DC convrtr posss inhrnt stabilising proprtis that prvnt ovrcurrnts and ovrvoltags in cas of trminal faults. Th faults on low voltag trminals ar particularly wll tolratd and only a -% margin in oprating frquncy is rquird to provid satisfactory opration through most svr faults. Th faults on high-voltag sid ar mor challnging, but thy crucially dpnd on th suitabl siz of th stp-up inductor on high-voltag sid. Th high-voltag inductor should b comparabl in siz to th low voltag inductor to achiv immunity from worst cas faults on high voltag trminals. Th rsarch dmonstrats that th convrtr is sn as high-impdanc circuit on th trminals opposit from faults, for both: low voltag and high voltag faults. Whil traditional protction stratgy racts to fault currnts (dtct and opn circuit, th prsnt dsign prvnts fault currnt lvls altogthr. Th convrtr also wll tolrats th unsymmtrical faults. Th dtaild PSCAD simulations on a ±44/±5k tst convrtr in a small DC ntwork, show that thr is no fault propagation through DC transformr. A SC convrtr on th opposit nd of km ±44k DC fdr vry wll coordinats fault rsponss with th DC transformr. III. APPENDIX TESTS SYSTEM TABE A. DC/DC CONERTER PARAMETERS Paramtr With u and d Singl f s [Hz] 7 33 / [k/k] 88/5 88/5 I av [ka].7.7 I av [ka].4.4 di /dt [A/µs] (max cp [k] (pak Efficincy [%] C r [µf] [mh] 8 67 [mh] u =4, d =4 4 α u [dg] 4 55 α d [dg] 4 C f [µf] 5 3 f [mh] 4 8 3

14 C f [µf] 5 f [mh] R g [Ω] 6 6 TABE A. SWITCH DATA IN THE PSCAD MODE (SIICON POWER T-T4 (C784 Forward/rvrs voltag [k] 5x4.5=7 T5-T8 (C64 5x4.5=7 Avrag on stat currnt [ka].65.4 On rsistanc [mω] 5x.37=55 5x.= Off rsistanc [MΩ] 5x.3=4.5 5x.6=9.3 oltag drop [] 5x.=65 5x.8=8 Extinction tim [µs] 4 4 TABE A.3 SC CONERTER AC voltag DC voltag 5k 88k PWM Modulation ratio DC capacitanc µf AC inductor 9mH Tabl A.4 DC lin paramtrs 44k lin 5k lin Rsistanc [Ω] 3 Inductanc [H].8.4 Capacitanc [µf] 6 3 IX. ACKNOWEDGEMENTS Th Authors ar thankful for th financial support from th Royal Acadmy UK, and National Rsarch Council Canada. 4

15 X. REFERENCES [] Bahram, M.; at all Intgration of small taps into (xisting HDC links IEEE Transactions on Powr Dlivry, olum, Issu 3, July 995, Pag(s: [] Svrr Gilj, alhall r-dvlopmnt projct, Powr from shor Cigré SC B4 Colloquium, Brgn, Jun 9, [3] D.Jovcic Off Shor Wind Farm with a Sris Multitrminal CSI HDC Elctric Powr Systms Rsarch, Elsvir, ol 78, issu 4, 8, pp [4] ianxiang Tang; Boon-Tck Ooi; Protction of SC Multitrminal HDC against DC faults Procdings of Powr lctronics spcialists confrnc, Jun, olum, Pag(s: [5] Baran, M.E.; Mahajan, N.R.; Ovrcurrnt Protction on oltag-sourc-convrtr-basd Multitrminal DC Distribution Systms IEEE Transactions on Powr Dlivry, olum, Issu, Jan. 7 Pag(s:46-4 [6] Nakao, H. at all DC currnt intrruption in HDC SF 6 gas MRTB by mans of slf-xcitd oscillation suprimposition IEEE Trans. on Powr Dlivry, olum 6, Issu 4, Oct. Pag(s: [7] Myr, C.; Kowal, M.; D Donckr, R.W., Circuit brakr concpts for futur high-powr DC-applications Industry Applications Confrnc, 5.olum, -6 Oct. 5 Pag(s: [8] McEwan, P.M.; Tnnakoon, S.B. A two-stag DC thyristor circuit brakr IEEE Transactions on Powr Elctronics olum, Issu 4, July 997 Pag(s: [9] N.Mohan, TM.Undland, WP.Robbins, Powr Elctronics Convrtrs, Applications and Dsign, John Wily & Sons, [] R.J.King, T.A.Stuart Inhrnt Ovrload Protction for sris rsonant convrtr IEEE Transactions on Arospac and Elctronic Systms ol AES 9 (6, Novmbr 983, pp [] D.Jovcic, Bidirctional high powr DC transformr IEEE Transactions on Powr Dlivry, ol. 4, issu 4, Octobr 9, pp [] Jovcic, D.; amont,.a.; Xu,.; SC Transmission modl for analytical studis IEEE PES mting, Toronto, Jun 3, ol. 3. 5

16 XI. FIGURES ist of Figurs: Figur. High-Powr Bidirctional DC-DC convrtr (>. Figur. Tst systm in normal opration. Paramtrs ar givn in th Appndix. Figur 3 Transint rspons for a zro-impdanc fault on in stp down mod ( :88k->k at.36s, =5k. Top graph: voltags, lowr graph: currnts. Figur 4. Chang in pak currnt and turn off tim for a zro-impdanc fault on. Figur 5. Stady-stat convrtr variabls for trminal voltag rduction. Figur 6. Transint rsponss for a zro-impdanc fault on in stp up mod ( :5k->k at.5s, =88k. Top graph: voltags, lowr graph: currnts. Figur 7. Transint rsponss for a zro-impdanc fault on positiv pol p in stp up mod ( p : 5k->k at.5s, n =-5k, =±44k. Top graph: voltags, lowr graph: currnts. Figur 8. Schmatic of tsts systm with intrfacing HDC convrtrs. Figur 9. Systm rsponss for a low-impdanc fault on 5k lin. ow voltag convrtr High voltag convrtr d T 3 T T 4 I T T 5 T 7 T 6 T 8 u I C r I c cr R g C r c cr T 4 T 3 T T T 6 T 8 T 5 T 7 u d f s f s α u α d controllr Figur. High-Powr Bidirctional DC-DC convrtr (>. oltag [k] Currnt [ka] c cr cr I I I filtrd I filtrd Tim [s] Figur. Tst systm in normal opration. Paramtrs ar givn in th Appndix. 6

17 oltag [k] Currnt [ka] B D C A B D A C T off T off I c C D cr α d A c B T off cr H fault B T off D C A H c nf I pk Tim [s] H B C D A T 3 T 4 B D A B C A B C A C D D I T 7 T8 T off I I Figur 3 Transint rspons for a zro-impdanc fault on in stp down mod ( :88k->k at.36s, =5k. Top graph: voltags, lowr graph: currnts. 5 4 Prcntag incras 3 - Pak currnt I pk Turn off tim T off Stpping ratio n Figur 4. Incras in pak currnt and turn off tim for a zro-impdanc fault on. I [ka] I [ka] cpk [k] Nominal oprating point cpk [k] I [ka] I [ka] 6 4 Nominal oprating point 4 [k] 8 [k] 4 a chang (fault C b chang (fault B Figur 5. Stady-stat convrtr variabls for trminal voltag rduction. 7

18 oltag [k] Currnt [ka] cr C A α u c T off D B A C H fault α u cr Toff B A T I 5 4 I T 5 I pk 3 I I A C BDA C H D D C c nf c BDA DC T off T off B A H D C c nf B B A D C B Tim [s] Figur 6. Transint rsponss for a zro-impdanc fault on in stp up mod ( :5k->k at.5s, =88k. Top graph: voltags, lowr graph: currnts. oltag [k] fault n cn Currnt [ka] p n p 4 I p I p I p I p - I n I n In -4 I n cp Tim [s] Figur 7. Transint rsponss for a zro-impdanc fault on positiv pol p in stp up mod ( p : 5k->k at.5s, n =-5k, =±44k. Top graph: voltags, lowr graph: currnts. 8

19 AC 35k 5k 5MW CC lin km 5k 5MW E CC AC 35k -5k C f f -5k f s DC/DC MW AC 5k M d M q 44k dc E Cf f ac SC km -44k Figur 8. Schmatic of tsts systm with intrfacing HDC convrtrs. P rf E E filtring I ς n, ωn X min P PI controllr - f s k p k i /s Figur 9. Schmatic of DC/DC convrtr controllr. 9

20 7 5 Ecr c oltag [k] E Currnt [ka] I I I I Powr [MW], Frq. fs [Hz] oltag [k] P Tim [s] 5 5 P fs dcrf dc acrf ac Tim [s] Figur. Systm rsponss for a low-impdanc fault on 5k lin.