The crossbar resistive memory array, in which the storage

pubs.acs.org/nanolett A Functional Hybrid Memristor Crossbar-Array/CMOS System for Data Storage and Neuromorphic Applications Kuk-Hwan Kim, Siddharth Gaba, Dana Wheeler, Jose M. Cruz-Albrecht, Tahir Hussain, Narayan Srinivasa, and Wei Lu*, Electrical Engineering and Computer Science, The University of Michigan, Ann Arbor, Michigan 48109, United States HRL Laboratories LLC, 3011 Malibu Canyon Road, Malibu, California 90265-4797, United States *S Supporting Information ABSTRACT: Crossbar arrays based on two-terminal resistive switches have been proposed as a leading candidate for future memory and logic applications. Here we demonstrate a highdensity, fully operational hybrid crossbar/cmos system composed of a transistor- and diode-less memristor crossbar array vertically integrated on top of a CMOS chip by taking advantage of the intrinsic nonlinear characteristics of the memristor element. The hybrid crossbar/cmos system can reliably store complex binary and multilevel 1600 pixel bitmap images using a new programming scheme. KEYWORDS: Memristor, resistive memory (RRAM), crossbar, hybrid integration, multilevel, neuromorphic system The crossbar resistive memory array, in which the storage elements are two-terminal resistive switches (sometimes termed memristors) forming a passive interconnected network, and hybrid crossbar/cmos systems have been identified as a leading candidate for future memory and logic applications. 1 11 However, a fundamental problem for such a passive array is that sneak paths, which correspond to parasitic current paths that bypass the target storage element, can be formed (Figure S1, Supporting Information) and cause the array to be nonfunctional. To suppress current flowing through sneak paths, a memory cell in the crossbar memory essentially needs two components: a memory switching element which offers data storage and a select device which regulates current flow. Several reports have shown that it is possible to scale the switching element down to nanometer scale with excellent performance in terms of speed, retention, and endurance. 12 15 On the other hand, obtaining a suitable select device that can be integrated in a crossbar array has become a significant challenge in resistive memory research, since diodes based on crystalline materials are not suitable for low-temperature fabrication, while those based on low-temperature materials suffer from performance and reliability issues. 16 18 Due to these difficulties, even though a number of approaches have been proposed to address the sneak path problem using diodes as the select device or using novel complementary cell structures, 16 20 the demonstrations have been essentially limited to the single-device level (either from standalone devices or from arrays in which all nonselected devices were kept in the off-state), and actual array-level operations where many cells are written then read out together have remained elusive. Instead of relying on an external diode as the select device, a more ideal approach is to take advantage of the inherent nonlinear current voltage (I V) characteristics obtained in some resistive switches themselves to break the sneak current paths. 21 24 Here we demonstrate that fully operational crossbar arrays that do not require external transistor or diode select devices can indeed be built by employing switching elements with inherently nonlinear I V characteristics. The transistorand diode-less crossbar arrays can be readily stacked on top of each other to further maximize the density advantage offered by the nanoscale devices. 4 Furthermore, by eliminating the requirement of having an external select device at each crosspoint, this approach significantly simplifies the array fabrication processes and enables the array to be completed at low temperature and directly integrated on top of underlying CMOS circuits. In this demonstration, the CMOS circuits provide peripheral functionality, such as address decoding, to complement the data storage functionalities of the crossbar array. A new programming scheme is also developed to control the device on-resistance and allow for multilevel storage in the array. The device structure studied here consists of a W/SiGe stack, an amorphous Si (a-si) layer, and a Ag layer acting as the bottom electrode, the switching medium, and the top electrode, respectively. The thickness of each layer was carefully designed for arrays of 50 nm half pitch. To prevent CMOS degradation in this back-end-of-line (BEOL) approach, the maximum Received: October 19, 2011 Revised: November 19, 2011 Published: December 5, 2011 2011 American Chemical Society 389

Nano s Figure 1. (a) SEM image of a crossbar array fabricated on top of a CMOS chip. Scale bar: 5 μm. (b) SEM image of the active crossbar array area showing 50 nm half pitch and 10 Gbits/cm2 density. Scale bar: 500 nm. (c) Schematic of the hybrid integrated system. Insets: schematic highlighting the vertical integration of the crossbar array with the on-chip CMOS circuitry. (d) Schematic of the program/read schemes. Each column or row in the crossbar array is connected to one of the two external signal pads (DATA A for signal applied to the selected column/row, DATA B for signal connected to the unselected column/row) through CMOS decoder circuits controlled by address I/O pads. (e) I V switching characteristics from 10 different cells in the crossbar array. Insets: I V switch characteristics plotted in log scale demonstrating current suppression at negative bias in the on-state. (f) Threshold voltage distribution of 256 cells in the fabricated crossbar array. The threshold voltage is defined as the voltage at which the measured current is above 10 6 A. temperature involved in all the fabrication processes was kept below 425 C. The final structure shown in Figure 1a has 40 top nanowire electrodes crossed with 40 bottom nanowire electrodes with a switching element formed at every crosspoint. A 50 nm half pitch was achieved through electron beam lithography and yielded an equivalent data storage density of 10 Gbits/cm2 (Figure 1b) when storing one bit per memory cell. A higher data storage density was also achieved by multilevel operation as discussed below. To integrate the crossbar structure directly on top of the CMOS circuit, every row (top electrode, corresponding to the word-line) and column (bottom electrode, corresponding to the bit-line) inside the crossbar array was connected through nanoscale ( 300 nm) vias to the output of a specific CMOS decoder unit underneath, as schematically illustrated in Figure 1c. In this integrated system, a row decoder enables the selection of a row wire (word line) for connection to the data input (DATA A) via CMOS pass transistors based on a row address code input. Unselected rows (whose addresses do not match the input address code) are connected to a separate data input (DATA 390

Nano s Figure 2. (a) The original black and white 40 40 bitmap image representing the University of Michigan logo. (b) The reconstructed bitmap image obtained by storing and retrieving data in the 40 40 crossbar array. (c) A second test image, which is complementary to the original, to be stored in the array. (d) The reconstructed image, obtained by storing the image in (c) in the same array. (e,f) Histograms of the on- and off-state resistances for the data in (b) and (d), respectively. side of the array), instead of having to supply 40 2 data inputs simultaneously, as is the case without CMOS decoder circuitry. Figure 1e shows the I V switching characteristics of the integrated memristor crossbar/cmos system using the programming method described above. Significantly, the fabrication of the memristor crossbar array in BEOL processing does not affect the CMOS device performance, and all programming and read signals can be passed through the CMOS circuit to the crossbar array as designed. In addition, Figure 1e shows that very similar switching curves can be obtained from devices in the fabricated crossbar array with a B), as schematically illustrated in Figure 1d. A similar configuration exists for the columns (bit lines). With the word- and bit-line combinations selected, the desired programming or read voltage (supplied to DATA A) is applied across the selected cell only. All other cells are biased with predefined protective voltages, grounded, or left floating through DATA B. As a result, the integrated system allows random programming of the 1600 cells inside the 40 40 array using only two DATA inputs and five address inputs at each side (20 rows or columns are connected to decoders on each 391

Nano s Figure 3. (a) I V characteristics of a single cell programmed with four different series resistance values (0.1, 0.5, 1, and 5 MΩ), demonstrating multilevel capability. (b) Histogram of the on-state resistances for the four target values. The data were collected from 30 different cells, each of which was programmed into all four levels. (c) Measurement diagram for the conventional programming scheme. In this case, the effective series resistance seen by the target cell consists of additional current paths through half-selected devices and cannot be predicted beforehand. (d) New measurement diagram that enables multilevel storage in the crossbar array. Parallel current paths through the half-selected devices are blocked dueto the external diodes at the outside and the intrinsic current-rectifying characteristics at each crosspoint. Asymmetric protecting voltages V pw and V pb can be applied to the unselected word- and bit-lines, respectively, to minimize disturbances during programming. narrow threshold voltage distribution. Tight distribution of the switching characteristics is a prerequisite for the operation of resistive memories at large scale to avoid accidental programming/erase events during the application of protective or read voltages. To further illustrate the switching parameter statistics, Figure 1f plots the histogram of the threshold voltages obtained from 256 cells in an array, showing a tight distribution with an average threshold voltage of 2.30 V and a standard deviation of 0.07 V. We note that the devices studied here are strictly speaking memristive devices instead of linear memristors, 25 but these two terms are commonly used interchangeably in the literature and will not be distinguished in this paper. It is also noteworthy that the cells maintain an intrinsic current-rectifying behavior as shown in Figure 1e (and its inset), such that the current at reverse bias is pronouncedly suppressed compared to the current at forward bias, consistent with earlier reports on similar stand-alone cells. 21 It needs to be noted that even though the current through the device is suppressed at relatively small reverse bias, the device remains in the on-state, and only transitions to the off-state become erased with large (e.g., < 1.5 V) negative voltages. This effect is verified in Figure S2, Supporting Information, which shows that the on-state is not destroyed with reverse biases up to 1 V. The intrinsic current-rectifying characteristic can effectively break the sneak current paths (Figure S1b, Supporting Information) and is a key reason that the array studied here can operate without having an external transistor or diode at each crosspoint. To test the operation of the integrated crossbar array, a binary bitmap image with 1600 pixels (40 40) representing the University of Michigan logo was prepared (Figure 2a, with the black pixels representing data 0, i.e., the off-state and white pixels representing data 1, i.e., the on-state ). The image was then programmed into the 40 40 integrated array and read out. For writing 1 into a cell inside the array, a 3.5 V, 100 μs pulse was applied across the selected cell through the CMOS decoder circuit using the protocol discussed above, while the other unselected electrodes in the 40 40 array were connected to a protective voltage with amplitude equaling half of the programming voltage to minimize disturbance of unselected cells. A similar approach was used for writing 0 using a 1.75 V, 100 μs erase pulse. The programming/erase speed here was mainly limited by the RC delay associated with the setup and can be significantly improved with integrated onchip programming and sensing circuitry, as much faster intrinsic programming speed has been reported on similar devices. 14,21 The programming/erasing was carried out based only on the input pattern and ignored the existing state of the memory 392

Nano s Figure 4. (a) A color 40 40 test image with 10 different target levels to be stored in the array. The resistances are represented by the different colors as defined in the color scale bar on right. (b) The reconstructed data map from the 40 40 array obtained by storing and retrieving the image in (a) (same color scale). (c) False-color image of the error for the stored data. The error is defined as (Rtarget Rmeasured)/(Rtarget) and represented by different colors in the color scale bar on right. (d) Histogram of the error values for the stored data. the integrated crossbar/cmos system can reliably store data at the array level. In addition, the large on/off ratio offered by the cells (e.g., Figure 1e) suggests the possibility for multilevel cell (MLC) storage. Storing multiple levels in a single memory element is necessary to satisfy the needs of increased storage density and is also required for many neuromorphic applications for which resistive switches (memristors) are ideally suited.26 MLC capability has been demonstrated in resistive memories by controlling the current compliance during switching or equivalently by controlling the series resistance the cell sees.27 29 To verify MLC capability for devices in the integrated system, a single cell in the crossbar array was programmed (with all other cells in the off-state in this case) using different series resistances (0.1, 0.5, 1, and 5 MΩ). The results shown in Figure 3a demonstrated that MLC is indeed possible with the on-state resistance of the cell controlled by the series resistor value. This multilevel storage effect can be explained by the self-limiting filament growth model in which the filament growth rate is roughly an exponential function of the applied voltage across the memory device.27,28 As the resistance of the memory device approaches the series resistance value, the voltage across the device is reduced by the voltage divider effect, and filament growth significantly slows down resulting in a device resistance determined by the series resistance.27,28 The reproducibility of the MLC operation is verified in Figure 3b, which plots the resistance distribution cells, and a single programming/erase pulse was sufficient for each cell. Once all data were programmed in an array, the information in the array was then read out one cell at a time by applying a 1 V, 500 μs read pulse across the target cell, while grounding all unselected electrodes through the CMOS decoder. To minimize cell wear out, the 40 40 array was divided into 25 8 8 subarrays, and each subarray was programmed as a whole followed by readout. The 40 40 pixel bitmap image was reconstructed by stitching results from the 25 8 8 subarrays together. The resulting image in Figure 2b accurately reflected the initial target image and clearly demonstrated that by taking advantage of the intrinsic nonlinear I V characteristics, the integrated crossbar/cmos system could function well without added transistor or diodes as select devices at each cell. Operations based on larger subarrays (e.g., 20 20) have also been performed, and results are shown in Figure S3, Support Information. To further illustrate the full functionality of the integrated crossbar array, a complementary image (Figure 2c) of the original was stored into the same array using the same approach. The reconstructed image for the complementary bitmap is presented in Figure 2d, verifying every bit in the crossbar array can be reliably reprogrammed to either the 1 or 0 state. The reliability of the memory array is further illustrated by examining the on- and off-state resistance distribution, as plotted in Figure 2e,f for the two cases. Clear separation between the 1 and 0 states is obtained, with at least 20 difference in resistance between the worst cases, verifying that 393

Nano s from 30 different cells, each programmed into four different resistance states. However, achieving multilevel storage in crossbar arrays is inherently much more difficult than achieving binary storage, since the series resistance seen by the target cell (or equivalently, the programming current through it) is affected by other cells in the array. As illustrated in Figure 3c, the current flowing through the target cell is not only affected by the external resistor but also by the states of the half-selected cells sharing the same word-line, i.e., the actual series resistance the target cell sees is the combination of the external series resistance and the resistance of the half-selected cells in parallel which cannot be determined beforehand. This effect explains why the resistance distributions obtained in the array shown in Figure 2e,f are larger than those shown in Figure 3b for individual cells and why the distributions are also worse in Figure 2f, which corresponds to a configuration with more cells in the on-state (and hence, more leakage paths) than those in Figure 2e. To address this problem and block the parallel current paths, we developed a new programming scheme. In this approach, schematically illustrated in Figure 3d, external diodes (e.g., P6KE15A, Littelfuse Inc. used in this study) are connected to each unselected bit- and word-line to prevent current flow into the external electrodes and to allow only the applied input voltage signals to path through. Once again, the intrinsic current-rectifying characteristic plays a crucial role in making the approach feasible since it prevents current from flowing backward at the crosspoints to reach the selected bit- or word-line. Combining the intrinsic-rectifying characteristics with external diodes, current flow through the half-selected cells can now be fully prohibited, enabling control over current in the target device during programming for multilevel storage capability. In addition, since no current flows through the halfselected cells, this approach reduces power consumption which is another drawback in conventional crossbar array programming. For comparison, our simulations (Figure S4, Supporting Information) show that without the intrinsic current-rectifying characteristics, programming current through the target cell cannot be controlled even with the application of external diodes at the unselected electrodes. In the new scheme shown in Figure 3d, since the unselected bottom electrodes are virtually floated due to the reverse-biased diodes, they may be charged up during programming to a potential close to the programming voltage. As a result, the internal voltage on the unselected bit-lines, V ub shown in Figure 3d, may be higher than the externally supplied protective voltage V pb, and during programming the unselected cells can potentially see large negative voltages (< 1 V) across them. To reduce this effect, asymmetric protecting voltages were used for the unselected word- and bit-lines (labeled as V pw and V pb, respectively, in Figure 3d with V pw > V pb ). The exact potential distribution across the entire crossbar array was simulated for the worst case scenario and presented in Figure S5, Supporting Information. By properly selecting the protective voltages, the maximum negative voltage the unselected cells could see was shown to be 0.8 V (in the worst case) during programming, not sufficient to disturb the state of the unselected cells. Based on this new programming scheme, a randomly generated color (multilevel) map with 10 different levels (0.025, 0.05, 0.1, 0.25, 0.5, 0.75, 1, 5, 7.5, and 10 MΩ) as presented in Figure 4a, was stored into the 40 40 array. Each target resistance value was set by a switchable series resistor and programmed using a single 3.5 V, 100 μs voltage pulse. A set of 5 5 subarrays were programmed, followed by a retrieval of all bits in the subarrays with 1 V, 500 μs read pulses without series resistor. The process was repeated to complete the 40 40 array, and the reconstructed image is presented in Figure 4b. The stored/retrieved image roughly follows the same patterns as the original image; however, some errors are also visible due to the relatively small spacings between the different resistance values used to store the 10 levels. The error, defined as ((R target R measured )/(R target )), is presented in Figure 4c,d. Overall 75% (1200/1600 cells) of the measured resistance values were within 50% of the target value, i.e., 0.5R target < R measured < 1.5R target. The apparent asymmetry of the histogram plot shown in Figure 4d is mainly due to the way error is calculated here using an asymmetric range from to 1. For digital information storage, the error reported here is relatively large but may be improved further by using on-chip integrated current compliance setups instead of an off-chip resistor to reduce parasitic effects. On the other hand, this level of error may not be a significant problem for neuromorphic applications as biological systems typically exhibit similar sized or even larger noise. 30 In summary, high-density, vertically integrated, hybrid memristor/cmos systems have demonstrated and function well by taking advantage of the intrinsic rectifying I V characteristics of the switching device itself. Binary bitmap images were successfully stored and retrieved with considerable read margin. A new programming scheme was developed to allow the integrated crossbar array to store up to 10 different levels by eliminating the parallel current paths. These demonstrations verify that it is possible to build high-density functional crossbar arrays without having to incorporate external select devices at each crosspoint, and the hybrid crossbar/cmos systems are well-suited for the proposed future data storage and neuromorphic applications. 1,7 11 ASSOCIATED CONTENT *S Supporting Information Additional supplementary figures showing the sneak path problem, the intrinsic rectifying behavior, results obtained from operating 20 20 subarrays, simulation results, and device fabrication processes and measurement setups of the integrated system. This material is available free of charge via the Internet at http://pubs.acs.org. AUTHOR INFORMATION Corresponding Author *E-mail: wluee@eecs.umich.edu. ACKNOWLEDGMENTS This work was supported in part by the DARPA SyNAPSE program under contract number HRL0011-09-C-001 and by the National Science Foundation (NSF) Career award (ECCS- 0954621). This work used the Lurie Nanofabrication Facility at the University of Michigan, a member of the National Nanotechnology Infrastructure Network (NNIN) funded by the NSF. The authors acknowledge M. Yung, D. Matthews and A. Soldin for assistance in design of CMOS circuitry. The views expressed are those of the authors and do not reflect the official policy or position of the Department of Defense or the U.S. Government. 394

REFERENCES (1) Strukov, D. B.; Likharev, K. K. J. Nanosci. Nanotechnol. 2007, 7, 151 167. (2) Waser, R.; Aono, M. Nat. Mater. 2007, 6, 833 840. (3) Strukov, D. B.; Snider, G. S.; Stewart, D. R.; Williams, R. S. Nature 2009, 453, 80 83. (4) Strukov, D. B.; Williams, R. S. Proc. Natl. Acad. Sci. U.S.A. 2009, 106, 20155 20158. (5) Ku geler, C.; Meier, M.; Rosezin, R.; Gilles, S.; Waser, R. Solid- State Electron. 2009, 53, 1287 1292. (6) Jo, S. H.; Kim, K.-H.; Lu, W. Nano Lett. 2009, 9, 870 874. (7) Jo, S. H.; Chang, T.; Ebong, I.; Bhavitavya, B.; Mazumder, P.; Lu, W. Nano Lett. 2010, 10, 1297 1301. (8) Borghetti, J.; Li, Z.; Straznicky, J.; Li, X.; Ohlberg, D. A. A.; Wu, W.; Stewart, D. R.; Williams, R. S. Proc. Natl. Acad. Sci. U.S.A. 2009, 106, 1699 1703. (9) Xia, Q.; Robinett, W.; Cumbie, M. W.; Banerjee, N.; Cardinali, T. J.; Yang, J. J.; Wu, W.; Li, X.; Tong, W. M.; Strukov, D. B.; Snider, G. S.; Medeiros-Ribeiro, G.; Williams, R. S. Nano Lett. 2009, 9, 3640 3645. (10) Yan, H.; Choe, H. S.; Nam, S.; Hu, Y.; Das, S.; Klemic, J. F.; Ellenbogen, J. C.; Lieber, C. M. Nature 2011, 470, 240 244. (11) Borghetti, J.; Snider, G. S.; Kueke, P. J.; Yang, J. J.; Stewart, D. R.; Williams, R. S. Nature 2010, 464, 873 876. (12) Lee, M.-J.; Han, S.; Jeon, S. H.; Park, B. H.; Kang, B. S.; Ahn, S.- E.; Kim, K. H.; Lee, C. B.; Kim, C. J.; Yoo, I.-K.; Seo, D. H.; Li, X.-S.; Park, J.-B.; Lee, J.-H.; Park, Y. Nano Lett. 2009, 9, 1476 1481. (13) Terabe, K.; Hasegawa, T.; Nakayama, T.; Aono, M. Nature 2005, 433, 47 50. (14) Jo, S. H.; Lu, W. Nano Lett. 2008, 8, 392 397. (15) Tran, X. A.; Yu, H. Y.; Yeo, Y. C.; Wu, L.; Liu, W. J.; Wang, Z. R.; Fang, Z.; Pey, K. L.; Sun, X. W.; Du, A. Y.; Nguyen, B. Y.; Li, M. F. IEEE Electron Device Lett. 2011, 32, 396 398. (16) Lee, M.-J.; Park, Y.; Suh, D.-S.; Lee, E.-H.; Seo, S.; Kim, D.-C.; Jung, R.; Kang, B.-S.; Ahn, S.-E.; Lee, C. B.; Seo, D. H.; Cha, Y.-H.; Yoo, I.-K.; Kim, J.-S.; Park, B. H. Adv. Mater. 2007, 19, 3919 3923. (17) Cho, B.; Kim, T.-W.; Song, S.; Ji, Y.; Jo, M.; Hwang, H.; Jung, G.-Y.; Lee, T. Adv. Mater. 2010, 22, 1228 1232. (18) Wang, C.-H.; Tsai, Y.-H.; Lin, K.-C.; Chang, M.-F.; King, Y.-C.; Lin, C. J.; Sheu, S.-S.; Chen, Y.-S.; Lee, H.-Y.; Chen, F. T.; Tsai, M.-J. IEEE Trans. Electron Devices 2011, 58, 2466 2472. (19) Linn, E.; Rosezin, R.; Ku geler, C.; Waser, R. Nat. Mater. 2010, 9, 403 406. (20) Lee, M.-J.; Le, C. B.; Lee, D.; Lee, S. R.; Chang, M.; Hur, J. H.; Kim, Y.-B.; Kim, C.-J.; Seo, D. H.; Seo, S.; Chung, U.-I.; Yoo, I.-K.; Kim, K. Nat. Mater. 2011, 10, 625 630. (21) Kim, K.-H.; Jo, S. H.; Gaba, S.; Lu, W. Appl. Phys. Lett. 2010, 96, 053106. (22) Puthentheradam, S. C.; Schroder, D. K.; Kozicki, M. N. Appl. Phys. A: Mater. Sci. Process. 2011, 102, 817 826. (23) Zuo, Q.; Long, S.; Yang, S.; Liu, Q.; Shao, L.; Wang, Q.; Zhang, S.; Li, Y.; Wang, Y.; Liu, M. IEEE Electron Device Lett. 2010, 31, 344 346. (24) Huang, J.-J.; Kuo, C.-W.; Chang, W.-C.; Hou, T.-H. Appl. Phys. Lett. 2010, 96, 262901. (25) Chua, L. O.; Kang, S. M. Proc.- IEEE 1976, 64, 209 223. (26) Snider, G. S. IEEE/ACM International Symposium Nanoscale Architectures, Anaheim, CA, June 12-13, 2008; IEEE: New York; pp 85 92. (27) Jo, S. H.; Kim, K.-H.; Lu, W. Nano Lett. 2009, 9, 496 500. (28) Russo, U.; Kamalanathan, D.; Ielmini, D.; Lacaita, A. L.; Kozicki, M. N. IEEE Trans. Electron Devices 2009, 56, 1040 1047. (29) Wang, Y.; Liu, Q.; Long, S.; Wang, W.; Wang, Q.; Zhang, M.; Zhang, S.; Li, Y.; Zuo, Q.; Yang, J.; Liu, M. Nanotechnology 2010, 21, 045202. (30) Bi, G.-Q.; Poo, M.-M. J. Neuroscience 1998, 18, 10464 10472. Nano s 395