Features Floating channel designed for bootstrap operation Fully operational to +6 V Tolerant to negative transient voltage, dv/dt immune Gate drive supply range from 1 V to 2 V Undervoltage lockout 3.3 V, V, and 1 V logic input compatible Matched propagation delay for both channels Outputs in phase with inputs RoHS compliant Description The IRS211 is a high voltage, high speed power MOSFET and IGBT driver with independent high-side and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the highside configuration which operates up to 6 V. Typical Connection Data Sheet No. PD62 HIGH AND LOW SIDE DRIVER Product Summary V OFFSET I O +/- V OUT t on/off (typ.) Delay Matching Packages 8-Lead SOIC IRS211S IRS211(S)PbF 6 V max. 13 ma/27 ma 1 V - 2 V 16 ns/1 ns ns 8-Lead PDIP IRS211 IRS211 (Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com 1
IRS211(S)PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Min. Units V B High-side floating supply voltage -.3 62 V S High-side floating supply offset voltage V B - 2 V B +.3 V HO High-side floating output voltage V S -.3 V B +.3 V CC Low-side and logic fixed supply voltage -.3 2 V LO Low-side output voltage -.3 V CC +.3 V IN Logic input voltage (HIN & LIN) -.3 V CC +.3 dv S /dt Allowable offset supply voltage transient V/ns P D Package power dissipation @ T A +2 C Rth JA Thermal resistance, junction to ambient (8 lead PDIP) 1. (8 lead SOIC).62 (8 lead PDIP) 12 (8 lead SOIC) 2 T J Junction temperature 1 T S Storage temperature - 1 T L Lead temperature (soldering, 1 seconds) 3 V W C/W C Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at a 1 V differential. Symbol Definition Min. Units V B High-side floating supply absolute voltage V S + 1 V S + 2 V S High-side floating supply offset voltage Note 1 6 V HO High-side floating output voltage V S V B V CC Low-side and logic fixed supply voltage 1 2 V V LO Low-side output voltage V CC V IN Logic input voltage (HIN & LIN) V CC T A Ambient temperature -4 12 C Note 1: Logic operational for V S of - V to +6 V. Logic state held for V S of - V to -V BS. (Please refer to the Design Tip DT97-3 for more details). www.irf.com 2
IRS211(S)PbF Dynamic Electrical Characteristics V BIAS (V CC, V BS ) = 1 V, C L = 1 pf and T A = 2 C unless otherwise specified. Symbol Definition Min. Units Test Conditions ton Turn-on propagation delay 16 22 V S = V toff Turn-off propagation delay 1 22 V S = 6 V ns tr Turn-on rise time 7 17 tf Turn-off fall time 3 9 MT Delay matching, HS & LS turn-on/off Static Electrical Characteristics V BIAS (V CC, V BS ) = 1 V and T A = 2 C unless otherwise specified. The V IN, V TH, and I IN parameters are referenced to COM. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol Definition Min. Units Test Conditions V IH Logic 1 input voltage 2. V IL Logic input voltage.8 V OH High level output voltage, V BIAS - V O..2 V OL Low level output voltage, V O.2.1 I LK Offset supply leakage current V B = V S = 6 V I QBS Quiescent V BS supply current 3 I QCC Quiescent V CC supply current 1 27 I IN+ Logic 1 input bias current 3 1 V IN = V I IN- Logic input bias current V IN = V V CCUV+ V CC supply undervoltage positive going threshold 8 8.9 9.8 V CCUV- V CC supply undervoltage negative going threshold 7.4 8.2 9 V O = V I O+ Output high short circuit pulsed current 13 29 V IN = Logic 1 PW 1 µs V O = 1 V I O- Output low short circuit pulsed current 27 6 V IN = Logic V µa V ma V CC = 1 V to 2 V I O = 2 ma V IN = V or V PW 1 µs www.irf.com 3
IRS211(S)PbF Functional Block Diagram IRS211 www.irf.com 4
IRS211(S)PbF Lead Definitions Symbol Description HIN LIN V B HO V S V CC LO COM Logic input for high-side gate driver output (HO), in phase Logic input for low-side gate driver output (LO), in phase High-side floating supply High-side gate drive output High-side floating supply return Low-side and logic fixed supply Low-side gate drive output Low-side return Lead Assignments 8 Lead PDIP 8 Lead SOIC IRS211PbF Part Number IRS211SPbF www.irf.com
IRS211(S)PbF Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions Figure 3. Delay Matching Waveform Definitions www.irf.com 6
IRS211(S)PbF Turn-On Delay Time (ns) 4 3 2 1 Turn-On Delay Time (ns) 4 3 2 1 - -2 2 7 1 12 Figure 6A. Turn-On Time 1 12 14 16 18 2 V BIAS Supply Voltage (V) Figure 6B. Turn-On Time vs. Supply Voltage Turn-On Delay Time (ns) 4 3 2 1 2 4 6 8 1 12 14 16 18 2 Turn-Off Delay Time (ns) 4 3 2 1 - -2 2 7 1 12 Input Voltage (V) Figure 6C. Turn-On Time vs. Input Voltage Figure 7A. Turn-Off Time Turn-Off Delay Time (ns) 4 3 2 1 Turn-Off Delay Time (ns 4 3 2 1 1 12 14 16 18 2 2 4 6 8 1 12 14 16 18 2 V BIAS Supply Voltage (V) Input Voltage (V) Figure 7B. Turn-Off Time vs. Supply Voltage Figure 7C. Turn-Off Time vs. Input Voltage www.irf.com 7
IRS211(S)PbF Turn-On Rise Time (ns) 4 3 2 1 - -2 2 7 1 12 Turn-On Rise Time (ns) 4 3 2 1 1 12 14 16 18 2 VBIAS Supply Voltage (V) Figure 9A. Turn-On Rise Time Figure 9B. Turn-On Rise Time vs. Voltage 2 2 Turn-Off Fall Time (ns) 1 1 - -2 2 7 1 12 Turn-Off Fall Time (ns) 1 1 1 12 14 16 18 2 V BIAS Supply Voltage (V) Input Voltage (V) Figure 1A. Turn-Off Fall Time 8 7 6 4 3 2 1 Min. - -2 2 7 1 12 Temperature ( o C) Figure 12A. Logic "1" Input Voltage Input Voltage (V) Figure 1B. Turn-Off Fall Time vs. Voltage 8 7 6 4 3 2 1 Min. 1 12 14 16 18 2 V BIAS Supply Voltage (V) Figure 12B. Logic "1" Input Voltage vs. Voltage www.irf.com 8
IRS211(S)PbF Logic "" Input Bias Current (µa) High Level Output Voltage (V) Low Level Output Voltage (V) 6 4 3 2 1 - -2 2 7 1 12 ( C)..4.3.2.1. - -2 2 7 1 12..4.3.2.1. Temperature ( o C) Figure 14A. High Level Output Voltage Max Figure 13A. Logic "" Input Bias Current - -2 2 7 1 12 Temperature ( o C) Figure 1A. Low Level Output Voltage Logic "" Input Bias Current (µa) High Level Output Voltage (V) Low Level Output Voltage (V) 6 4 3 2 1..4.3.2.1. 1 12 14 16 18 2 Vcc Supply Voltage (V) V BAIS Supply Voltage (V)..4.3.2.1 Max 1 12 14 16 18 2 Supply Voltage (V) Figure 13B. Logic "" Input Bias Current vs. Voltage Figure 14B. High Level Output vs. Supply Voltage 1 12 14 16 18 2 V BIAS Supply Voltage (V) Figure 1B. Low level Output vs.supply Voltage www.irf.com 9
IRS211(S)PbF Offset Supply Leakage Current (µa) 4 3 2 1 - -2 2 7 1 12 Offset Supply Leakage Current (µa) (µa) 4 3 2 1 1 2 3 4 6 V B Boost Voltage (V) Figure 16A. Offset Supply Current Figure 16B. Offset Supply Current vs. Voltage 1 1 V BS Supply Current (µa) 12 9 6 3 - -2 2 7 1 12 V BS Supply Current (µa) 12 9 6 3 1 12 14 16 18 2 V BS Floating Supply Voltage (V) Figure 17A. V BS Supply Current Figure 17B. V BS Supply Current vs. Voltage 7 7 V cc Supply Current (µa) 6 4 3 2 1 - -2 2 7 1 12 V cc Supply Current (µa) 6 4 3 2 1 1 12 14 16 18 2 V cc Supply Voltage (V) Figure 18A. Vcc Supply Current Figure 18B. Vcc Supply Current vs. Voltage www.irf.com 1
IRS211(S)PbF 3 3 Logic 1 Input Current (µa) 2 2 1 1 - -2 2 7 1 12 Logic 1 Input Current (µa) 2 2 1 1 1 12 14 16 18 2 V cc Supply Voltage (V) Figure 19A. Logic"1" Input Current Figure 19B. Logic"1" Input Current vs. Voltage Logic Input Current (µa) 4 3 2 1 - -2 2 7 1 12 Logic Input Current (µa) 4 3 2 1 1 12 14 16 18 2 Vcc Supply Voltage (V) Figure 2A. Logic "" Input Current Figure 2B. Logic "" Input Current vs. Voltage V CC UVLO Threshold +(V) 11 1 9 Min. 8 7 6 - -2 2 7 1 12 V CC UVLO Threshold - (V) 11 1 9 8 7 Min. 6 - -2 2 7 1 12 Figure 21A. Vcc Undervoltage Threshold(+) Figure 21B. Vcc Undervoltage Threshold(-) www.irf.com 11
Output Source Current (ma) Output Source Current (ma) IRS211(S)PbF 4 ( ) 4 3 3 2 2 1 Min. 1 - -2 2 7 1 12 Temperature ( o C) Figure 22A. Output Source Current Min. 1 12 14 16 18 2 V BIAS S Supply Voltage (V) ( ) Figure 22B. Output Source Current vs. Supply Voltage 1 1 Output Sink Current (ma) 8 6 4 Min. 2 - -2 2 7 1 12 Output Sink Current (ma) 8 6 4 2 Min. 1 12 14 16 18 2 V BIAS Supply Voltage (V) Figure 23A. Output Sink Current Figure 23B. Output Sink Current vs. Supply Voltage www.irf.com 12
IRS211(S)PbF Case Outlines 8 Lead PDIP 1-614 1-33 1 (MS-1AB) A E 6 6X D 8 7 6 1 2 3 4 e B H.2 [.1] A 6.46 [.2] 3X 1.27 [.] FOOTPRINT 8X.72 [.28] 8X 1.78 [.7] DIM INC HES MILLIMETERS MIN MAX MIN MAX A A1.32.4.688.98 1.3.1 1.7.2 b.13.2.33.1 c.7.98.19.2 D E.189.1497.1968.174 4.8 3.8. 4. e. BASIC 1.27 BASIC e1.2 BASIC.63 BASIC H K L y.2284.99.16.244.196. 8.8.2.4 6.2. 1.27 8 e1 A C y K x 4 8X b A1.2 [.1] C A B.1 [.4] 8X L 7 8X c NOTES: 1. DIMENSIONING & TOLERANCING PER ASME Y14.M-1994. 2. CONTROLLING DIMENSION: MILLIMETER 3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-12AA. 8 Lead SOIC DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED.1 [.6]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED.2 [.1]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE. 1-627 1-21 11 (MS-12AA) www.irf.com 13
IRS211(S)PbF Tape & Reel 8-lead SOIC LOADED TA PE FEED DIRECTION B A H D F C N OTE : CONTROLLING D IMENSION IN MM E G CARRIER TAPE DIMENSION FOR 8SOICN M etr ic Im p erial Code Min Max Min Max A 7.9 8.1.31 1.3 18 B 3.9 4.1.13.161 C 11.7 12.3.46.484 D.4..21 4.2 18 E 6.3 6..24 8.2 F.1.3.2.2 8 G 1. n/a.9 n/a H 1. 1.6. 9. 62 F D E C B A G H REEL DIMENSIONS FOR 8SOICN M etr ic Im p erial Code Min Max Min Max A 329.6 33.2 12.976 13.1 B 2.9 21.4.824.844 C 12.8 13.2.3.19 D 1.9 2.4.76 7. 96 E 98. 12. 3.88 4.1 F n/a 18.4 n/a.724 G 14. 17.1.7.673 H 12.4 14.4.488.66 www.irf.com 14
IRS211(S)PbF LEADFREE PART MARKING INFORMATION Part number Date code IRxxxxxx S YWW? IR logo Pin 1 Identifier? MARKING CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - 4 digit SPN code) Assembly site code Per SCOP 2-2 ORDER INFORMATION 8-Lead PDIP IRS211PbF 8-Lead SOIC IRS211SPbF 8-Lead SOIC Tape & Reel IRS211STRPbF The SOIC-8 is MSL2 qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 924 Tel: (31) 22-71 Data and specifications subject to change without notice. 11/27/26 www.irf.com 1