June 18, 2004 Xilinx Spartan -3 XC3S200 FT256AFQ Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Major Findings 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 Isolation 3.8 Wells and Epi 4 SRAM Cell Analysis 4.1 SRAM Plan View Analysis 5 Materials Analysis 5.1 SIMS Analysis of the Dielectrics 5.2 TEM-EDS Analysis of Metal 8 5.3 EDS Analysis of ILD 1 and the Pre-Metal Dielectics 5.4 Transistor, Contacts, polycide and STI 5.5 SRP Analysis of the Wells and Substrate
Structural Analysis 6 Critical Dimensions 6.1 Horizontal Dimensions 6.2 Vertical Dimensions About Chipworks
Overview 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Package Top 2.1.2 Package Bottom 2.1.3 Plan View Package X-Ray 2.1.4 Side View Package X-Ray 2.1.5 Die Photograph 2.1.6 Die at Metal 2 2.1.7 Die Marking 1 2.1.8 Die Marking 2 2.2.1 Die Corner 2.2.2 Die Corner 2.2.3 Die Corner 2.2.4 Die Corner 2.2.5 Pad Ring and Bond Pads 2.2.6 Pad Ring and Power Buses 2.2.7 Bond Pads 3 Process Analysis 3.1.1 General View of the XC3S200 FT256AFQ 3.1.2 Die Edge 3.1.3 Die Seal 3.2.1 Ball Bond to Bond Pad 3.2.2 Bond Pad Edge 3.3.1 Passivation 3.3.2 ILD 7 and ILD 6 3.3.3 TEM Image of ILD 6 3.3.4 ILD 5 3.3.5 TEM Image of ILD 5 Line Dielectric 3.3.6 ILD 4 Through ILD 2 Levels 3.3.7 TEM Image of ILD 1 3.3.8 Pre-Metal Dielectric 3.4.1 Minimum Pitch Metal 8 3.4.2 TEM Section of Metal 8 3.4.3 Minimum Pitch Metal 7 3.4.4 TEM Cross-Section of Metal 7 1-1
Overview 3.4.5 Metal 7 Ta/TaN Bilayer 3.4.6 Minimum Pitch Metal 6 3.4.7 TEM of Minimum Pitch Metal 5 3.4.8 Minimum Pitch Metal 4 3.4.9 TEM of Minimum Pitch Metal 3 3.4.10 Minimum Pitch Metal 2 3.4.11 TEM of Minimum Pitch Metal 1 3.4.12 TEM of Metal 1 Ta/TaN Liner 3.5.1 Minimum Pitch Via 6 s and Via 5 s 3.5.2 TEM Section of Via 5 3.5.3 Minimum Pitch Via 5 s Through Via 2 s 3.5.4 TEM Section of a Via 2 3.5.5 Minimum Pitch Via 1 s 3.5.6 Minimum Pitch Contacts to Diffusion 3.5.7 Minimum Pitch Contacts to Polycide 3.5.8 TEM of Metal 1 to Contact Interface 3.5.9 TEM of Contact to Diffusion 3.5.10 TEM of Contact to Polycide 3.6.1 Minimum Gate Length NMOS Transistor 3.6.2 Minimum Gate Lenth PMOS Transistor 3.6.3 TEM of Logic Transistor 3.6.4 TEM of Thick Gate Oxide 3.6.5 TEM of Thin Gate Oxide 3.6.6 Minimum Pitch Polycide 3.7.1 Minimum Width STI 3.7.2 Polycide Over STI 3.7.3 Polycide Over Field Oxide 3.7.4 TEM of Thick Gate Dielectric 3.8.1 SCM Profile of N-Well and P-Well 4 SRAM Cell Analysis 4.0.1 8T SRAM Cell 4.1.1 Dual Port SRAM at Metal 2 4.1.2 SRAM at Metal 1 4.1.3 SRAM at Polycide 4.1.4 SRAM Cell at Polycide 4.1.5 SRAM Delayered to Diffusion 1-2
Overview 5 Materials Analysis 5.1.1 SEM Cross-Section Showing Dielectric Levels 5.1.2 SIMS Profile Through the Dielectrics 5.2.1 TEM Cross-Section of Metal 8 5.2.2 TiN Cap Layer 5.2.3 TEM-EDS Spectrum of the TiN Barrier Layer 5.2.4 TEM-EDS Spectrum of the Ti Adhesion Layer 5.2.5 TEM-EDS Spectrum of the Ta Barrier Layer 5.3.1 EDS Spectrum of ILD 1-2 5.3.2 EDS Spectrum of ILD 2-2 5.3.3 EDS Spectrum of PMD 5 5.3.4 EDS Spectrum of PMD 4 5.3.5 EDS Spectrum of PMD 3 5.3.6 EDS Spectrum of PMD 2 5.4.1 TEM-EDS Spectrum of the Gate Polycide 5.4.2 TEM-EDS Spectrum of Source/Drain Silicide 5.5.1 N-Well SRP Plot 5.5.2 P-Well SRP Plot 6 Critical Dimensions 7 Report Evaluation 1.2 List of Tables 3.3.1 Dielectric Thicknesses 3.4.1 Metallization Vertical Dimensions 3.4.2 Metallization Horizontal Dimensions 3.5.1 Via and Contact Dimensions 3.6.1 Transistor and Polycide Dimensions 4.1.1 SRAM Transistor Sizes 1-3
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