Full-Chip Verication Methods for DSM Power Distribution Systems Gregory Steele, David Overhauser, Steen Rochel, Syed Zakir Hussain Simplex Solutions, Inc. Abstract Power distribution verication is rapidly becoming a necessary step in deep submicron (DSM) design of high performance integrated circuits. With the increased load and reduced tolerances of DSM circuits, more failures are being seen due to poorly designed power distribution systems. This paper describes an ecient approach for the verication of power distribution at the full-chip transistor level based on a combination of hierarchical static and dynamic techniques. Application of the methodology on practical design examples will be provided. We will also demonstrate the necessity of an analysis at the full-chip transistor level to verify the complex interactions between dierent design blocks based on static and dynamic eects. 1 Introduction The comparison of the power density for an average microprocessor (ca. 20W / 400 mm 2 = 50kW / m 2 ) and the power density of a large city (ca. 500MW / 100 km 2 =5W / m 2 ) reveals some of the challenges related to the full-chip power distribution verication. Not only is the power density high, but it is also increasing with shrinking transistor geometries and increasing device count. The reduced power supply voltage, increased power density, and thinner wires used in DSM designs are causing an increase in the number of failures related to the power distribution network. Failures are considered excessive voltage drops at the gates due to the sheet resistance of the power supply lines, so called IR drop failures, as well as the growth of voids and shorts at the power supply lines due to electromigration. With the narrow noise margins of a DSM design, severe IR drop due to missing vias or an inadequate power grid can cause functional failures. Less severe IR drop may cause timing problems. A ve percent drop in the supply voltage of a gate can cause a fteen percent increase in the gate delay. Proper gate supply voltage is critical to maintain functionality and performance. Power grid verication is a necessary step in ensuring that a new design will work at its intended speed once fabricated. In DSM, parasitic resistance and capacitance of the power and signal lines have a considerable eect on the actual chip performance, therefore increasing the accuracy requirement for parasitic extraction. For current design technologies, the extraction of linear resistors and capacitors is in general considered sucient but, in the future, inductive eects as well as frequency eects may have to be considered. The eective loading of the power grid caused by parasitic device capacitances and signal lines has to be taken into account during power analysis. Additionally, signal timing and signal slope are aecting power consumption, which increases the accuracy demands for power distribution verication. It is reasonable to start looking for IR drop problems early in the design cycle. As soon as the layout of a functional block is completed, power distribution analysis of this block may be performed. This is referred to as block level analysis. Many common design mistakes may be found by performing block level analysis. However, due to the tight and complex interactions between dierent blocks of the design, an analysis at the full-chip level must be performed to ensure that no IR drop related problems will occur in the assembled design. At this stage all parasitic elements can be extracted based on layout and technology description. The number of resistors in a power grid can be estimated roughly by the number of transistors times the number of metal layers, but the relationship is actually super-linear. Typically, for a design with 5 million transistors in a ve metal layer process, the number of resistors is about 30-40 million. Furthermore, circuit reduction cannot be applied for electromigration reliability verication of the power grid. This demonstrates clearly the demands on the capacity of the verication tools as well as the need for an ecient postprocessing mechanism to quickly pinpoint critical spots in the design. In the following sections, we will use the term "power grid" for a power distribution network even if it is not necessarily a grid based design. We will omit the discussion of techniques for the extraction of the circuit description, the power distribution network itself, as well as the signal interconnect lines. But it is necessary to point out that to perform electromigration analysis, the extractor has to be able to provide layout and geometry information for the resistors comprising the power grid and must provide the location of all circuit elements. Section 2 discusses block-based and full-chip power grid analysis methodology. In Section 3, we will discuss in detail static and dynamic techniques to determine the current loading at the power grid. Section 4 describes dierent methods for analyzing results of the power grid analysis. 1-58113-049-x-98/0006/$3.50 35 th Design Automation Conference Copyright 1998 ACM DAC98-06/98 San Francisco, CA USA
Electromigration verication will be discussed in Section 5 and the application of the described methodology is demonstrated in Section 6. 2 Verication Methodology Power grid analysis for either blocks or full-chip can be divided into two basic phases. Each phase can be varied in complexity and accuracy depending on the stage in the design process where the power distribution analysis is applied. Nevertheless, accurate verication requires consideration at the transistor level. First, the circuit description (behavioral, gate or transistor level) as well as the power grid including parasitic elements have to be extracted from the design database. Secondly, the current distribution in the power grid has to be calculated. This can be done in two dierent ways. One possibility is to calculate the power grid and transistor circuit together. This takes into account the coupled nature of the problem and provides an accurate picture, but also limits the size of the problem that can be handled. The complexity of the problem and run times will limit the application of this method to a block level. Therefore, this technique cannot be applied for nal verication of complex designs such as microprocessors and ASSP's and will not be discussed further. Especially for digital circuits, a more ecient two-step technique can be applied. The rst step is to calculate the current consumption for all circuit elements assuming ideal power supply values using static or dynamic current data, later on referred to as static and dynamic approaches. Different techniques are described in the literature and will be discussed below. The second step is to use computed loading currents to calculate the current distribution in the power grid. The resulting IR drop can be fed back into the rst step to improve the accuracy of the current data drawn from the power grid. Usually, one iteration loop is sucient to get realistic IR drop and current data for the power grid. The separation into two steps allows the exploitation of specialized algorithms during each step which in return improves speed and capacity. Block-based analysis can be applied at dierent stages of the design process. Two possible scenarios can be described, the verication of the local voltage distribution inside a block or the verication of the global power grid based on a block loading abstraction. Both methods can be based on static and dynamic current data and allow a global veri- cation to check for basic violations. This allows easy location of major layout mistakes like omitting a row of vias or contacts. Static simulations are useful for fast analysis of the power distribution trends in the design, whereas dynamic simulations can pinpoint problems due to simultaneously switching gates within a block. Additionally, vector-based dynamic analysis provides a much better coverage and through-put on a block level versus full-chip simulation. This allows verication of the dynamic behavior in much greater detail. In order to perform a block-based analysis, assumptions about the supply voltage have to be made where the block connects to either the global power grid or other blocks. Worst case assumptions should be used in any case for a block-based analysis. Later on, these assumptions have to be veried in a full-chip context. The block can be simulated using current data generated under the assumption that each transistor was operating at the full supply voltage. This approach will overestimate the current data and the results will be slightly pessimistic. Again, the accuracy of the analysis can be improved by feeding back the calculated IR drop at the power grid and repeat the current calculation. Another wayistosimulate the power grid and block together as long as the block size is small enough. Block-based analysis should be performed using both static and dynamic current data as early in the design cycle as is practical. Static analysis should be performed, and changes to the grid structure made, until no further power grid problems appear during analysis. Then a dynamic analysis can be run to ensure that no additional problems occur due to simultaneously switching gates. Even though block-based analysis provides valuable information about power distribution trends and local IR drop data, it is dangerous to base sign-o only on a block-based analysis. The assumptions which enabled block-based analysis may be violated in the full-chip context. The connection of neighboring blocks in the full chip design will frequently inuence the IR drop within the block as current ows through the block to its neighbors. Additionally, it is hard to estimate the potential eects of electromigration in a block-based context, where current may be supplied to neighboring blocks. A full-chip analysis must therefore be performed to validate the assumptions used during blockbased analysis, and for reliability verication after the nal layout of the entire chip has been completed. Since the power in a design is supplied to the blocks through metal lines which are often designed separately from the blocks, the eects of these metal lines on the block supply voltages must be examined. If the designer is only interested in verifying that the block supply voltage is within the specication used for block-based analysis, then it suf- ces to simulate only the upper layers of the grid, down to the level of the blocks. One method is to use the current data at the connection point of each block to its neighbors as well as the global power grid and analyze only the upper metal layers of the grid. Full-chip IR drop analysis should be performed in both static and dynamic modes. Dynamic current data gathered during detailed block based dynamic verication may be reused during full-chip verication [1]. Full-chip analysis often reveals problems with the power grid which were not evident from the block-level analysis. The power supply for blocks near the center of the chip may be routed through neighboring blocks which are not prepared to handle the additional current load. These blocks which appeared ne during block level analysis could show excess voltage drop due to current drain of their neighbors. One of the worst cases is, for example, the supply of a high activity data path through a neighboring RAM for which the power supply was designed with the assumption of a low current drain. 3 Current Calculation 3.1 Static Approach A static approach to calculate the currents is useful as a rst step in power grid analysis. Practical experience has shown that most major power grid design problems will show up during analysis based on static current data. Additionally, performing static analysis is much faster than a dynamic one, allowing a designer to make several iterations quickly while making changes to a portion of the power grid. Very simple and fast current estimates can be generated
by calculating the Id-sat of the devices connected to the power grid. Usually this current data must be calibrated (i.e. scaled) so that the average power consumption is equivalent to that of the actual circuit. The availability of parasitic capacitance data is not required, which allows a fast qualitative analysis on a power grid design. An amazingly large number of weak spots, design aws, and mistakes in the power grid design may be found very quickly. The most appealing advantage of this approach is simply the achievable turn-around time. However, the results have to be carefully interpreted. The current calculation based on Id-sat frequently indicates potential problems in portions of the design with low switching probabilities, such as cache RAMs. These errors are not real, since in reality only a few of the transistors in these parts of the design will be active atany given time. Therefore these IR drop problems must be ignored during Id-sat based static analysis. A much more accurate static calculation can be performed by considering the amount of charge drawn from the power grid during each clock cycle based on the switching activity at the gate level. The accuracy of this approach depends heavily on accurate device and interconnect capacitance data as well as the accuracy of the actual switching probability. Switching data can be derived from probabilistic analysis as well as vector-based simulation at the behavioral, gate or transistor level [2], [3], [4], [5]. The average power dissipation for each gate can be expressed by the relatively accurate approximation [6]: P avg =1=2 C L V dd P s f (1) whereby C L is the eective loading capacitance seen by the gate, V dd the supply voltage, P s the switching probability and f the clock frequency. Static current values estimated in this way are generally very close to actual average current values, and are therefore very useful for electromigration analysis. This also avoids some of the problems encountered using only Id-sat based current calculation in areas with low switching probabilities. 3.2 Dynamic Approach Dynamic analysis has to be performed to verify instantaneous voltage drops at the power grid due to simultaneously switching gates. Just after a clock transition, many ofthe gates in a design begin to switch simultaneously, causing peak current consumption and peak IR drop on a power grid. This eect will not be seen using a static current calculation, which is the reason a dynamic verication must be performed for sign o. The dynamic peak IR drop will cause additional delays until the signals settle and may cause timing conicts in aggressive designs, especially if cycle stealing techniques are used. A representative set of vectors has to be used for dynamic IR drop analysis. Ideally a large set of vectors would be simulated to ensure that no IR drop problems occur under operating conditions. However this is impractical due to the simulation time that would be required to run a large set of vectors. Dierent techniques have been proposed to either reduce the number of vectors to be considered for a dynamic analysis [2] or to nd a subset from all possible input stimuli representing a similar power distribution [7], [8]. In practice, only a few tens of vectors are used to identify IR drop problems. Dynamic power grid analysis presents some unique challenges due to the size of the problem as well as the time required to perform dynamic simulation at the transistor level. To reduce the time required for performing dynamic simulation at transistor level, macro modeling techniques based on gate-level simulation have been proposed [9], [10] and are utilized during synthesis and optimization. Because of the accuracy required for nal verication, transistor level analysis that takes into account the interdependency of power consumption, signal delay and slope degradation is still required. Due to the time required to simulate the entire power grid once, it is undesirable to simulate the power grid over many clock cycles. A compaction technique has been developed which reduces current data, calculated from a simulation lasting several clock cycles, to produce a current prole for a typical cycle [11]. The compaction method averages the current data, so the calculated IR drop is slightly pessimistic. This technique not only decreases the necessary time interval for the power grid simulation itself, but it also provides average data usable for electromigration analysis. 4 Analyzing Power Grid Data Due to the immense quantity of data generated during power grid analysis, data pruning has to be applied before reporting results. Application-dependent data ltering ensures that only critical sections of the design need to be investigated in detail. A visual plot is extremely useful for tracking down the elements of a design that are contributing to excessive IR-drop or electromigration problems. During static IR-drop analysis with Id-sat data, the absolute value of the voltage on each node is not particularly meaningful. The important aspect to observe is the voltage distribution trends in the design. Frequently one or two areas of a design are found to be operating at much lower voltages than the rest of the chip. This indicates that the portion of the power grid supplying these areas may be insucient and that more accurate analysis, such as activitybased static analysis, has to be performed on those portions of the design. Examining the current distribution in the power grid shows the source of the supply current for a block. Especially for blocks with IR problems, the expected source from visual inspection of the power grid and the real source dier signicantly. Activity-based static analysis and full dynamic analysis produce meaningful data values that may be compared to design specications for sign-o purposes. Any portions of the design that exhibit excessive voltage drop with activitybased current data should be carefully inspected to locate the cause. Changes should be made until this condition is corrected. 5 Electromigration Analysis Full-chip reliability analysis has become more critical because advances in technology are yielding narrower interconnect structures and higher-frequency designs. This combination increases the risk of electromigration and joule heating failures in designs. Performing power grid reliability analysis on designs with tens of millions of resistors in the grid requires new techniques. Traditionally, designers are given simple layout design rules based on wire current density limits to which they must adhere. These limits, set to provide reliability over a broad range of circuit congurations, can make high-speed designs excessively large or impossible to design. This indicates that a methodology for reliability budgeting is needed
Figure 1: Static IR drop with removed connection between blocks Figure 2: Static Full chip current distribution for the initial version of the design to permit engineering tradeos between performance, design size and lifetime. This methodology must analyze the circuit to obtain realistic estimates of actual currents owing in the circuit; apply advanced electromigration models to wire segments, usually based on Black's equation; and perform statistical analysis over the wires in the design to estimate the probability of the chip operating properly over its lifetime. With growing chip complexities and power grid redundancies designers no longer understand exactly how their chip operates. Due to complex power grid and distributed blocks in a design, current owfromachip pin to the gates cannot be determined without full-chip analysis. This is one of the reasons that Full-chip electromigration analysis nds design problems. The current owing in the chip may be taking a completely unexpected route, through failure prone portions of the power grid. A methodology has been developed to permit analysis of the complete power grid. This methodology includes extraction of chip interconnect data without the application of interconnect net reduction or contact clustering, static and dynamic full-chip analysis to determine current loading characteristics at the various device contacts to power grid, and modeling mechanisms to report either wire segments likely to fail or overall chip lifetime statistics. Full-chip reliability analysis is part of the power distribution verication process and can be carried out in parallel with IR drop analysis. The ability to apply reliability analysis at the full-chip level makes it possible to bring product reliability and reliability budgeting into designers hands. Power grid electromigration analyses require the creation of models for a chip. Model data is provided for each metal and via layer in the chip. Each metal layer model provides the layer thickness; current density limits for peak, average, and RMS currents through wire segments (dierent foundries provide dierent rules) for simple threshold checks; and a set of model parameters for the mean time to failure (MTF) model. Dierent model parameters may be applied for narrow wires and wide wires, where an additional model parameter denes the boundary between narrow and wide wires. Each via and contact model provides the current limits for peak, average, and RMS currents through each via/contact for simple threshold checks, and a set of model parameters for the MTF model. An MTF model can be based on Black's equation or some other model. Since the actual MTF value for an individual component can be misleading, and because the MTF values of relatively reliable components can vary overavery wide range, it is more useful to examine the inverse of the MTF. The inverse of the MTF is referred to as EM risk - the risk that the design will fail during the time of operation. During reliability analysis, the components with larger EM risk values are the ones most likely to fail. The power grid of a chip is operated primarily in a pulsed DC sense with respect to electromigration analysis. Therefore average current data throughout the circuit is used to perform electromigration analysis on the grid. Because the frequency is above 100kHz, the full-chip transistor analysis tool provides the average current drawn by each transistor connected to the power grid. One at a time, each power grid is modeled by voltage sources at the pins, providing power to the chip and the transistor tap currents at the device connection points. The large linear system is then solved to determine the precise current owing through every wire segment and via in the chip. Once each wire segment current density has been determined, the simple checks are applied to identify those wires in the design which exceed the threshold. A more detailed analysis of the reliability is made by calculating the theoretical time to failure and EM-risk value for each element and using the proper failure statistics to obtain a failure probability as a function of time for the entire chip. The results are highly dependent on the choice of the statistical model used. Extreme value lognormal, also known as multilognormal statistics, is used, assuming the
Figure 3: Static IR drop analysis results with improved power grid Figure 4: Electromigration analysis results on an improved power grid failure probability to be that of a chain that fails at the weakest link. The links are assumed to be lognormally distributed. Since the wire segments with highest EM risk are identied, these can be provided to the designer for an engineering change order (ECO) if the overall chip probability is below specication. Improving the reliability of the least reliable elements in the design will drastically increase the overall MTF of the design. 6 Example A modied design of a multi-media chip with 1.6M transistors has been used to demonstrate the capabilities of the proposed methodology. Figure 1 shows the result of an static IR drop analysis. Loading currents have been calculated as described above and are scaled according to the switching activity ineach block. The highest voltage drop is represented in the darkest (red) color, giving an immediate feedback to the designer, which blocks are the most critical one as well the location of the critical spots inside the blocks. It is clearly visible that the large block in the middle draws current from its neighbors, causing remarkable voltage drops in the surrounding blocks. It is interesting to see, that the missing power connection from the lower part of the chip to the upper right block causes an excessive IR drop in the lower left corner of that block. The result of a current distribution analysis is shown in Figure 2. It has to be pointed out, that this level of detail about the operation of the circuit can only be extracted by a full chip analysis. The current distribution analysis on the chip enables designer to gain knowledge of the current paths between the blocks as well as inside the blocks and in this way allowing them to correct the problem. The results of a static IR drop analysis on an improved design version is shown in Figure 3. The upper and lower blocks are now connected. Current distribution changed in such away, that the IR drop in the lower left logic block is reduced, but now an IR drop in the memory block is introduced. Another interesting eect is revealed by performing electromigration analysis on the design as shown in Figure 4. First the analysis shows clearly, that the connection is not sucient to carry the introduced high current density over a longer period of time and will eventually fail during the lifetime of the chip. Second electromigration problems have been detected at points far from the location of the modication. This problems are also marked with dark (red) colors to be able to easily spot the problems. Even if every block is properly designed by considering IR drop and electromigration, problems caused by the connection between the blocks cannot be detected by an analysis on the block level emphasizing the importance of nal verication at full chip. Figure 5 shows the IR drop on a further improved design version. In this case the attempt was made to avoid electromigration problems and to minimize the IR drop across the chip. The analysis results on the nal design version show, that the attempt was successful and the excessive IR drop in the large block at the upper right side of the chip has been avoided. Additionally, the coupling to the neighboring blocks has been reduced and a more uniform IR drop distribution across the chip achieved. A snapshot of the IR drop during dynamic analysis of a clock cycle is shown in Figure 6. This example was captured immediately after the clock switched. The comparision between static and dynamic analysis shows that the global IR drop is approximated very well. Besides the inherent dierences of the static and dynamic approach, local dierences are caused by inaccuracies of the underlying switching probabilities and the test vectors used for dynamic analysis. The results validate the experience of the authors, that most of the design problems related to power distribution can be detected using static techniques.
Figure 5: Static IR drop analysis results with proper power grid Figure 6: Snapshot of the dynamic IR drop immediatly after clock switching (power grid itself is not drawn) 7 Conclusion Due to the advancement in fabrication and design technology, power grid analysis has become a necessary step in the verication of new designs. The quality of the power grid has a signicant eect on the timing and reliability of a design. In the future, new materials such as copper, with lower sheet resistances and higher resistance to electromigration, will be used for power distribution and interconnect lines. This will increase performance and improve reliability, but this advantage will quickly be diminished by increasing device density and higher operating frequencies. Power grid analysis will continue to be an important part of the design verication process. A methodology has been described, which allows the application of full-chip power grid analysis, permitting the validation of power supply voltages at every gate in the design as well as the reliability of the power grid. The combination of dierent techniques makes it possible for designers to determine critical voltage drops and reliability weak spots at the full-chip level, taking into account the interdependency of adjacent blocks in terms of power ow. The authors would like to thank R. Saleh and M. Benoit for valuable discussions and support. References [1] Lightning V1.2 Power-Distribution Verication Manual. Simplex Solutions, Inc., 1997. [2] Chi-ying Tsui, Radu Marculescu, Diana Marculescu, and Massoud Pedram. Improving the eciency of power simulators by input vector compaction. In Design Automation Conf., pages 165{168, June 1997. [3] Joseph N. Kozhaya and Farid N. Najm. Accurate Power Estimation for Large Sequential Circuits. In Int'l Conf. on Computer Aided Design, pages 488{493, November 1997. [4] Yong Je Lim, Kyung-Im Son, Heung-Joon Park, and Mani Soma. A Statistical Approach to the Estimation of Delay-Dependent Switching Activities in CMOS Combinational Circuits. In Design Automation Conf., pages 445{450, June 1996. [5] Li-Pen Yuan, Chin-Chi Teng, and Sung-Mo Kang. Statistical Estimation of Average Power Dissipation in Sequential Circuits. In Design Automation Conf., pages 377{382, June 1997. [6] H.J.M. Veendrick. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buer circuits. IEEE J. Solid-State Circuits, SC-19:486{473, August 1984. [7] Radu Marculescu, Diana Marculescu, and Massoud Pedram. Hierarchical Sequence Compaction for Power Estimation. In Design Automation Conf., pages 570{575, June 1997. [8] Angela Krstic and Kwang-Ting Cheng. Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits. In Design Automation Conf., pages 383{388, June 1997. [9] Subodh Gupta and Farid N. Najm. Power Macromodeling for High Level Power Estimation". In Design Automation Conf., pages 365{370, June 1997. [10] Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, and Bruno Ricco. Gate-Level Power and Current Simulation of CMOS Integrated Circuits. IEEE Trans. VLSI Syst., 5(4):473{487, December 1997. [11] Thunder V1.2 Transistor-Level Verication Manual. Simplex Solutions, Inc., 1997.