Interconnecting the next generation of electronics

Ormet Circuits Inc. Interconnecting the next generation of electronics

Overview Ormet Circuits provides conductive pastes that enable electrical interconnection and thermal management in electronic substrates, components and assemblies. 2

Ormet is Focused on Markets Requiring Advanced Electrical Interconnects PCB Fabrication Core to Core PCB Fabrication Any-Layer Interconnects Semiconductor Die Attach Semiconductor Assembly Interconnects High Layer Count Printed Circuit Boards Printed Circuit Boards For Smartphones and Tablets Power ICs LEDs Power Discretes Wirebond Replacement Wafer Level Packaging Patented sintering technology platform enables Green Electronic Assemblies Ormet targeting high growth applications in PCB and Semiconductor Packaging Materials Markets 3

Ormet s Materials Are a New Electrical Interconnection Technology Industry currently uses several technologies to form electronic interconnections Copper Plating Printed circuit boards Time consuming with poor yield for new designs Solder IC packaging for power devices High temperature processes reduce reliability Environmental concerns Metal filled polymers Conductive Adhesives are used as an alternate to solder in some applications Copper pastes have limited electrical and thermal properties 4

Transient Liquid Phase Sintering

Ormet s Patented Technology is Called Transient Liquid Phase Sintering (TLPS) Liquid Paste Before Cure Sintered Network After Cure Copper and alloy particles in a liquid organic formulation Sintered metal network 6

Ormet s TLPS Materials Do Not Remelt After Cure DSC Analysis of Ormet 700 Lead Free Composition Cure Process showing sintering Second thermal cycle, no re-melt below 265ºc. 5/2/08 7

Ormet s Paste Materials are Formulated with Fine Metal Powders Point Copper Tin Bismuth 1 98.48 1.52 2 100 3 100 8

After Cure, Ormet Materials Form a Sintered Metal Network Point Copper Tin Bismuth 1 52 47 2 70 29 3 54 45 4 71 28 5 100 9

Ormet Materials Are Thermally Above Pb-free Solder Reflow Temperatures Bismuth Melt 267 C 10-16% of total matrix Copper Melt 1085 C Cu 3 Sn intermetallic Melt 640 C Cu 6 Sn 5 intermetallic Melt 415 C Direction of tin migration 10

Ormet Circuits Provides Enabling Materials Technology Low temperature metallic joining Processing temperatures between 175-205C Compatible with Pb-free solder reflow profiles Thermally stable up to 280C Superior shear strength versus conductive adhesives at elevated temperatures Metallic joining 25%+ higher strength versus adhesives Pb-free & Halogen-free composition Copper and Tin/Bismuth alloys Excellent Electrical and Thermal Conductivity <100 uohm-cm volume resistivity 15-30 W/mK Thermal Conductivity 11

Only Ormet Circuits Lead-free Interconnects Enable Low Cost Smartphone Circuit Boards The growth of mobile electronics has created an urgent need for a better manufacturing approach: Faster production cycles Lower cost Environmentally friendly High cost plated PCB Low cost Ormet Interconnects

Advantages of Paste Interconnects EI Confidential Smaller vias (2-4 mils) Smaller antipad in power plane 2S1P Low speed High Density Wiring 2S1P High speed Wiring Paste interconnects can dramatically increase density in substrates

Ormet s Technology is Proven in in High Reliability Applications High Performance Computing Semiconductor Test (ATE) RF Applications Military Ormet Interconnect Elimination of Plating for Vias Ormet Interconnect Ormet Interconnect Source: DDI Corp. Ormet s high reliability interconnect technology is moving from low volume applications to high volume markets. Source: Endicott Interconnect Technologies

3rd Party TLPS Interconnect Reliability Data Shows Ormet Meets Reliability Requirements Test Test Conditions Result Thermal shock -55-125,500 cycles Pass, Max resistance change 7.5% Temp Cycling 0-100,1000 cycles Pass Humidity + bias testing 85,85RH%, 50V bias,hold 240 hrs Pass Humidity + Thermal Aging High Temperature Storage 85,85RH%, hold 1000hrs Pass, Max resistance change 4.0% 150, hold 1000h Pass, Max resistance change 7.0% Solder reflow test Reflow @ 260,5cycles No delamination Electrical test No shorts or opens Pass Ormet interconnects are well established in HDI and high layer PCB applications. 15

Paste Interconnects have Robust Performance at High Frequency Reference: Das, Rabindra, Egitto, Frank, Lauffer, John, Antesberger, Tim, and Markovich, Voya, Z-axis Interconnections for Next Generation Packaging, Advanced Microelectronics Vol 38 No.6, pp12-19

Ormet Interconnects Demonstrate Stable Electrical Performance in Stress Testing

Sintered Pastes Can Enable Thin Substrates and High Via Density 50 microns 50 microns Sintered Paste Microvia Ormet materials can support small microvia diameters through high strength metallic bonding to copper catch pads. Via diameters less than 125 microns may not be possible with non-sintering paste materials Via diameters of 75-100 microns may be required to support 0.3mm BGA pitch technology

Power IC and LED Die Attach Interconnecting the next generation of electronics Ormet Circuits Confidential

Ormet s Die Attach Materials Enable Lead-free Power Semiconductors Ormet Die Attach Ormet Die Attach Opportunity drivers EU regulatory ban on Lead compounds in electronics Other technologies do not meet customer requirements High cost of precious metals In qualification at major Power Semiconductor companies

Large & Rapidly Growing Market for Power Semiconductors Requires New Materials Increasing complexity of Power Semiconductor packaging solutions has created a new market for enabling materials. Ormet s Lead-free materials enable High yield fabrication processes System in package strategy at low cost Alignment to industry environmental impact and recycling roadmaps Single chip FET with clip System In Package FET + IC with clip High Complexity System In Package 21

Ormet s Patented Technology is Differentiated from Competing Technologies Ormet Meets Reliability Requirements Competition is not stable after Reliability Testing Ormet Competition Electrical Resistance (mohms) 5 4.5 4 3.5 3 2.5 2 1.5 1 Reliable Performance after stress testing 0 20 40 60 80 100 120 140 Units x0 IR X5 IR Electrical Resistance (mohms) 5 4.5 4 3.5 3 2.5 2 1.5 1 Performance is unstable after stress testing 0 20 40 60 80 Units Initial Post-Stress Stable electrical performance is critical to semiconductor devices and differentiates Ormet from competitors.

Die Attach Reliability Testing Industry desire to replace: Pb-based solders in Power IC Au-based solders in LED applications Conductive Epoxy Ormet materials offer superior electrical performance.

Ormet Product Properties Ormet 555LV2C Cone & Plate type Brookfield viscometer Spindle # : CP 51 @25C Ormet 555LV2P Ormet DAP-279 Viscosity, (cp) 0.5rpm 75,000 56,000 94,000 5.0rpm 38,000 25,000 52,000 Thix. index 0.5/5.0 2.0 2.2 1.8 Electrical Conductivity Thermal Conductivity Cure Profile µohm-cm <100 <100 <100 W/mK 14 22 30 45 minute ramp to 205C + 90 minutes at 205C 45 minute ramp to 205C + 90 minutes at 205C 60 minute ramp to 240C + 30 minutes @ 240C Good rheological properties for dispensing and printing applications

Ormet Die Attach Materials Can be Applied Directly to the Wafers and Create a New Paradigm Wafer applied materials greatly simplify assembly of semiconductors and significantly reduce costs Ormet s cooperation programs with industry leaders

Sintering Film Technology The metallurgical bonds formed to the metal leadframe and metalized die backside are key to Ormet technology The metallurgical bond is a mechanical bond that enables high 260C die shear strength, high thermal conductivity and high electrical conductivity Ag-Backed Die Metallurgical bond is structurally different from a typical adhesive bond Metallurgical Bonding of Tin to Ag Backside of Die Resin Continuous Metallurgical Pathway from die to Leadframe Tin Ag-Plated Copper Leadframe Copper Particles Metallurgical Bonding of Tin to Leadframe

Cross Section of Power Die Attach Film Targets: Film Thickness: 25-50 microns Wafer size: 100, 200, 300 mm wafer diameters Wafer lamination temperature: 60-100C Electrical resistivity: <300 µohm-cm Thermal conductivity: >10W/mK Die shear strength @ 260C: >0.5 kg/mm 2

Fillet Images After Die Attach 150 C Die Attach Temp 180 C Die Attach Temp 200 C Die Attach Temp Die Attach After Film Stored in Ambient Conditions for 1 week. Shelf life studies post-dicing are ongoing. Die attach process window (force, temperature, time) is in development.

Flash Memory Interconnecting the next generation of electronics

IC Packaging: Wirebond Replacement Source: Vertical Circuits Innovative IC packaging solution for portable memory

Ormet Materials Can Replace Wirebonds in Stacked Die Flash Memory Applications 8 Die Stack Flash Memory Device Photo courtesy of Vertical Circuits Memory capacity in smartphones and tablets is growing rapidly 80% reduction in size of components using Ormet enables more memory in next generation of smartphones Elimination of Gold wires dramatically lowers cost

Component Attach Interconnecting the next generation of electronics

Ormet for Capacitor Attach Passive components attached with Pb-free solder inside semiconductor packages are a reliability risk when exposed to solder reflow temperatures during component attach. Ormet s technology can reduce the passive attach processing temperature, and will not reflow during subsequent Pb-free reflow profiles

TLPS Advantages for Component Attach Ormet materials for component attach offer key advantages: High temperature stability 300C+ Elimination of step soldering, and use of complex solder alloys No flux residue

Summary Ormet is a leader in advanced electrical interconnect materials for PCB and semiconductor applications Transient Liquid Phase Sintering materials have many of the advantages of solders and conductive adhesives Low processing temperature High thermal and electrical conductivity Ormet materials enable customers to meet next generation device requirements Low cost PCBs for mobile applications Pb-free assembly materials for Semiconductor Packaging High density flash memory packaging for mobile devices

Reference Information

Advantages of Z-Interconnect Smaller vias (2-4 mils) Smaller antipad in power plane Small Capture pad (~8mils) Low speed High Density Wiring Ormet Paste No stub/ backdrill hole obstructions for wiring channels Zero via stub High speed Wiring Package using Z Interconnect Structures

Advantages of Z-Interconnect Best signal / power integrity: Zero stub length by construction no backdrill required zero signal reflection / loss due to stubs Via size minimization (<4 mil vias vs 10+ mil PTHs) Smaller capture pad size Opens up more wiring channels Lower via capacitance Lower cross talk vs PTH designs Smaller impedance discontinuity Smaller anti-pads in power / ground layers Reduction in inter signal-plane crosstalk Reduction in power plane current crowding

Advantages of Z-Interconnect Best signal / power integrity cont.: P3 power plane construction provides best high power delivery solutions Thin power plane dielectric layers with minimum power plane inductance Heavy copper provides minimal IR drop for high current applications Embedded pre-testable capacitance layers allow high performance decoupling for extremely high speed application with lowest path inductance Best wiring density Lower layer counts / higher wiring density for equivalent design More wiring channels due to: Smaller vias / capture pads Less wiring blockage Smaller antipad size allows denser wiring in adjacent signal planes due to low cross talk No stub / backdrill hole obstructions for wiring channels Enables finer BGA / LGA / via pitch