CHAPTER 5 Bipolar Transistor and Related Device
Bulk p+ p+ Buried layer Figure 5-1. Perspective view of a silicon p-n-p bipolar transistor.
E = B +C PNP, 以 hole carrier 為主, p+ 為 emitter 電壓, 電流, 極性都相反. NPN, 以 electron carrier 為主, n+ 為 emitter Figure 5-2. (a) dealized one-dimensional schematic of a p-n-p bipolar transistor and (b) its circuit symbol. (c) dealized one-dimensional schematic of an n-p-n bipolar transistor and (d) its circuit symbol.
Figure 5-3. (a) A p-n-p transistor with all leads grounded (at thermal equilibrium). (b) Doping profile of a transistor with abrupt impurity distributions. (c) Electric-field profile. (d) Energy band diagram at thermal equilibrium. e 熱平衡, 無電流,EF 是平的 h
Figure 5.4. (a) The transistor shown in Fig. 3 under the active mode of operation. 3 (b) Doping profiles and the depletion regions under biasing conditions. (c) Electric-field profile. (d) Energy band diagram. Forward electron Reverse Hole 越過 EB junction 後, 若 Base 很窄, 則會大部分被 C 收集. Base 很寬就不是 Transistor, 所以二個背對背之 Diode 不等於 Transistor.
0 w BB : 補充電子 Cn : 熱產生之電子 Figure 5.5. Various current components in a p-n-p transistor under active mode of operation. The electron flow is in the opposite direction to the electron current.
En :B 到 E 之電子流, 越小越好 (p+ 很濃,heterojunction) Common-base current gain : 1 CB : Ri 小,Ro=Rc 大, Current follower. (5)
Emitter efficiency Base transport factor (En ) (6) (7) ( BB, W B, N B ) (8) CB current gain = (emmitter eff)*(base transport factor)
(9) 令 Cn= CB0 (10) 指 EB open Common base
Active mode Continuity eq. for E=0 (Chap 3 eq.(61) ) (11)
分解為 : (12) B.C. EB forward(13a) BC reverse (13b) Ref. Fig. 5.6 ( 後面 )
(14) f W/Lp<<1 (15) linear
(16) B.C (17) (18) (19)
W/Lp<<1 (20) (21) 越小越好 (22) (23)
=EP+En (24) =cp+cn (27) 又 a12=a21 (30)
for rev P+ N P W 大時 Figure 5.6. Minority carrier distribution in various regions of a p-n-p transistor under the active mode of operation.
Summary : 1. B, C 受 V 影響, 正比 exp(qv/kt), continuity eq. 2. C, E 可由邊界之少數載子梯度表示. 3. B=E-C Emitter eff. (31) E (31a) 欲使 γ 1 1. NB/NE 2. W
Analog : active, chip driver Digital : sat. cutoff 若寬 P+ N P 若寬 Figure 5-7. Junction polarities and minority carrier distributions of a p-n-p transistor under four modes of operation.
VBC 使 BC forward 注意 C 仍未變 X V BC Figure 5-8. (a) Common-base configuration of a p-n-p transistor. (b) ts output current-voltage characteristics.
解釋 act. 解釋 sat. BCJ forward (VBC<0) VBC= -0.8V CBJ reverse 變化不大所以 C 不變 VBC Figure 5.9. Minority carrier distributions in the base region of a p-n-p transistor. (a) Active mode for V BC = 0 and V BC > 0. (b) Saturation mode with both junctions forward biased.
Base Width Modulation CE 才是最常用的 (A 很大 ) C C C 0 ( ) CEO 0 B 0 C 0 CBO B 1 1 0 C B E common-emitter current gain (1 B CBO 1 0 CEO 0 ) CBO 0 0 * α 0 = γ*α T 無 B 之 C 大小 CEO ~β 0 * CBO (35) (36) (37)
O/P V CB >0 Early effect /P V A Figure 5.10. (a) Common-emitter configuration of a p-n-p transistor. (b) ts output current-voltage characteristics.
Figure 5.11. Schematic diagram of the Early effect and Early voltage V A. The collector currents for different base currents meet at V A.
Figure 5-12. (a) Bipolar transistor connected in the common-emitter configuration. (b) Small-signal operation of the transistor circuit.
Figure 5-13. (a) Basic transistor equivalent circuit. (b) Basic circuit with the addition of depletion and diffusion capacitances. (c) Basic circuit with the addition of resistance and conductance.
P B B qv( x) p( x) A W dx W 0 v( x) 0 速度 W 2D W 2 P 分佈 qp( x) A dx P (42) (43) (44) ( 基極傳導時間影響 freq. response) Figure 5.14. Current gain as a function of operating frequency. D ( 用 electron 之 Dn~3Dp 即多為 npn BJT)
sat. cutoff CEO Figure 5.15. (a) Schematic of a transistor switching circuit. (b) Switching operation from cutoff to saturation.
B X sat Figure 5.16. Transistor switching characteristics (a) nput base current pulse. (b) Variations of the base-stored charge with time. (c) Variation of the collector current with time. (d) Minoritycarrier distributions in the base at different times. cutoff Q B X cutoff Storage time delay E B C dp/dx~const sat.c 不變 (V CB >0) linear (V CB <0) V CB =0
En majority, Ep 抑制, 增加 γ Figure 5-17. (a) Schematic cross section of an n-p-n heterojunction bipolar transistor (HBT) structure. (b) Energy band diagram of a HBT operated under active mode.
Figure 5-18. Current gain as a function of operating frequency for an np-based HBT. 8
最重要的 BJT 電特性圖
Figure 5.19. (a) Device structure of an n-p-n Si/SiGe/Si HBT. (b) Collector and base current versus V EB for a HBT and bipolar junction transistor (BJT). Compatible with Si standard technology
Graded base, ε bi Current gain, f T 不同材料形成之 junction (Eg 不同 ) Figure 5.20. Energy band diagrams for a heterojunction bipolar transistor with and without graded layer in the junction, and with and without a graded-base layer.
Figure 5.21. Energy band diagram for the ballistic collector transistor (BCT). 9
Figure 10.27
Figure 10.29
Thyristor (high power,voltage switch) Figure 5-22. (a) Four-layer p-n-p-n diode. (b) Typical doping profile of a thyristor. (c) Energy band diagram of a thyristor in thermal equilibrium. i 大,area 大,uniform 要好 For high voltage n1 為 bulk (NTD wafer) P1,P2 為一起 dope n2 為 high dope (P2<P1)
*CMOS 之 latch-up 阻抗很小 阻斷 hold 阻抗很大 breakover 電壓 breakdown Figure 5-23. Current-voltage characteristics of a p-n-p-n diode.
Q1 Q2 Figure 5.24. Two-transistor representation of a thyristor. 2 Q1:PNP Q2:NPN
Q1: Q2: ) ( ) 1 ( 1 1 1 1 1 1 1 1 1 CBO E C E C E B 1 1 ) 1 ( 1 為 Q1 之 CBO 2 2 2 2 2 2 E C 2 為 Q2 之 CBO 令 B1 = C2 ) ( 1 ) (1 2 1 2 1 2 2 1 1 CBO 之和 α1+α2~1 時,break over VAK, α1,α2 不大時, α1, α2 <<1
Figure 5.25. Depletion layer widths and voltage drops of a thyristor operated under (a) equilibrium, (b) forward blocking, (c) forward conducting, and (d) reverse blocking. (d) Breakdown 由 J1 決定 (b) 若在 P2 加入 g,α2 ( α1+α2 ~ 1) 則能在小 V 進入 (c) 以 g 控制 thyristor 全在 act 全在 sat E C for 大部分壓降 B rev C for for for B E for α1+α2 ~ 1 V --
SCR: 矽控整流器 ( 即在 PNPN 加 -gate) Figure 5.26. (a) Schematic of a planar three-terminal thyristor. (b) One-dimensional cross section of the planar thyristor. E B C C B E
PNPN 受到外界之破壞, 產生 g g 上升則 latch-up 越易發生 5 10 g 上升則 leakage 上升 Figure 5-27. Affect of gate current on current-voltage characteristics of a thyristor.
SCR 之應用 CKT Figure 5-28. (a) Schematic circuit for a thyristor application. (b) Wave forms of voltages and gate current.
Figure 5.29. (a) Two reverseconnected p-n-p-n diodes. (b) ntegration of the diodes into a single twoterminal diode ac switch (diac). (c) Current-voltage characteristics of a diac.
Figure 5.30. Cross section of a triode ac switch, a six-layer structure having five p n junctions.
Figure 5.31. Comparison of the structure and electric field for the same forwardblocking voltage: (a) the asymmetric thyristor and (b) the conventional thyristor. Asymmetric: 因為 n+, 只要 deplete 一點優點 : n1 變薄, Von, t(on) T(off) (stored Q )
Figure 5-32. The gate turn-off thyristor with a negative voltage applied to the gate. The main applications of thyristors. 10
Figure 5-33. The main application of thyristors. 10