CMPE328 Microprocessors (Spring 27-8) Memory and I/O address ecoders By r. Mehmet Bodur You will be able to: Objectives efine the capacity, organization and types of the semiconductor memory devices Calculate the chip capacity and organization of memory chips from their pin layouts. Compare various kinds of memory devices according their volatility, access time, and per bit prices. iagram various kind of memory address decoding circuits. iagram the address map of the devices in a memory address space. escribe 6 bit memory access circuits. CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 2 Memory Fundamentals Memory Capacity: measured in number of bits. Memory Organization described in number.of.words wordsize Word-size is determined by the number.of.data.lines on the chip. Example is an EPROM with 8-data and 3-address lines: organization: 2 3 x 8-bit = 8k x 8-bit capacity: 64 kilo bit. CMPE328 Spring 27-8 Section. r.mehmet Bodur, EMU-CMPE 3 CMPE328 Spring 27-8 Units of Memory Capacity bit stores one of two cases. Either, or. No other value is possible nibble = four bits. It stores one of 6 cases. BC digits, hexadecimal digits, etc. byte = 8-bit. It stores one SCII character. kbit = 2 bits = 24 bits lmost one page of alphanumeric text. kbyte = 2 Bytes = 24 x 8 bits. ddress lines to 9 specifies 24 locations. MByte = 2 2 Bytes = 24 kbytes Gbyte = 2 3 bytes = 24 Mbytes Section. ddress Pins [..9] [..] [..] [..2] [..3] [..4] [..5] [..6] [..7] [..8] [..9] Mem Size k 2k 4k 8k 6k 32k 64k 28k 256k 52k M r.mehmet Bodur, EMU-CMPE 4
Section. Section. CMPE328 Spring 27-8 Memory Characteristics Memory Speed: (Memory ccess Time) Read Cycle Time includes read access time and data transfer time Write Cycle Time includes write access time and data write time. Memory Read/Write Cycle time is the maximum of read cycle and write cycle. Other Characteristics Memory Power Consumption Number of write cycles. r.mehmet Bodur, EMU-CMPE 5 Memory Types Read Only Memory (ROM). Masked ROM (the fastest memory device) Programmable ROM PROM also called One Time Programmable ROM 52 x 8bit: T rc <ns) 8k x 8bit: T rc ns Erasable-PROM EPROM (Erased in minutes under UV- lamp) Programming similar to OTP ROM. 2 times programmable 8k x 8bit: T rc 2ns Electrically Erasable- PROM EEPROM In-circuit Programming possible. 5 times programmable Erase or Write takes 5.. 2ms, T rc 2ns Flash ROM. Twc= 5...2ms/block ( 256 B.. 8kB ). times progr. Very large capacities possible ( GByte, access time 2ns) CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 6 27xxx: EPROM 28Cxxx EEPROM 28Fxxx Flash ROM Section. Memory Chips used in Microprocessors Typical ddress ata and Control Lines of a ROM [.. n] ddress lines O[.. n] Output lines. (or ~CS) ctive-low Chip or evice enable isabled device typically consumes m while enabled device draws around 2m. ctive low Output Enable isabled output stays floating (output disconnected) Enabled output delivers the contents of addressed location only after the settling time is over. ~Vpp, and ~PGM are programming related control signals. CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 7 CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 8
Section. Static RM evices Static Random ccess Memory (SRM devices) typical ns < T RWC < 25ns (faster devices are expensive. Fast devices are used for Local Cache.) Various capacities possible. 66 (2k x 8-bit) 6264 (8k x 8-bit) 62256 (8k x 32-bit) NV-RM is a low-power SRM. It has a Lithium Battery and powercontrol circuit. It has infinite write cycle life, and data retention over years. (Config. RM in PC s) NV is abbreviation of non-volatile. 66 Typical Memory Control Lines ~CS ( ~chip select = : ~chip enable) (Write Enable) (Output Enable) CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 9 CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE Section. Section. RM devices use ddress lines multiplexed. Example: 64kx4 bit device needs [..5], but 6 lines are multiplexed to 8 lines. t the edge of CS device holds [...7]. t the edge of RS device holds [8..5]. RM evices Properties of RM RM memory cells are made of two transistors and a capacitor. They are eight times cheaper than ten-transistor-flip-flops of SRM circuits. The charge stored in the capacitor decays in ms. It needs row-refresh circuitry additional to the row-column address multiplexing circuit. The row-refresh and multiplexing requires RM controller circuits. Example: 8-bit row and 8-bit column decoders of 4464 RM works faster than a full 4-bit decoder of 62256 SRM device. For 4464, a RM controller generates 256 refresh cycles at every millisecond. CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 2
Section.2 ddress ecoding ddress ecoding provides systematic generation of memory ~CS signals. The goal of address decoding is to enable only a single memory device Well known methods of address decoding: N-OR-COMPLEMENT, or NN gate logic. Using commercial decoder chips, LS38, LS39. Using PROM, PL, FPG devices. Current Technology uses programmable devices. We will see only by using gates, and decoder devices to understand the decoding process. Section.2 Memory/IO ddress ecoding We limit designs only to SRM and EPROM circuits. We assume complete address decoding. ll address lines must be included to decoding. memory system design shall be accompanied by a memory address map. memory address map is a table of ddress Bus Lines, with corresponding status for each memory or decoder device. CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 3 CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 4 Section.2 Section.2 888 Memory/IO ecoding Circuits CMPE328 Spring 27-8 ddress lines [..9], ata lines [..7] Control lines,, ~MEMW, ~IOR, ~IOW. ROM must occupy the high end of the memory space (. to FFFFFh). r.mehmet Bodur, EMU-CMPE 5 CMPE328 Spring 27-8 Memory data-size expansion p of 2 k m-bit devices are combined to form a 2 k n-bits device, where n=p m. Example, k= 2, (2 2 =4k ) m= 4 ; n=8 ; p=2. 2 (4k 4-bit ) 4k 8-bit [..] [..] [..] r.mehmet Bodur, EMU-CMPE 6 [..3] [4..7] Both devices are active at the same instant. The first device gives first half of data, while second provides the other half [..7]
Memory ddress-space Expansion 2 p of 2 k n-bit devices are combined to form a 2 k+p n-bit device. Example, p= 2, (2 p =4 chips required) n=8 4 (4k 8-bit) 6k 8-bit CMPE328 Spring 27-8 [..3] t a given instant, only one of the devices is active. ctive device depends on decoder output of [2..3] lines. [2..3] S Y Y Y2 E Y3 [..] [..] [..] [..] Section.2 [..7] [..7] [..7] [..7] r.mehmet Bodur, EMU-CMPE 7 [..7] CMPE328 Spring 27-8 ecoder Circuits by NN 888 Example: esign a decoder to select a 276, and three 66 devices: 66, B and C address h. Solution: start with address map Processor 66-66-B 66-C 276 9 8 7 6 5 4 3 2 9 8 Section.2 [4..7] [..3] hex address from h F F. to 7FFh from 8h F F. to FFFh from h F F. to 7FFh from FF8h. to FFFFFh internal decoded address lines are [..] for 66, and [..] for 276. From the map, decide on the inverted/non-inverted inputs of NN. r.mehmet Bodur, EMU-CMPE 8 Section.2 Section.2 esign a decoder to select a 276, and three 66 devices: 66, B and C address h. The blue part is the memory address decoder circuit. The complete circuit is the Memory Sub System. 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 Memory Sub System for 888 Example 2 2 2 [..] 66- [..7] ~MEMW [..] 66-B [..7] ~MEMW [..] 66-C [..7] ~MEMW [..] 276 [..7] ecoder Circuits by NN 888 Example: esign a decoder to select a, and three 66 devices: 66, B and C address h. Solution: start with address map Processor 66-66-B 66-C 9 8 7 6 5 4 3 2 9 8 [4..7] [..3] hex address from h F F. to 7FFh from 8h F F. to FFFh from h F F. to 7FFh from FEh. to FFFFFh internal decoded address lines are [..] for 66, and [..2] for. From the map, decide on the inverted/non-inverted inputs of NN. CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 9 CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 2
Section.2 Section.2 esign a decoder to select a, and three 66 devices: 66, B and C address h. The blue part is the memory address decoder circuit. The complete circuit is the Memory Sub System. 3 4 5 6 7 8 9 3 4 5 6 7 8 9 Memory Sub System for 888 Example 2 2 2 [..] 66- [..7] ~MEMW [..] 66-B [..7] ~MEMW [..] 66-C [..7] ~MEMW [..2] [..7] 74LS38 and 74LS39 ecoders Truth Table of 74LS3 E ~E2 ~E3 C B ~Y ~Y ~Y2 ~Y3 ~Y4 ~Y5 ~Y6 ~Y7 X X X X X X X X X X X X X X X B Truth Table of 74LS39 ~E B ~Y ~Y ~Y2 ~Y3 X X CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 2 CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 22 Section.2 Section.2 esign a decoder to select a, and three 66 devices: 66, B and C address h. Processor 66-66-B 66-C LS39 LS39B CMPE328 Spring 27-8 esign with ecoders We search patterns of address lines that matches to inputs of LS38 or LS39. 9 8 7 6 5 4 3 2 B ----------------- ~E -------------- B We used both halves of LS39 chip. 9 8 [4..7] [..3] hex address from h F F. to 7FFh from 8h F F. to FFFh from h F F. to 7FFh from FEh. to FFFFFh r.mehmet Bodur, EMU-CMPE 23 esign a decoder to select a, and three 66 devices: 66, B and C address h. WITH LS39 decoder CMPE328 Spring 27-8 9 8 GN 3 4 5 6 7 esign with LS39 2 3 4 5 6 7 [..] 66- [..7] ~MEMW [..] 66-B [..7] ~MEMW [..] 66-C [..7] ~MEMW [..2] [..7] r.mehmet Bodur, EMU-CMPE 24
esign a decoder to select a, and three 66 devices: 66, B and C address h. Processor 66-66-B 66-C LS38- LS38-2 CMPE328 Spring 27-8 esign with ecoders Using only LS38, the address map will look like this one. 9 8 7 6 5 4 3 2 9 C B ~Y ~E3 ~E2 C B We used two LS38 chips. 8 Section.2 [4..7] [..3] hex address from h F F. to 7FFh from 8h F F. to FFFh from h F F. to 7FFh from FEh. to FFFFFh r.mehmet Bodur, EMU-CMPE 25 esign a decoder to select a 276, and three 66 devices: 66, B and C address h. WITH LS38 decoders 7 8 9 Vs GN GN CMPE328 Spring 27-8 5 6 esign with LS38 2 3 Vs 4 3 4 5 6 [..] 66- [..7] ~MEMW [..] 66-B [..7] ~MEMW [..] 66-C [..7] ~MEMW [..2] Section.2 [..7] r.mehmet Bodur, EMU-CMPE 26 Section.2 Section.4 esign a memory subsystem to have one 66 address 62h, ~[62h 627FFh] two 6264 RM from 64h, and one 62256 from 68h using LS38 decoders. Processor a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a a a hex address 66 from 62h. to 627FFh 664- from 64h. to 65FFFh 664-B from 66h. to 67FFFh 62256 from 68h. to 6FFFFh LS38- ~E3 E ~E2 C B in an address decoding circuit you can determine the address range of a select output by making non-processed address lines and. CMPE328 Spring 27-8 ~[62h 63FFFh] 8 9 ~[4h ~7FFFFh] 3 4 5 7 6 2 Example-2 [..] ~MEMW [..2] ~MEMW [..2] ~MEMW [..4] ~MEMW 66- [..7] 2kx8bit 6264- [..7] 8kx8bit 6264-B [..7] 8kx8bit 62256 [..7] 32kx8bit r.mehmet Bodur, EMU-CMPE 27 CMPE328 Spring 27-8 ata Integrity of PC Memory ROM memory system. On Power-Up, boot program tests the sum of all bytes in ROM to test any failure of the ROM block. (It is called CHECKSUM test). RM memory system Organized in 9-bit words. There is a parity generator-tester 74S28 When writing data, it puts into 9 th bit a parity bit (that completes the 8 data bits to even parity) When reading data, it tests parity bit. If parity fails, it generates a non-maskable interrupt to give a memory error message. It is called parity-test r.mehmet Bodur, EMU-CMPE 28
6-bit Memory Interfacing 8286 has 6-bit memory system organized in two banks. Bank- (even) connected to [..7] It is ctivated by is low Bank- (odd) connected to [8..5]. It is activated by BHE is low. 6-bit bus doubles data transfer rate.. [..7]. chip select decoding circuit. [8..5]. BHE 74LS245 74LS245 to other even banks to other odd banks Section.5 Look at how the address lines are shifted one bit. Section.5 Memory Bus Bandwidth The data rate of a bus is mostly called the Bus Bandwidth. Bus Bandwidth = bus-width / bus-cycle-time. (measured in MBytes/sec) Example: 888 bus takes 4 processor cycles to carry out 8-bit memory read or write cycles. Find Bus Bandwidth of a 2MHz 888 system. Bus-Bandwidth 888 = byte 2MHz / 4 proc-cyc. = 5 MB/s 8286 bus takes 2 processor cycles for a 6-bit memory read or write. Find Bus Bandwidth of a 2 MHz 8286 system. Bus-Bandwidth 8286 = 2bytes 2MHz / 2proc-cyc = 2 MB/s Buses with wait cycles will have smaller bandwidth. CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 29 CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 3 What is the Next? Next we will start to hardware and software to use IO ports (IO ports). Please solve the problems (p.33) for Section.,.2,.3,.4,.5, CMPE328 Spring 27-8 r.mehmet Bodur, EMU-CMPE 3