Random-Access Memory (RAM) The Memory Hierarchy. SRAM vs DRAM Summary. Conventional DRAM Organization. Page 1

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1 Random-ccess Memor (RM) The Memor Hierarch Topics Storage technologies and trends Localit of reference Caching in the hierarch Ke features RM is packaged as a chip. Basic storage unit is a cell (one bit per cell). Multiple RM chips form a. Static RM (SRM) Each cell stores bit with a six-transistor circuit. Retains value indefinitel, as long as it is kept powered. Relativel insensitive to disturbances such as electrical noise. Faster and more expensive than DRM. Dnamic RM (DRM) Each cell stores bit with a capacitor and transistor. Value must be refreshed ever 1-1 ms. Sensitive to disturbances. Slower and cheaper than SRM. class1.ppt SRM vs DRM Summar Tran. ccess per bit time Persist? Sensitive? Cost pplications SRM 6 1X Yes No 1x cache memories DRM 1 1X No Yes 1X Main memories, frame buffers Conventional DRM Organization d x w DRM: dw total organized as d supercells of size w (to CPU) addr 8 data 16 x 8 DRM chip 1 rows 3 cols 1 3 supercell (,1) internal row buffer Page 1

2 Reading DRM Supercell (,1) Step 1(a): Row access strobe (RS) selects row Step. 1(b): Row copied from DRM arra to row buffer. RS = addr 8 data 16 x 8 DRM chip 1 rows 3 cols 1 3 Reading DRM Supercell (,1) Step (a): Column access strobe (CS) selects column 1. Step (b): Supercell (,1) copied from buffer to data lines, and eventuall back to the CPU. To CPU supercell (,1) CS = 1 addr 8 data 16 x 8 DRM chip 1 rows 3 cols 1 3 internal row buffer supercell (,1) internal row buffer Memor Modules addr (row = i, col = j) DRM DRM bit doubleword at address 64-bit doubleword : supercell (i,j) 64 MB module consisting of eight 8Mx8 DRMs Memor Enhanced DRMs ll enhanced DRMs are built around the conventional DRM core. Fast page mode DRM (FPM DRM) ccess contents of row with [RS, CS, CS, CS, CS] instead of [(RS,CS), (RS,CS), (RS,CS), (RS,CS)]. Extended data out DRM (EDO DRM) Enhanced FPM DRM with more closel spaced CS signals. Snchronous DRM (SDRM) Driven with rising clock edge instead of asnchronous control signals. Double data-rate snchronous DRM (DDR SDRM) Enhancement of SDRM that uses both clock edges as control signals. Video RM (VRM) Like FPM DRM, but output is produced b shifting row buffer Dual ported (allows concurrent reads and writes) Page

3 Nonvolatile Memories DRM and SRM are volatile memories Lose information if powered off. Nonvolatile memories retain value even if powered off. Generic name is read-onl (ROM). Misleading because some ROMs can be read and modified. Tpes of ROMs Programmable ROM (PROM) Eraseable programmable ROM (EPROM) Electricall eraseable PROM (EEPROM) Flash Firmware Program stored in a ROM Boot time code, BIOS (basic inputouput sstem) graphics cards, s. Tpical Bus Structure Connecting CPU and Memor bus is a collection of parallel wires that carr address, data, and control signals. Buses are tpicall shared b multiple devices. CPU chip sstem bus IO bridge bus Memor Read Transaction (1) CPU places address on the bus. Memor Read Transaction () Main reads from the bus, retrieves word x, and places it on the bus. Load operation: movl, Load operation: movl, x x x Page 3

4 Memor Read Transaction (3) CPU reads word x from the bus and copies it into register. Memor Write Transaction (1) CPU places address on bus. Main reads it and waits for the corresponding data word to arrive. Load operation: movl, Store operation: movl, x x Memor Write Transaction () CPU places data word on the bus. Memor Write Transaction (3) Main reads data word from the bus and stores it at address. Store operation: movl, Store operation: movl, Page 4

5 Disk Geometr Disks consist of platters, each with two surfaces. Each surface consists of concentric rings called tracks. Each track consists of sectors separated b gaps. tracks surface track k gaps Disk Geometr (Muliple( Muliple-Platter View) ligned tracks form a clinder. surface surface 1 surface surface 3 surface 4 surface 5 clinder k platter platter 1 platter sectors Disk Capacit Capacit: maximum number of that can be stored. Vendors express capacit in units of gigabtes (GB), where 1 GB = 1^9. Capacit is determined b these technolog factors: Recording densit (in): number of that can be squeezed into a 1 inch segment of a track. Track densit (tracksin): number of tracks that can be squeezed into a 1 inch radial segment. real densit (in): product of recording and track densit. Computing Disk Capacit Capacit = (# btessector) x (avg. # sectorstrack) x (# trackssurface) x (# surfacesplatter) x (# platters) Example: 51 btessector 3 sectorstrack (on average), trackssurface surfacesplatter 5 platters Capacit = 51 x 3 x x x 5 = 3,7,, = 3.7 GB Page 5

6 Disk Operation (Single-Platter View) Disk Operation (Multi-Platter View) The surface spins at a fixed rotational rate The readwrite head is attached to the end of the arm and flies over the surface on a thin cushion of air. readwrite heads move in unison from clinder to clinder arm B moving radiall, the arm can position the readwrite head over an track. Disk ccess Time verage time to access some target sector approximated b : Taccess = Tavg seek + Tavg rotation + Tavg transfer Seek time (Tavg seek) Time to position heads over clinder containing target sector. Tpical Tavg seek = 9 ms Rotational latenc (Tavg rotation) Time waiting for first bit of target sector to pass under rw head. Tavg rotation = 1 x 1RPMs x 6 sec1 min Transfer time (Tavg transfer) Time to read the in the target sector. Tavg transfer = 1RPM x 1(avg # sectorstrack) x 6 secs1 min. Disk ccess Time Example Given: Rotational rate = 7, RPM verage seek time = 9 ms. vg # sectorstrack = 4. Derived: Tavg rotation = 1 x (6 secs7 RPM) x 1 mssec = 4 ms. Tavg transfer = 67 RPM x 14 secstrack x 1 mssec =. ms Taccess = 9 ms + 4 ms +. ms Important points: ccess time dominated b seek time and rotational latenc. First bit in a sector is the most expensive, the rest are free. SRM access time is about 4 nsdoubleword, DRM about 6 ns Disk is about 4, times slower than SRM,,5 times slower then DRM. Page 6

7 Logical Disk Blocks Modern s present a simpler abstract view of the complex sector geometr: The set of available sectors is modeled as a sequence of b-sized logical blocks (, 1,,...) Mapping between logical blocks and actual (phsical) sectors Maintained b hardwarefirmware device called. Converts requests for logical blocks into (surface,track,sector) triples. llows to set aside spare clinders for each zone. ccounts for the difference in formatted capacit and maximum capacit. CPU chip USB mousekeboard graphics adapter monitor IO Bus sstem bus IO bridge IO bus bus Expansion slots for other devices such as network adapters. CPU chip Reading a Disk Sector (1) CPU initiates a read b writing a command, logical block number, and destination address to a port (address) associated with. CPU chip Reading a Disk Sector () Disk reads the sector and performs a direct access (DM) transfer into. IO bus IO bus USB graphics adapter USB graphics adapter mousekeboard monitor mousekeboard monitor Page 7

8 CPU chip Reading a Disk Sector (3) USB mousekeboard graphics adapter monitor When the DM transfer completes, the notifies the CPU with an interrupt (i.e., asserts a special interrupt pin on the CPU) IO bus ns The CPU-Memor Gap The increasing gap between DRM,, and CPU speeds. 1,, 1,, 1,, 1, 1, 1, ear Disk seek time DRM access time SRM access time CPU ccle time Page 8