Features n Measures Up to 12 Li-Ion Ces in Series (6V Max) n Stackabe Architecture Enabes Monitoring High Votage Battery Stacks n Individuay Addressabe with 4-Bit Address n.25% Maximum Tota Measurement Error n 13ms to Measure A Ces in a System n Ce Baancing: On-Chip Passive Ce Baancing Switches Provision for Off-Chip Passive Baancing n Two Thermistor Inputs Pus Onboard Temperature Sensor n 1MHz Seria Interface with Packet Error Checking n High EMI Immunity n Deta-Sigma Converter With Buit-In Noise Fiter n Open-Wire Connection Faut Detection n Low Power Modes n 44-Lead SSOP Package Appications n Eectric and Hybrid Eectric Vehices n High Power Portabe Equipment n Backup Battery Systems n High Votage Data Acquisition Systems Mutice Addressabe Battery Stack Monitor Description The LTC 682-2 is a compete battery monitoring IC that incudes a 12-bit ADC, a precision votage reference, a high votage input mutipexer and a seria interface. Each can measure 12 series connected battery ces, with a tota input votage up to 6V. The votage on a 12 input channes can be measured within 13ms. Many devices can be stacked to measure the votage of each ce in a ong battery string. Each has an individuay addressabe seria interface, aowing up to 16 devices to interface to one contro processor and operate simutaneousy. To minimize power, the offers a measure mode to monitor each ce for overvotage and undervotage conditions. A standby mode is aso provided to reduce suppy current to 5µA. Each ce input has an associated MOSFET switch that can discharge any overcharged ce. The reated LTC682-1 offers a seria interface that aows the seria ports of mutipe LTC682-1 devices to be daisy chained without opto-coupers or isoators. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Typica Appication 12-CELL BATTERY STRING NEXT 12-CELL PACK ABOVE NEXT 12-CELL PACK BELOW V V MUX EXTERNAL TEMP DIE TEMP REGISTERS AND CONTROL 12-BIT ADC VOLTAGE REFERENCE 6822 TA1a SERIAL DATA 4-BIT ADDRESS MEASUREMENT ERROR (%).3.25.2.15.1.5.5.1.15.2.25.3 5 Measurement Error Over Extended Temperature 7 REPRESENTATIVE UNITS V S = 43.2V CELL VOLTAGE 3.6V 25 25 5 75 1 TEMPERATURE ( C) 6822 TA1b 125 1k NTC 1k
Absoute Maximum Ratings (Note 1) Tota Suppy Votage (V to V )...6V Input Votage (Reative to V ) C1....3V to 9V C12...V.6V to V.3V Cn (Note 5)....3V to Min (9 n, 6V) Sn (Note 5)....3V to Min (9 n, 6V) A Other Pins....3V to 7V Votage Between Inputs Cn to Cn 1....3V to 9V Sn to Cn 1....3V to 9V C12 to C8....3V to 25V C8 to C4....3V to 25V C4 to V....3V to 25V Operating Temperature Range... 4 C to 85 C Specified Temperature Range... 4 C to 85 C Junction Temperature... 15 C Storage Temperature Range... 65 C to 15 C *n = 1 to 12 Pin Configuration TOP VIEW V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 17 18 19 2 21 22 44 43 42 41 4 39 38 37 36 35 34 33 32 31 3 29 28 27 26 25 24 23 G PACKAGE 44-LEAD PLASTIC SSOP T JMAX = 15 C, θ JA = 7 C/W CSBI SDO SDI SCKI A3 A2 A1 A GPIO2 GPIO1 WDTB MMB TOS V REG V REF V TEMP2 V TEMP1 NC V S1 C1 S2 order information LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC682IG-2#PBF LTC682IG-2#TRPBF LTC682G-2 44-Lead Pastic SSOP 4 C to 85 C Consut LTC Marketing for parts specified with wider operating temperature ranges. Consut LTC Marketing for information on non-standard ead based finish parts. For more information on ead free part marking, go to: http://www.inear.com/eadfree/ For more information on tape and ree specifications, go to: http://www.inear.com/tapeandree/
Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V = 43.2V, V = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Specifications V ACC Measurement Resoution Quantization of the ADC 1.5 mv/bit ADC Offset Votage (Note 2).5.5 mv ADC Gain Error (Note 2).12.22.12.22 % % V ERR Tota Measurement Error (Note 4) V CELL = V V CELL = 2.3V V CELL = 2.3V V CELL = 3.6V V CELL = 3.6V V CELL = 4.2V V CELL = 4.2V V CELL = 4.6V V TEMP = 2.3V V TEMP = 3.6V V TEMP = 4.2V V CELL Ce Votage Range Fu-Scae Votage Range 5 V V CM Common Mode Votage Range Measured 3.7 5 n V Reative to V Range of Inputs Cn for <.25% Gain Error, n = 3 to 11 Range of Input C3 for <1% Gain Error Range of Input C2 for <.25% Gain Error Range of Input C1 for <.25% Gain Error 1.8 1.2 15 1 5 V V V Overvotage (OV) Detection Leve Programmed for 4.2V 4.182 4.2 4.218 V Undervotage (UV) Detection Leve Programmed for 2.3V 2.29 2.3 2.31 V Die Temperature Measurement Error Error in Measurement at 125 C 3 C V REF Reference Pin Votage R LOAD = 1k to V Reference Votage Temperature 8 ppm/ C Coefficient Reference Votage Therma Hysteresis 25 C to 85 C and 25 C to 4 C 1 ppm Reference Votage Long-Term Drift 6 ppm/ khr V REG Reguator Pin Votage 1 < V < 5, No Load I LOAD = 4mA 2.8 5.1 4.3 7.9 5 9.2 5.1 7.9 9.2 3.2 3.15 4.5 4.1.8 ±8 3.65 3.65 5. 4.8 2.8 5.1 4.3 7.9 5 9.2 5.1 7.9 9.2 3.11 3.115 mv mv mv mv mv mv mv mv mv mv mv V V 5.5 V V Reguator Pin Short-Circuit Current Limit 5 8 ma V S Suppy Votage, V Reative to V V ERR Specifications Met Timing Specifications Met I B Input Bias Current In/Out of Pins C1 Through C12 When Measuring Ces When Not Measuring Ces I S Suppy Current, Active Current Into the V Pin When Measuring Votages with the ADC I M Suppy Current, Monitor Mode Average Current Into the V Pin Whie Monitoring for UV and OV Conditions Continuous Monitoring (CDC = 2) Monitor Every 13ms (CDC = 5) Monitor Every 5ms (CDC = 6) Monitor Every 2 Seconds (CDC = 7) I QS Suppy Current, Ide Current Into the V Pin When Ide A Seria Port Pins at Logic 1 1 4 1 37.5 32.5 1 5 5.8 1.1 1.2 8 225 15 1 62.5 82.5 87.5 V V 1 µa na ma ma µa µa µa µa µa µa
Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V = 43.2V, V = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Discharge Switch On-Resistance V CELL > 3V (Note 3) 1 2 Ω Temperature Range 4 85 C Therma Shutdown Temperature 145 C Therma Shutdown Hysteresis 5 C Timing Specifications t CYCLE Measurement Cyce Time Time Required to Measure 11 or 12 Ces Time Required to Measure Up to 1 Ces Time Required to Measure 1 Ce t 1 SDI Vaid to SCKI Rising Setup 1 ns t 2 SDI Vaid to SCKI Rising Hod 25 ns t 3 SCKI Low 4 ns t 4 SCKI High 4 ns t 5 CSBI Puse Width 4 ns t 6 SCKI Rising to CSBI Rising 1 ns t 7 CSBI Faing to SCKI Rising 1 ns t 8 SCKI Faing to SDO Vaid 25 ns Cock Frequency 1 MHz Watchdog Timer Time-Out Period 1 2.5 s Digita I/O Specifications V IH Digita Votage Input High 2 V V IL Digita Votage Input Low.8 V V OL Digita Votage Output Low Sinking 5µA.3 V 11 9.2 1 13 11 1.2 16 13.5 1.5 ms ms ms Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: The ADC specifications are guaranteed by the tota measurement error (V ERR ) specification. Note 3: Due to the contact resistance of the production tester, this specification is tested to reaxed imits. The 2Ω imit is guaranteed by design. Note 4: V CELL refers to the votage appied across the foowing pin combinations: Cn to Cn 1 for n = 2 to 12, C1 to V. V TEMP refers to the votage appied from V TEMP1 or V TEMP2 to V Note 5: These absoute maximum ratings appy provided that the votage between inputs do not exceed their absoute maximum ratings.
Typica Performance Characteristics TOTAL UNADJUSTED ERROR (mv) 1 8 6 4 2 2 4 6 8 1 Ce Measurement Tota Unadjusted Error T A = 4 C T A = 25 C T A = 85 C T A = 125 C.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. CELL VOLTAGE (V) 6822 G9 TOTAL UNADJUSTED ERROR (mv) 1 1 2 3 4 5 6 7 8 Ce Measurement Tota Unadjusted Error vs Input Resistance R S = 1k R S = 2k R S = 5k R S = 1k R S IN SERIES WITH Cn AND Cn 1 NO EXTERNAL CAPACITANCE ON Cn AND Cn 1.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. CELL VOLTAGE (V) 6822 G1 NUMBER OF UNITS 25 2 15 1 5 Measurement Gain Error Hysteresis T A = 85 C TO 25 C 25 2 15 1 5 5 1 15 2 CHANGE IN GAIN ERROR (ppm) 6822 G2 NUMBER OF UNITS 2 18 16 14 12 1 8 6 4 2 Measurement Gain Error Hysteresis T A = 45 C TO 25 C 25 2 15 1 5 5 1 15 2 CHANGE IN GAIN ERROR (ppm) 6822 G21 REJECTION (db) 1 2 3 4 5 6 Ce Measurement Common Mode Rejection V CM(IN) = 5V P-P 72dB REJECTION CORRESPONDS TO LESS THAN 1 BIT AT ADC OUTPUT 7 1 1 1k 1k 1k 1M 1M FREQUENCY (Hz) 6822 G15 REJECTION (db) 1 2 3 4 5 6 ADC Norma Mode Rejection vs Frequency 7 1 1 1k 1k 1k FREQUENCY (Hz) 6822 G14 2. ADC INL 1. ADC DNL 5 Ce Input Bias Current in Standby INL (BITS) 1.5 1..5.5 1. 1.5 DNL (BITS).8.6.4.2.2.4.6.8 C PIN BIAS CURRENT (na) 4 3 2 1 C1 C12 C2 TO C11 2. 1 2 3 4 INPUT (V) 5 6822 G5 1. 1 2 3 4 INPUT (V) 5 6822 G6 1 4 2 2 4 6 8 1 12 TEMPERATURE ( C) 6822 G3
Typica Performance Characteristics C PIN BIAS CURRENT (µa) DIFFERENCE BETWEEN INTERNAL DIE TEMPERATURE MEASUREMENT AND AMBIENT TEMPERATURE ( C) 2.7 2.65 2.6 2.55 2.5 2.45 2.4 Ce Input Bias Current During Conversion CELL INPUT = 3.6V 2.35 4 2 2 4 6 8 1 12 TEMPERATURE ( C) 5 4 3 2 1 1 2 3 4 5 5 Interna Die Temperature Measurement vs Ambient Temperature V S = 43.2V 25 25 5 75 1 AMBIENT TEMPERATURE ( C) 6822 G4 DEVICE IN STANDBY PRIOR TO MAKING DIE MEASUREMENTS TO MINIMIZE SELF HEATING 125 6822 G12 STANDBY SUPPLY CURRENT (µa) TOTAL UNADJUSTED ERROR (mv) 6 5 4 3 2 1 1 5 5 1 15 2 Suppy Current vs Suppy Votage Standby T A = 4 C T A = 25 C T A = 85 C 1 2 3 4 5 SUPPLY VOLTAGE (V) 6 6822 G1 Externa Temperature Measurement Tota Unadjusted Error vs Input T A = 4 C T A = 25 C T A = 85 C T A = 15 C.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. TEMPERATURE INPUT VOLTAGE (V) 6822 G13 SUPPLY CURRENT (ma) V REF (V).9.85.8.75.7.65.6 3.7 3.68 3.66 3.64 3.62 3.6 3.58 Suppy Current vs Suppy Votage in CDC = 2 CDC = 2 (CONTINUOUS CELL CONVERSIONS) T A = 85 C T A = 25 C T A = 4 C 1 2 3 4 5 SUPPLY VOLTAGE (V) V REF Output Votage vs Temperature 5 REPRESENTATIVE UNITS 3.56 5 25 25 5 75 1 TEMPERATURE ( C) 6 6822 G2 125 6822 G22 V REF (V) 3.9 3.8 3.7 3.6 3.5 3.4 V REF Load Reguation T A = 4 C T A = 25 C T A = 85 C 1 1 SOURCING CURRENT (µa) 1 6822 G7 V REF (V) 3.74 3.72 3.7 3.68 3.66 3.64 3.62 3.6 V REF Line Reguation NO EXTERNAL LOAD ON V REF, CDC = 2 (CONTINUOUS CELL CONVERSIONS) T A = 25 C T A = 85 C T A = 4 C 1 2 3 4 5 SUPPLY VOLTAGE (V) 6 6822 G8 V REG (V) V REG Load Reguation 5.4 5.2 5. T A = 85 C 4.8 T A = 25 C 4.6 T A = 4 C 4.4 4.2 4. 1 2 3 4 5 6 7 8 9 1 SUPPLY CURRENT (ma) 6822 G16
Typica Performance Characteristics V REG (V) 5.5 5. 4.5 4. 3.5 3. 5 V REG Line Reguation T A = 25 C T A = 85 C T A = 4 C NO EXTERNAL LOAD ON V REG, CDC = 2 (CONTINUOUS CELL CONVERSIONS) 15 25 35 45 55 SUPPLY VOLTAGE (V) 6822 G17 DISCHARGE RESISTANCE (Ω) 5 45 4 35 3 25 2 15 1 5 Interna Discharge Resistance vs Ce Votage T A = 45 C T A = 25 C T A = 85 C T A = 15 C.5 1. 1.5 2. 2.5 3. 3.5 4. 4.5 5. CELL VOLTAGE (V) 6822 G11 INCREASE IN DIE TEMPERATURE ( C) 5 45 4 35 3 25 2 15 1 5 Die Temperature Increase vs Discharge Current in Interna FET ALL 12 CELLS AT 3.6V V S = 43.2V T A = 25 C 12 CELLS DISCHARGING 6 CELLS DISCHARGING 1 CELL DISCHARGING 1 2 3 4 5 6 7 8 DISCHARGE CURRENT PER CELL (ma) 6822 G18 CONVERSION TIME (ms) Ce Conversion Time 13.2 13.15 13.1 13.5 13. 12.95 12.9 12.85 12.8 4 2 2 4 6 8 1 12 TEMPERATURE ( C) 6822 G19
Pin Functions V (Pin 1): Tie Pin 1 to the most positive potentia in the battery stack. V must be approximatey the same potentia as C12. C12, C11, C1, C9, C8, C7, C6, C5, C4, C3, C2, C1 (Pins 2, 4, 6, 8, 1, 12, 14, 16, 18, 2, 22, 24): C1 through C12 are the inputs for monitoring battery ce votages. Up to 12 ces can be monitored. The owest potentia is tied to the V pin. The next owest potentia is tied to C1 and so forth. See the figures in the Appications Information section for more detais on connecting batteries to the. S12, S11, S1, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25): S1 though S12 pins are used to baance battery ces. If one ce in a series becomes over charged, an S output can be used to discharge the ce. Each S output is an interna N-channe MOSFET for discharging. See the Bock Diagram. The NMOS has a maximum on-resistance of 2Ω. An externa resistor shoud be connected in series with the NMOS to dissipate heat outside of the package. When using the interna MOSFETs to discharge ces, the die temperature shoud be monitored. See Power Dissipation and Therma Shutdown in the Appications Information section. The S pins aso feature an interna 1k pu-up resistor. This aows the S pins to be used to drive the gates of externa P-channe MOSFETs for higher discharge capabiity. V (Pin 26): Connect V to the most negative potentia in the series of ces. NC (Pin 27): Pin 27 is internay connected to V through 1Ω. Pin 27 can be eft unconnected or connect Pin 27 to Pin 26 on the PCB. V TEMP1, V TEMP2 (Pins 28, 29): Temperature Sensor Inputs. The ADC wi measure the votage on V TEMPx with respect to V and store the resut in the TMP register. The ADC measurements are reative to the V REF pin votage. Therefore a simpe thermistor and resistor combination connected to the V REF pin can be used to monitor temperature. The V TEMP inputs can aso be genera purpose ADC inputs. V REF (Pin 3): 3.75V Votage Reference Output. This pin shoud be bypassed with a 1µF capacitor. The V REF pin can drive a 1k resistive oad connected to V. Larger oads shoud be buffered with an LT63 op amp, or simiar device. V REG (Pin 31): Linear Votage Reguator Output. This pin shoud be bypassed with a 1µF capacitor. The V REG is capabe of sourcing up to 4mA to an externa oad. The V REG pin does not sink current. TOS (Pin 32): Top of Stack Input. The TOS pin can be tied to V REG or V for the. The state of the TOS pin aters the operation of the SDO pin in the togge poing mode. See the Seria Port description. MMB (Pin 33): Monitor Mode Input (Active Low). When MMB is ow (same potentia as V ), the goes into monitor mode. See Modes of Operation in the Appications Information section. WDTB (Pin 34): Watchdog Timer Output (Active Low). If there is no activity on the SCKI pin for 2.5 seconds, the WDTB output is asserted. The WDTB pin is an open-drain NMOS output. When asserted it pus the output down to V and resets the configuration register to its defaut state. See Watchdog Timer Circuit in the Appications Information section. GPIO1, GPIO2 (Pins 35, 36): Genera Purpose Input/Output. The operation of these pins depends on the state of the MMB pin. When MMB is high, the pins behave as traditiona GPIOs. By writing a to a GPIO configuration register bit, the open drain output is activated and the pin is pued to V. By writing a ogic 1 to the configuration register bit, the corresponding GPIO pin is high impedance. An externa resistor is needed to pu the pin up to V REG. By reading the configuration register ocations GPIO1 and GPIO2, the state of the pins can be determined. For exampe, if a is written to register bit GPIO1, a is aways read back because the output NMOSFET pus Pin 35 to V. If a 1 is written to register bit GPIO1, the
Pin Functions pin becomes high impedance. Either a 1 or a is read back, depending on the votage present at Pin 35. The GPIOs make it possibe to turn on/off circuitry around the, or read ogic vaues from a circuit around the. When the MMB pin is ow, the GPIO pins and the WDTB pin are treated as inputs that set the number of ces to be monitored. See Monitor Mode in the Appications Information section. A, A1, A2, A3 (Pins 37, 38, 39, 4): Address Inputs. These pins are tied to V REG or V. The state of the address pins (V REG = 1, V = ) determines the address. See Address Commands in the Seria Port subsection of the Appications Information section. SCKI (Pin 41): Seria Cock Input. The SCKI pin interfaces to any ogic gate (TTL eves). See Seria Port in the Appications Information section. SDI (Pin 42): Seria Data Input. The SDI pin interfaces to any ogic gate (TTL eves). See Seria Port in the Appications Information section. SDO (Pin 43): Seria Data Output. The SDO pin is an NMOS open drain output and requires an externa resistor pu-up. See Seria Port in the Appications Information section. CSBI (Pin 44): Chip Seect (Active Low) Input. The CSBI pin interfaces to any ogic gate (TTL eves). See Seria Port in the Appications Information section. Bock Diagram 1 V 2 C12 REGULATOR V REG 31 1k 3 S12 4 C11 WATCHDOG TIMER WDTB 34 1k 21 S3 MUX 22 C2 1k 23 S2 A/D CONVERTER 12 RESULTS REGISTER AND COMMUNICATIONS A3 4 A2 39 A1 38 A 37 CSBI 44 SDO 43 SDI 42 SCKI 41 24 C1 25 S1 1k REFERENCE CONTROL GPIO2 36 GPIO1 35 MMB 33 26 V TOS 32 27 NC 1Ω DIE TEMP EXTERNAL TEMP V TEMP1 V TEMP2 V REF 28 29 3 6822 BD
TIMING Diagram Timing Diagram of the Seria Interface t 1 t 2 t 4 t 3 t 6 t 7 SCKI SDI D3 D2 D1 D D7 D4 D3 t 5 CSBI t 8 SDO D4 D3 D2 D1 D D7 D4 D3 PREVIOUS COMMAND CURRENT COMMAND 6822 TD Operation Theory of operation The is a data acquisition IC capabe of measuring the votage of 12 series connected battery ces. An input mutipexer connects the batteries to a 12-bit deta-sigma anaog to digita converter (ADC). An interna 5ppm votage reference combined with the ADC give the its outstanding measurement accuracy. The inherent benefits of the deta-sigma ADC vs other types of ADCs (e.g. successive approximation) are expained in Advantages of Deta-Sigma ADCs in the Appications Information section. Communication between the and a host processor is handed by a SPI compatibe seria interface. Mutipe s can be connected to a singe seria interface. This is shown in Figure 1. The s are isoated from one another using digita isoators. A unique addressing scheme aows a s to connect to the same seria port of the host processor. Further expanation of the can be found in the Seria Port section of the data sheet. The aso contains circuitry to baance ce votages. Interna MOSFETs can be used to discharge ces. These interna MOSFETs can aso be used to contro externa baancing circuits. Figure 1 iustrates ce baancing by interna discharge. Figure 4 shows the S pin controing an externa baancing circuit. It is important to note that 1 the makes no decisions about turning on/off the interna MOSFETs. This is competey controed by the host processor. The host processor writes vaues to a configuration register inside the to contro the switches. The watchdog timer on the can be used to turn off the discharge switches if communication with the host processor is interrupted. Open-Connection Detection When a ce input (C pin) is open, it affects 2-ce measurements. Figure 2 shows an open connection to C3, in an appication without externa fitering between the C pins and the ces. During norma ADC conversions (that is, using the STCVAD command), the LTC682 wi give near zero readings for B3 and B4 when C3 is open. The zero reading for B3 occurs because during the measurement of B3, the ADC input resistance wi pu C3 to the C2 potentia. Simiary, during the measurement of B4, the ADC input resistance pus C3 to the C4 potentia. Figure 3 shows an open connection at the same point in the ce stack as Figure 2, but this time there is an externa fiter network sti connected to C3. Depending on the vaue of the capacitor remaining on C3, a norma measurement of B3 and B4 may not give near zero readings, since the C3 pin is not truy open. In fact, with a arge externa capacitance on C3, the C3 votage wi be charged midway
Operation IC #3 TO IC #7 V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 IC #2 CSBI SDO SDI SCKI A3 A2 A1 A GPIO2 GPIO1 WDTB MMB TOS V REG V REF V TEMP2 V TEMP1 NC V S1 C1 S2 ADDRESS 1 V2 OE2 V2 V2 V1 OE1 V1 V1 DIGITAL ISOLATOR 3V BATTERY POSITIVE 35V V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 IC #8 CSBI SDO SDI SCKI A3 A2 A1 A GPIO2 GPIO1 WDTB MMB TOS V REG V REF V TEMP2 V TEMP1 NC V S1 C1 S2 ADDRESS 15 V2 OE2 V2 V2 V1 OE1 V1 V1 DIGITAL ISOLATOR 3V V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 IC #1 CSBI SDO SDI SCKI A3 A2 A1 A GPIO2 GPIO1 WDTB MMB TOS V REG V REF V TEMP2 V TEMP1 NC V S1 C1 S2 ADDRESS V2 OE2 V2 V2 V1 OE1 V1 V1 DIGITAL ISOLATOR 3V MISO CS MOSI CLK 3V MPU MODULE IO 6822 F1 Figure 1. 96-Ce Battery Stack, Isoated Interface. In this Diagram the Battery Negative is Isoated from Modue Ground. Opto-Coupers or Digita Isoators Aow Each IC to be Addressed Individuay. This is a Simpified Schematic Showing the Basic Muti-IC Architecture between C2 and C4 after severa cyces of measuring ces B3 and B4. Thus the measurements for B3 and B4 may indicate a vaid ce votage when in fact the exact state of B3 and B4 is unknown. To reiaby detect an open connection, the command STOWAD is provided. With this command, two 1µA current sources are connected to the ADC inputs and turned on during a ce conversions. Referring again to Figure 3, with the STOWAD command, the C3 pin wi be pued down by the 1µA current source during the B3 ce measurement AND during the B4 ce measurement. This wi tend to decrease the B3 measurement resut and increase the B4 measurement resut reative to the norma STCVAD command. The biggest change is observed in the 11
Operation B4 B3 B4 B3 C F4 C F3 C4 C3 C2 C1 MUX V 1µA Figure 2. Open Connection C4 C3 C2 C1 MUX V 1µA Figure 3. Open Connection with RC Fitering 6822 F2 6822 F3 B4 measurement when C3 is open. So, the best method to detect an open wire at input C3 is to ook for an increase in the measurement of the ce connected between inputs C3 and C4 (ce B4). Thus the foowing agorithm can be used to detect an open connection to ce pin Cn: 1. Issue a STCVAD command (ADC convert without 1µA current sources). 2. Issue a RDCV command and store a ce measurements into array CELLA(n). 3. Issue a STOWAD command (ADC convert with 1µA current sources). 4. Issue a RDCV command and store a ce measurements into array CELLB(n). 5. For each vaue of n from 1 to 11: If CELLB(n 1) CELLA(n 1) 2mV, then Cn is open, otherwise it is not open. The 2mV threshod is chosen to provide toerance for errors in the measurement with the 1µA current source connected. Even without an open connection there is aways some difference between a ce measured with and without the 1µA current source because of the IR drop across the finite resistance of the MUX switches. On the other hand, with capacitors arger then.1µf remaining on an otherwise open C pin, the 1µA current source may not be enough to move the open C pin 2mV with a singe STOWAD command. If the STOWAD command is repeated severa times, the arge externa capacitor wi discharge enough to create a 2mV change in ce readings. To detect an open connection with arger then.1µf capacitance sti on the pin, one must repeat step 3 a number of times before proceeding to step 4. The agorithm above determines if the Cn pin is open based on measurements of the n 1 ce. For exampe, in a 12-ce system, the agorithm finds opens on Pins C1 through C11 by ooking at the measurements of ces B2 through B12. Therefore the agorithm can not be used to determine if the topmost C pin is open. Fortunatey, an open wire from the battery to the top C pin usuay means the V pin is aso foating. When this happens, the readings for the top battery ce wi aways be V, indicating a faiure. If the top C pin is open yet V is sti connected, then the best way to detect an open connection to the top C pin is by comparing the sum of a ce measurements using the STCVAD command to an auxiiary measurement of the sum of a the ces, using a method simiar to that shown in Figure 15. A significanty ower resut for the cacuated sum of a 12 ces suggests an open connection to the top C pin, provided it was aready determined that no other C pin is open. 12
Operation Discharging During Ce Measurements The primary ce votage A/D measurement commands (STCVAD and STOWAD) automaticay turn off a ce s discharge switch whie its votage is being measured. The discharge switches for the ce above and the ce beow wi aso be turned off during the measurement. For exampe, discharge switches S4, S5, and S6 wi be disabed whie ce 5 is being measured. In some systems it may be desirabe to aow discharging to continue during ce votage measurements. The ce votage A/D conversion commands STCVDC and STOWDC aow any enabed discharge switches to remain on during ce votage measurements. This feature aows the system to perform a sef test to verify the discharge functionaity and mutipexer operation. A discharge switches are automaticay disabed during OV and UV comparison measurements. A/D CONVERTER Digita Sef Test Two sef-test commands can be used to verify the functionaity of the digita portions of the ADC. The sef tests aso verify the ce votage registers and ce temperature registers. During these sef tests a test signa is appied to the ADC. If the circuitry is working propery the ce votage or ce temperature registers wi contain identica codes. For sef test 1 the registers wi contain x555. For sef test 2, the registers wi contain xaaa. The time required for the sef-test function is the same as required to measure a ce votages or a temperature sensors. Perform the sef-test function with CDC[2:] set to 1 in the configuration register. Using the S Pins as Digita Outputs or GATE Drivers The S outputs incude an interna 1k pu-up resistor. Therefore the S pins wi behave as a digita output when oaded with a high impedance, e.g., the gate of an externa MOSFET. For appications requiring high battery discharge currents, connect a discrete PMOS switch device and suitabe discharge resistor to the ce, and the gate termina to the S output pin, as iustrated in Figure 4. SI2351DS MM3Z12VT1 15Ω 3.3k 1W VISHAY CRCW2512 SERIES 6822 F4 Figure 4. Externa Discharge FET Connection (One Ce Shown) Power Dissipation and Therma Shutdown The MOSFETs connected to the Pins S1 through S12 can be used to discharge battery ces. An externa resistor shoud be used to imit the power dissipated by the MOSFETs. The maximum power dissipation in the MOSFETs is imited by the amount of heat that can be toerated by the. Excessive heat resuts in eevated die temperatures. The eectrica characteristics are guaranteed for die temperatures up to 85 C. Litte or no degradation wi be observed in the measurement accuracy for die temperatures up to 15 C. Damage may occur near 15 C, therefore the recommended maximum die temperature is 125 C. To protect the from damage due to overheating, a therma shutdown circuit is incuded. Overheating of the device can occur when dissipating significant power in the ce discharge switches. The probem is exacerbated when operating with a arge votage between V and V or when the therma conductivity of the system is poor. If the temperature detected on the device goes above approximatey 145 C, the configuration registers wi be reset to defaut states, turning off a discharge switches and disabing A/D conversions. When a therma shutdown has occurred, the THSD bit in the temperature register group wi go high. The bit is ceared by performing a read of the temperature registers (RDTMP command). Since therma shutdown interrupts norma operation, the interna temperature monitor shoud be used to determine when the device temperature is approaching unacceptabe eves. Cn Sn Cn 1 13
Appications Information Using the with Less Than 12 Ces The can typicay be used with as few as 4 ces. The minimum number of ces is governed by the suppy votage requirements of the. The sum of the ce votages must be 1V to guarantee that a eectrica specifications are met. Figure 5 shows an exampe of the when used to monitor 7 ces. The owest C inputs connect to the 7 ces and the upper C inputs connect to V. Other configurations, e.g., 9 ces, woud be configured in the same way: the owest C inputs connected to the battery ces and the unused C inputs connected to V. The unused inputs wi resut in a reading of V for those channes. The ADC can aso be commanded to measure a stack of ces by making 1 or 12 measurements, depending on the state of the CELL1 bit in the contro register. Data from a 1 or 12 measurements must be downoaded when reading the conversion resuts. The ADC can be commanded to measure any individua ce votage. 14 NEXT HIGHER GROUP OF 7 CELLS NEXT LOWER GROUP OF 7 CELLS V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 S1 V 6822 F5 Figure 5. Monitoring 7 Ces with the Using the Genera Purpose Inputs/Outputs (GPIO1, GPIO2) The has two genera purpose digita inputs/outputs. By writing a GPIO configuration register bit to a ogic ow, the open-drain output can be activated. The GPIOs give the user the abiity to turn on/off circuitry around the. One exampe might be a circuit to verify the operation of the system. When a GPIO configuration bit is written to a ogic high, the corresponding GPIO pin may be used as an input. The read back vaue of that bit wi be the ogic eve that appears at the GPIO pin. When the MMB pin is ow, the GPIO pins and the WDTB pin are treated as inputs that set the number of ces to be monitored. See the Monitor Mode section. WATCHDOG Timer Circuit The incudes a watchdog timer circuit. If no activity is detected on the SCKI pin for 2.5 seconds, the WDTB open-drain output is asserted ow. The WDTB pin remains ow unti an edge is detected on the SCKI pin. When the watchdog timer circuit times out, the configuration bits are reset to their defaut (power-up) state. In the power-up state, the S outputs are off. Therefore, the watchdog timer provides a means to turn off ce discharging shoud communications to the MPU be interrupted. The IC is in the minimum power standby mode after a time out. Note that externay puing the WDTB pin ow wi not reset the configuration bits. The watchdog timer operation is disabed when MMB is ow. When reading the configuration register, byte CFG bit 7 wi refect the state of the WDTB pin. Revision Code The temperature register group contains a 3-bit revision code. If software detection of device revision is necessary, then contact the factory for detais. Otherwise, the code can be ignored. In a cases, however, the vaues of a bits must be used when cacuating the packet error code (PEC) CRC byte on data reads.
Appications Information Modes of Operation The has three modes of operation: standby, measure and monitor. Standby mode is a power saving state where a circuits except the seria interface are turned off. In measure mode, the is used to measure ce votages and store the resuts in memory. Measure mode wi aso monitor each ce votage for overvotage (OV) and undervotage (UV) conditions. In monitor mode, the device wi ony monitor ces for UV and OV conditions. A signa is output on the SDO pin to indicate the UV/OV status. The seria interface is disabed. Standby Mode The defauts (powers up) to standby mode. Standby mode is the owest possibe suppy current state. A circuits are turned off except the seria interface and the votage reguator. The can be programmed for standby mode by setting configuration bits CDC[2:] to. If the part is put into standby mode whie ADC measurements are in progress, the measurements wi be interrupted and the ce votage registers wi be in an indeterminate state. To exit standby mode, the CDC bits must be written to a vaue other than. Measure Mode The is in measure mode when the CDC bits are programmed with a vaue from 1 to 7. The IC monitors each ce votage and produces an interrupt signa on the SDO pin indicating a ce votages are within the UV and OV imits. There are two methods for indicating the UV/OV interrupt status: togge poing (using a 1kHz output signa) and eve poing (using a high or ow output signa). The poing methods are described in the Seria Port section. The UV/OV imits are set by the VUV and VOV vaues in the configuration registers. When a ce votage exceeds the UV/OV imits a bit is set in the fag register. The UV and OV fag status for each ce can be determined using the Read Fag Register Group. If fewer than 12 ces are connected to the then it is necessary to mask the unused input channes. The MCxI bits in the configuration registers are used to mask channes. If the CELL1 bit is high, then the inputs for ces 11 and 12 are automaticay masked. The can monitor UV and OV conditions continuousy. Aternativey, the duty cyce of the UV and OV comparisons can be reduced or turned off to ower the overa power consumption. The CDC bits are used to contro the duty cyce. To initiate ce votage measurements whie in measure mode, a Start A/D Conversion and Po Status command must be sent. After the command has been sent, the wi send the A/D converter status using either the togge poing or the eve poing method, as described in the Seria Port section. If the CELL1 bit is high, then ony the bottom 1 ce votages wi be measured, thereby reducing power consumption and measurement time. By defaut the CELL1 bit is ow, enabing measurement of a 12 ce votages. During ce votage measurement commands, UV and OV fag conditions, refected in the fag register group, are aso updated. When the measurements are compete, the part wi go back to monitoring UV and OV conditions at the rate designated by the CDC bits. Monitor Mode The can be used as a simpe monitoring circuit with no seria interface by puing the MMB pin ow. When in this mode, the interrupt status is indicated on the SDO pin using the togge poing mode described in the Seria Port section. Unike seria port poing commands, however, the togging is independent of the state of the CSBI pin. When the MMB pin is ow, a the device configuration vaues are reset to the defaut states shown in Tabe 15 Memory Bit Descriptions. When MMB is hed ow the VUV, VOV, and CDC register vaues are ignored. Instead VUV and VOV use factory-programmed setings. CDC is set to state 5. The number of ces to be monitored is set by the ogic eves on the WDTB and GPIO pins, as shown in Tabe 1. 15
Appications Information Tabe 1. Monitor Mode Ce Seection WDTB GPIO2 GPIO1 CELL INPUTS MONITORED Ces 1 to 5 1 Ces 1 to 6 1 Ces 1 to 7 1 1 Ces 1 to 8 1 Ces 1 to 9 1 1 Ces 1 to 1 1 1 Ces 1 to 11 1 1 1 Ces 1 to 12 If MMB is ow then brought high, a device configuration vaues are reset to the defaut states incuding the VUV, VOV, and CDC configuration bits. Seria Port Overview The has an SPI bus compatibe seria port. Devices can be connected in parae, using digita isoators. Mutipe devices are uniquey identified by a part address determined by the A to A3 pins. Physica Layer On the, four pins comprise the seria interface: CSBI, SCKI, SDI and SDO. The SDO and SDI may be tied together, if desired, to form a singe, bidirectiona port. Four address pins (A to A3) set the part address for address commands. The TOS pin designates the top device (ogic high) for poing commands. A interface pins are votage mode, with votage eves sensed with respect to the V suppy. See Figure 1. Data Link Layer Cock Phase And Poarity: The SPI compatibe interface is configured to operate in a system using CPHA = 1 and CPOL = 1. Consequenty, data on SDI must be stabe during the rising edge of SCKI. Data Transfers: Every byte consists of 8 bits. Bytes are transferred with the most significant bit (MSB) first. On a write, the data vaue on SDI is atched into the device on the rising edge of SCKI (Figure 6). Simiary, on a read, the data vaue output on SDO is vaid during the rising edge of SCKI and transitions on the faing edge of SCKI (Figure 7). CSBI must remain ow for the entire duration of a command sequence, incuding between a command byte and subsequent data. On a write command, data is atched in on the rising edge of CSBI. After a poing command has been entered, the SDO output wi immediatey be driven by the poing state, with the SCKI input ignored (Figure 8). See the Togge Poing and Leve Poing sections. Network Layer Broadcast Commands: A broadcast command is one to which a devices on the bus wi respond, regardess of device address. See the Bus Protocos and Commands sections. CSBI SCKI SDI MSB (CMD) BIT6 (CMD) LSB (CMD) MSB (DATA) LSB (DATA) 6822 F6 Figure 6. Transmission Format (Write) 16
Appications Information CSBI SCKI SDI MSB (CMD) BIT6 (CMD) LSB (CMD) SDO MSB (DATA) LSB (DATA) 6822 F7 Figure 7. Transmission Format (Read) CSBI SCKI SDI MSB (CMD) BIT6 (CMD) LSB (CMD) SDO POLL STATE 6822 F8 Figure 8. Transmission Format (Po) With broadcast commands a devices can be sent commands simutaneousy. This is usefu for A/D conversion and poing commands. It can aso be used with write commands when a parts are being written with the same data. Broadcast read commands shoud not be used in the parae configuration. Address Commands: An address command is one in which ony the addressed device on the bus responds. The first byte of an address command consists of 4 bits with a vaue of 1 and 4 address bits. The second byte is the command byte. See the Bus Protocos and Commands section. PEC Byte: The packet error code (PEC) byte is a CRC vaue cacuated for a of the bits in a register group in the order they are read, using the foowing characteristic poynomia: x 8 x 2 x 1 On a read command, after sending the ast byte of a register group, the device wi shift out the cacuated PEC, MSB first. Togge Poing: Togge poing aows a robust determination both of device states and of the integrity of the connections between the devices in a stack. Togge poing 17
Appications Information is enabed when the LVLPL bit is ow. After entering a poing command, the data out ine wi be driven by the save devices based on their status. When poing for the A/D converter status, data out wi be ow when any device is busy performing an A/D conversion and wi togge at 1kHz when no device is busy. Simiary, when poing for interrupt status, the output wi be ow when any device has an interrupt condition and wi togge at 1kHz when none has an interrupt condition. Togge Poing Address Poing: The addressed device drives the SDO ine based on its state aone ow for busy/in interrupt, togging at 1kHz for not busy/not in interrupt. Togge Poing Parae Broadcast Poing: No part address is sent, so a devices respond simutaneousy. If a device is busy/in interrupt, it wi pu SDO ow. If a device is not busy/not in interrupt, then it wi reease the SDO ine (TOS = ) or attempt to togge the SDO ine at 1kHz (TOS =1). The master controer pus CSBI high to exit poing. Leve poing: Leve poing is enabed when the LVLPL bit is high. After entering a poing command, the data out ine wi be driven by the save devices based on their status. When poing for the A/D converter status, data out wi be ow when any device is busy performing an A/D conversion and wi be high when no device is busy. Simiary, when poing for interrupt status, the output wi be ow when any device has an interrupt condition and wi be high when none has an interrupt condition. Leve poing Address Poing: The addressed device drives the SDO ine based on its state aone pued ow for busy/in interrupt, reeased for not busy/not in interrupt. Leve poing Parae Broadcast Poing: No part address is sent, so a devices respond simutaneousy. If a device is busy/in interrupt, it wi pu SDO ow. If a device is not busy/not in interrupt, then it wi reease the SDO ine. If any device is busy or in interrupt the SDO signa wi be ow. If a devices are not busy/not in interrupt, the SDO signa wi be high. The master controer pus CSBI high to exit poing. Poing Methods: For A/D conversions, three methods can be used to determine A/D competion. First, a controer can start an A/D conversion and wait for the specified conversion time to pass before reading the resuts. The second method is to hod CSBI ow after an A/D start command has been sent. The A/D conversion status wi be output on SDO. A probem with the second method is that the controer is not free to do other seria communication whie waiting for A/D conversions to compete. The third method overcomes this imitation. The controer can send an A/D start command, perform other tasks, and then send a Po A/D Converter Status (PLADC) command to determine the status of the A/D conversions. For OV/UV interrupt status, the po interrupt status (PLINT) command can be used to quicky determine whether any ce in a stack is in an overvotage or undervotage condition. Bus Protocos There are 6 different protoco formats, depicted in Tabe 3 through Tabe 8. Tabe 2 is the key for reading the protoco diagrams. 18
Appications Information Tabe 2. Protoco Key PEC Packet error code (CRC-8) Master-to-save N Number of bits Save-to-master Continuation of protoco Compete byte of data Tabe 3. Broadcast Po Command 8 Command Po Data Tabe 4. Broadcast Read 8 8 8 8 Command Data Byte Low Data Byte High PEC Tabe 5. Broadcast Write 8 8 8 Command Data Byte Low Data Byte High Tabe 6. Address Po Command 4 4 8 1 Address Command Po Data Tabe 7. Address Read 4 4 8 8 8 8 1 Address Command Data Byte Low Data Byte High PEC Tabe 8. Address Write 4 4 8 8 8 1 Address Command Data Byte Low Data Byte High 19
Appications Information Commands Tabe 9. Command Codes Write Configuration Register Group WRCFG x1 Read Configuration Register Group RDCFG x2 Read Ce Votage Register Group RDCV x4 Read Fag Register Group RDFLG x6 Read Temperature Register Group RDTMP x8 Start Ce Votage A/D Conversions and Po Status STCVAD x1 (a ce votage inputs) x11 (ce 1 ony) x12 (ce 2 ony) x1a (ce 1 ony) x1b (ce 11 ony, if CELL1 bit=) x1c (ce 12 ony, if CELL1 bit=) x1d (unused) x1e (ce sef test 1; a CV=x555) x1f (ce sef test 2; a CV=xAAA) Start Open-Wire A/D Conversions and Po Status STOWAD x2 (a ce votage inputs) x21 (ce 1 ony) x22 (ce 2 ony) x2a (ce 1 ony) x2b (ce 11 ony, if CELL1 bit=) x2c (ce 12 ony, if CELL1 bit=) x2d (unused) x2e (ce sef test 1; a CV=x555) x2f (ce sef test 2; a CV=xAAA) Start Temperature A/D Conversions and Po Status STTMPAD x3 (a temperature inputs) x31 (externa temp 1 ony) x32 (externa temp 2 ony) x33 (interna temp ony) x34 x3d (unused) x3e (temp sef test 1; a TMP=x555) x3f (temp sef test 2; a TMP=xAAA) Po A/D Converter Status PLADC x4 Po Interrupt Status PLINT x5 Start Ce Votage A/D Conversions and Po Status, with Discharge Permitted Start Open-Wire A/D Conversions and Po Status, with Discharge Permitted 2 STCVDC STOWDC x6 (a ce votage inputs) x61 (ce 1 ony) x62 (ce 2 ony) x6a (ce 1 ony) x6b (ce 11 ony, if CELL1 bit=) x6c (ce 12 ony, if CELL1 bit=) x6d (unused) x6e (ce sef test 1; a CV=x555) x6f (ce sef test 2; a CV=xAAA) x7 (a ce votage inputs) x71 (ce 1 ony) x72 (ce 2 ony) x7a (ce 1 ony) x7b (ce 11 ony, if CELL1 bit=) x7c (ce 12 ony, if CELL1 bit=) x7d (unused) x7e (ce sef test 1; a CV=x555) x7f (ce sef test 2; a CV=xAAA)
Appications Information Memory Map Tabe 1 through Tabe 15 show the memory map for the. Tabe 15 gives bit descriptions. Tabe 1. Configuration (CFG) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT CFGR RD/WR WDT GPIO2 GPIO1 LVLPL CELL1 CDC[2] CDC[1] CDC[] CFGR1 RD/WR DCC8 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 CFGR2 RD/WR MC4I MC3I MC2I MC1I DCC12 DCC11 DCC1 DCC9 CFGR3 RD/WR MC12I MC11I MC1I MC9I MC8I MC7I MC6I MC5I CFGR4 RD/WR VUV[7] VUV[6] VUV[5] VUV[4] VUV[3] VUV[2] VUV[1] VUV[] CFGR5 RD/WR VOV[7] VOV[6] VOV[5] VOV[4] VOV[3] VOV[2] VOV[1] VOV[] Tabe 11. Ce Votage (CV) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT CVR RD C1V[7] C1V[6] C1V[5] C1V[4] C1V[3] C1V[2] C1V[1] C1V[] CVR1 RD C2V[3] C2V[2] C2V[1] C2V[] C1V[11] C1V[1] C1V[9] C1V[8] CVR2 RD C2V[11] C2V[1] C2V[9] C2V[8] C2V[7] C2V[6] C2V[5] C2V[4] CVR3 RD C3V[7] C3V[6] C3V[5] C3V[4] C3V[3] C3V[2] C3V[1] C3V[] CVR4 RD C4V[3] C4V[2] C4V[1] C4V[] C3V[11] C3V[1] C3V[9] C3V[8] CVR5 RD C4V[11] C4V[1] C4V[9] C4V[8] C4V[7] C4V[6] C4V[5] C4V[4] CVR6 RD C5V[7] C5V[6] C5V[5] C5V[4] C5V[3] C5V[2] C5V[1] C5V[] CVR7 RD C6V[3] C6V[2] C6V[1] C6V[] C5V[11] C5V[1] C5V[9] C5V[8] CVR8 RD C6V[11] C6V[1] C6V[9] C6V[8] C6V[7] C6V[6] C6V[5] C6V[4] CVR9 RD C7V[7] C7V[6] C7V[5] C7V[4] C7V[3] C7V[2] C7V[1] C7V[] CVR1 RD C8V[3] C8V[2] C8V[1] C8V[] C7V[11] C7V[1] C7V[9] C7V[8] CVR11 RD C8V[11] C8V[1] C8V[9] C8V[8] C8V[7] C8V[6] C8V[5] C8V[4] CVR12 RD C9V[7] C9V[6] C9V[5] C9V[4] C9V[3] C9V[2] C9V[1] C9V[] CVR13 RD C1V[3] C1V[2] C1V[1] C1V[] C9V[11] C9V[1] C9V[9] C9V[8] CVR14 RD C1V[11] C1V[1] C1V[9] C1V[8] C1V[7] C1V[6] C1V[5] C1V[4] CVR15* RD C11V[7] C11V[6] C11V[5] C11V[4] C11V[3] C11V[2] C11V[1] C11V[] CVR16* RD C12V[3] C12V[2] C12V[1] C12V[] C11V[11] C11V[1] C11V[9] C11V[8] CVR17* RD C12V[11] C12V[1] C12V[9] C12V[8] C12V[7] C12V[6] C12V[5] C12V[4] *Registers CVR15, CVR16, and CVR17 can ony be read if the CELL1 bit in register CFGR is ow. 21
Appications Information Tabe 12. Fag (FLG) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT FLGR RD C4OV C4UV C3OV C3UV C2OV C2UV C1OV C1UV FLGR1 RD C8OV C8UV C7OV C7UV C6OV C6UV C5OV C5UV FLGR2 RD C12OV* C12UV* C11OV* C11UV* C1OV C1UV C9OV C9UV *Bits C11UV, C12UV, C11OV, and C12OV are aways ow if the CELL1 bit in register CFGR is high. Tabe 13. Temperature (TMP) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT TMPR RD ETMP1[7] ETMP1[6] ETMP1[5] ETMP1[4] ETMP1[3] ETMP1[2] ETMP1[1] ETMP1[] TMPR1 RD ETMP2[3] ETMP2[2] ETMP2[1] ETMP2[] ETMP1[11] ETMP1[1] ETMP1[9] ETMP1[8] TMPR2 RD ETMP2[11] ETMP2[1] ETMP2[9] ETMP2[8] ETMP2[7] ETMP2[6] ETMP2[5] ETMP2[4] TMPR3 RD ITMP[7] ITMP[6] ITMP[5] ITMP[4] ITMP[3] ITMP[2] ITMP[1] ITMP[] TMPR4 RD REV[2] REV[1] REV[] THSD ITMP[11] ITMP[1] ITMP[9] ITMP[8] Tabe 14. Packet Error Code (PEC) REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT PEC RD PEC[7] PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[] 22
Appications Information Tabe 15. Memory Bit Descriptions NAME DESCRIPTION VALUES CDC Comparator Duty Cyce CDC (defaut) UV/OV COMPARATOR PERIOD N/A (Comparator Off) Standby Mode V REF POWERED DOWN BETWEEN MEASUREMENTS Yes CELL VOLTAGE MEASUREMENT TIME 1 N/A (Comparator Off) No 13ms 2 13ms No 13ms 3 13ms No 13ms 4 5ms No 13ms 5* 13ms Yes 21ms 6 5ms Yes 21ms 7 2ms Yes 21ms *when MMB pin is ow, the CDC vaue is set to 5 CELL1 1-Ce Mode =12-ce mode (defaut); 1=1-ce mode LVLPL Leve Poing Mode =togge poing (defaut); 1=eve poing GPIO1 GPIO1 Pin Contro Write: =GPIO1 pin pu down on; 1=GPIO1 pin pu down off (defaut) Read: =GPIO1 pin at ogic ; 1=GPIO1 pin at ogic 1 GPIO2 GPIO2 Pin Contro Write: =GPIO2 pin pu down on; 1=GPIO2 pin pu down off (defaut) Read: =GPIO2 pin at ogic ; 1=GPIO2 pin at ogic 1 WDT Watchdog Timer Read Ony: =WDTB pin at ogic ; 1=WDTB pin at ogic 1 DCCx Discharge Ce x x=1..12 =turn off shorting switch for ce x (defaut); 1=turn on shorting switch VUV Undervotage Comparison Votage* Comparison votage = VUV * 16 * 1.5mV (defaut VUV=. When MMB pin is ow a factory programmed comparison votage is used) VOV Overvotage Comparison Votage* Comparison votage = VOV * 16 * 1.5mV (defaut VOV=. When MMB pin is ow a factory programmed comparison votage is used) MCxI Mask Ce x Interrupts x=1..12 =enabe interrupts for ce x (defaut) 1=turn off interrupts and cear fags for ce x CxV CxUV CxOV Ce x Votage* Ce x Undervotage Fag Ce x Overvotage Fag x=1..12 x=1..12 x=1..12 12-bit ADC measurement vaue for ce x ce votage for ce x = CxV * 1.5mV reads as xfff whie A/D conversion in progress ce votage compared to VUV comparison votage =ce x not fagged for under votage condition; 1=ce x fagged ce votage compared to VOV comparison votage =ce x not fagged for over votage condition; 1=ce x fagged ETMPx Externa Temperature Measurement* Temperature measurement votage = ETMPx * 1.5mV THSD Therma Shutdown Status = therma shutdown has not occurred; 1=therma shutdown has occurred Status ceared to on read of Therma Register Group REV Revision Code Device revision code ITMP Interna Temperature Measurement* Temperature measurement votage = ITMP * 1.5mV = 8mV * T( K) PEC Packet Error Code CRC vaue for reads *Votage determinations use the decima vaue of the registers, to 495 for 12-bit and to 255 for 8-bit registers. N/A 23
Appications Information Seria Command Exampe for (Addressabe Configuration) Exampes beow use a configuration of three stacked devices: bottom (B), midde (M), and top (T) Write Configuration Registers (Broadcast Command) 1. Pu CSBI ow 2. Send WRCFG command byte 3. Send CFGR byte, then CFGR1, CFGR2, CFGR5 (A devices on bus receive same data) 4. Pu CSBI high; data atched into a devices on rising edge of CSBI Cacuation of seria interface time for sequence above: Number of devices in stack= N Number of bytes in sequence = B = 1 command byte and 6 data bytes Seria port frequency per bit = F Time = (1/F) * B * 8 bits/byte = (1/F) * (16) * 8 Time for 3 ce stacks exampe above, with 1MHz seria port = (1/1) * (16)*8 = 56us Read Ce Votage Registers (Address Command) 1. Pu CSBI ow 2. Send Address byte for bottom device 3. Send RDCV command byte 4. Read CVR byte of bottom device, then CVR1 (B), CVR2 (B), CVR17 (B), and then PEC (B) 5. Pu CSBI high 6. Repeat steps 1-5 for midde device and top device Cacuation of seria interface time for sequence above: Number of devices in stack= N Number of bytes in sequence = B = 1 address, 1 command, 18 register, and 1 PEC byte per device = 21*N Seria port frequency per bit = F Time = (1/F) * B * 8 bits/byte = (1/F) * (21*N) * 8 Time for 3-ce stacks exampe above, with 1MHz seria port = (1/1) * (21*3)*8 = 54us Start Ce Votage A/D Conversions and Po Status (Broadcast Command with Togge Poing) 1. Pu CSBI ow 2. Send STCVAD command byte (a devices in stack start A/D conversions simutaneousy) 3. SDO output of a devices in parae pued ow for approximatey 12ms 4. SDO output togges at 1kHz rate, indicating conversions compete for a devices 5. Pu CSBI high to exit poing 24
Appications Information Po Interrupt Status (Leve Poing) 1. Pu CSBI ow 2. Send Address byte for bottom device 3. Send PLINT command byte 4. SDO output from bottom device pued ow if any device has an interrupt condition; otherwise, SDO high 5. Pu CSBI high to exit poing 6. Repeat steps 1-5 for midde device and top device Faut Protection Overview Care shoud aways be taken when using high energy sources such as batteries. There are numerous ways that systems can be (mis-)configured that might affect a battery system during its usefu ifespan. Tabe 16 shows the various situations that shoud be considered when panning protection circuitry. The first five scenarios are to be anticipated during production and appropriate protection is incuded within the device itsef. Tabe 16. Faiure Mechanism Effect Anaysis SCENARIO EFFECT DESIGN MITIGATION Ce input open circuit (random) Power-up sequence at IC inputs Camp diodes at each pin to V and V (within IC) provide aternate power path. Ce input open circuit (random) Differentia input votage overstress Zener diodes across each ce votage input pair (within IC) imits stress. Top ce input connection oss (V ) Power wi come from highest connected ce input or via data port faut current Camp diodes at each pin to V and V (within IC) provide aternate power path. Bottom ce input connection oss (V ) Disconnection of a harness between a group of battery ces and the IC (in a system of stacked groups) Data ink disconnection between and the master. Ce-pack integrity, break between stacked units Ce-pack integrity, break within stacked unit Ce-pack integrity, break within stacked unit Power wi come from owest connected ce input or via data port faut current Loss of suppy connection to the IC Loss of seria communication (no stress to ICs). No effect during charge or discharge Ce input reverse overstress during discharge Ce input positive overstress during charge Camp diodes at each pin to V and V (within IC) provide aternate power path. Camp diodes at each pin to V and V (within IC) provide an aternate power path if there are other devices (which can suppy power) connected to the. The device wi enter standby mode within 2 seconds of disconnect. Discharge switches are disabed in standby mode. Use digita isoators to isoate the seria port from other seria ports. Add parae Schottky diodes across each ce for oad-path redundancy. Diode and connections must hande fu operating current of stack, wi imit stress on IC Add SCR across each ce for charge-path redundancy. SCR and connections must hande fu charging current of stack, wi imit stress on IC by seection of trigger Zener 25
Appications Information Interna Protection Diodes Each pin of the has protection diodes to hep prevent damage to the interna device structures caused by externa appication of votages beyond the suppy rais as shown in Figure 9. The diodes shown are conventiona siicon diodes with a forward breakdown votage of.5v. The unabeed Zener diode structures have a reverse-breakdown characteristic which initiay breaks down at 12V then snaps back to a 7V camping potentia. The Zener diodes abeed Z CLAMP are higher votage devices with an initia reverse breakdown V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 Z CLAMP Z CLAMP A3 A2 A1 A CSBI SDO of 3V snapping back to 25V. The forward votage drop of a Zeners is.5v. Refer to this diagram in the event of unpredictabe votage camping or current fow. Limiting the current fow at any pin to ±1mA wi prevent damage to the IC. Ce-Votage Fitering The empoys a samping system to perform its anaog-to-digita conversions and provides a conversion resut that is essentiay an average over the.5ms conversion window, provided there isn t noise aiasing with respect to the deta-sigma moduator rate of 512kHz. This indicates that a owpass fiter with usefu attenuation at 5kHz may be beneficia. Since the deta-sigma integration bandwidth is about 1kHz, the fiter corner need not be ower than this to assure accurate conversions. Series resistors of 1Ω may be inserted in the input paths without introducing meaningfu measurement error, provided ony externa discharge switch FETs are being used. Shunt capacitors may be added from the ce inputs to V, creating RC fitering as shown in Figure 1. Note that this fitering is not compatibe with use of the interna discharge switches to carry current since this woud induce setting errors at the time of conversion as any activated switches temporariy open to provide Kevin mode ce sensing. As a discharge switch opens, ce wiring resistance wi aso form a sma votage step (recovery of the sma IR drop), so keeping the frequency cutoff of the fiter reativey high wi aow adequate setting prior to the actua conversion. A guard time of about 6µs is provided in the ADC timing, so a 16kHz LP is optima and offers about 3dB of noise rejection. S4 SDI C3 S3 C2 Z CLAMP SCKI V MODE GPIO2 1Ω 1nF Cn 6.2V S2 GPIO1 Sn C1 S1 WDTB MMB 1Ω 1nF Cn 1 6821 F1 V Figure 9. Interna Protection Diodes TOS 6822 F9 Figure 1. Adding RC Fitering to the Ce Inputs (One Ce Connection Shown) 26
Appications Information No resistor shoud be paced in series with the V pin. Because the suppy current fows from the V pin, any resistance on this pin coud generate a significant conversion error for CELL1. Reading Externa temperature probes Using Dedicated Inputs The incudes two channes of ADC input, V TEMP1 and V TEMP2, that are intended to monitor thermistors (tempco about 4%/ C generay) or diodes ( 2.2mV/ C typica) ocated within the ce array. Sensors can be powered directy from V REF as shown in Figure 11 (up to 6µA tota). For sensors that require higher drive currents, a buffer op amp may be used as shown in Figure 12. Power for the sensor is actuay sourced indirecty from the V REG pin in this case. Probe oads up to about 1mA maximum are supported in this configuration. Since V REF is shutdown during the ide and shutdown modes, the thermistor drive is aso shut off and thus power dissipation minimized. Since V REG remains aways on, the buffer op amp (LT6 shown) is seected for its utraow power consumption (1µA). Expanding Probe Count The provides genera purpose I/O pins, GPIO1 and GPIO2, that may be used to contro mutipexing of severa temperature probes. Using just one of the GPIO pins, the sensor count can doube to four as shown in Figure 13. Using both GPIO pins, up to eight sensor inputs can be supported. GPIO1 1k 1k SN74LVC1G3157 OR SIMILAR DEVICE V REG V REF V TEMP2 V TEMP1 NC V 1µF 1µF 1k 1k NTC 1k 1k NTC V REG V REF V TEMP2 V TEMP1 NC V 1k 1µF 1k NTC 1k NTC 1k NTC 1k NTC 6822 F13 Figure 11. Driving Thermistors Directy from V REF V REG V REF V TEMP2 V TEMP1 NC V LT6 6822 F11 1k 1k NTC 6822 F12 Figure 12. Buffering V REF for Higher Current Sensors 1k 1k NTC Figure 13. Expanding Sensor Count with Mutipexing Using Diodes to Monitor Temperatures in Mutipe Locations Another method of mutipe sensor support is possibe without the use of any GPIO pins. If the sensors are PN diodes and severa used in parae, then the hottest diode wi produce the owest forward votage and effectivey estabish the input signa to the V TEMP input(s). The hottest diode wi therefore dominate the readout from the V TEMP inputs that the diodes are connected to. In this scenario, the specific ocation or distribution of heat is not known, but such information may not be important in practice. Figure 14 shows the basic concept. In any of the sensor configurations shown, a fu-scae cod readout woud be an indication of a faied-open sensor connection to the. 27
Appications Information V REG V REF V TEMP2 V TEMP1 NC V Adding Caibration and Fu-stack Measurements By adding mutipexing hardware, additiona signas can be digitized by the CELL1 ADC channe. One usefu signa to provide is a high accuracy votage reference, such as from an LT 1461A-4 or LTC6652A-4.96. By periodic readings of this signa, host software can provide correction of the readings to improve the accuracy over that of the interna reference, and/or vaidate ADC operation. Another usefu signa is a measure of the 2k 2k 6822 F14 Figure 14. Using Diode Sensors as Hot-Spot Detectors tota stack potentia. This provides a redundant operationa measurement of the ces in the event of a mafunction in the norma acquisition process, or as a faster means of monitoring the entire stack potentia. Figure 15 shows a means of providing both of these features. A resistor divider is used to provide a ow votage representation of the fu stack potentia (C12 to C votage) with MOSFETs that decoupe the divider current under unneeded conditions. Other MOSFETs, in conjunction with an op amp having a shutdown mode, form a votage seector that aows measurement of the norma ce1 potentia (when GPIO1 is ow) or a buffered MUX signa. When the MUX is active (GPIO1 is high), seection can be made between the reference (4.96V) or the fu-stack votage divider (GPOI2 set ow wi seect the reference). During ide time when the WDTB signa goes ow, the externa circuitry goes into a power-down condition, reducing battery drain to a minimum. When not activey performing measurements, GPIO1 shoud be set ow and GPIO2 shoud be set high to achieve the owest power state for the configuration shown. CELL12 TP61K 2.2M 1M GPIO2 GPIO1 = REF_EN = CELL1 V STACK12 WDTB V REG 1M 1µF 1M 2N72 1M 2N72 1M 9.9k LT1461A-4 DNC DNC DNC V IN SD GND V OUT DNC 4.96V V 2.2µF CELL1 1Ω TP61K C1 TP61K 15Ω 1nF TP61K SD LT1636 V DD CH CH1 SEL TC4W53FU COM INH V EE V SS 6822 F15 1M Figure 15. Providing Measurement of Caibration Reference and Fu-Stack Votage Through CELL1 Port 28
Appications Information Providing High speed opto-isoation of the SPI data port Isoation techniques that are capabe of supporting the 1Mbps data rate of the require more power on the isoated (battery) side than can be furnished by the V REG output of the. To keep battery drain minima, this means that a DC/DC function must be impemented aong with a suitabe data isoation circuit, such as shown in Figure 16. Here an optima Avago 4-channe (3/1 bidirectiona) opto-couper is used, with a simpe isoated suppy generated by an LTC1693-2 configured as a 2kHz osciator. The DC/DC function provides an unreguated ogic votage (~4V) to the opto-couper isoated side, from energy provided by host-furnished 5V. This circuit provides totay gavanic isoation between the batteries and the host processor, with an insuation rating of 56V continuous, 25V transient. The Figure 16 functionaity is incuded in the demo board. PCB LAYOUT CONSIDERATIONS The V REG and V REF pins shoud be bypassed with a 1µF capacitor for best performance. The is capabe of operation with as much as 6V between V and V. Care shoud be taken on the PCB ayout to maintain physica separation of traces at different potentias. The pinout of the was chosen to faciitate this physica separation. Figure 17 shows the DC votage on each pin with respect to V when tweve 3.6V battery ces are connected to the. There is no more then 5.5V between any two adjacent pins. The package body is used to separate the highest votage (43.5V) from the owest votage (V). CSBI SDO SDI 3.57k 3.57k 3.57k 33Ω 1k TP61K 33Ω 1k TP61K 1k 5V_HOST CSBI SDI SCKI SCKI 33Ω TP61K V REG 249Ω 1nF 4.99k SDO GND_HOST ACSL-641 ISOLATED V LOGIC 1µF 47pF 2k BAT54S BAT54S V CC1 IN1 V 1µF 6 1 4 3 PE68386 33nF OUT1 GND1 V CC2 IN2 OUT2 GND2 LTC1693-2 1k 6822 F16 Figure 16. Providing an Isoated High-Speed Data Interface 29
Appications Information 43.2V 43.2V 43.2V 39.6V 39.6V 36V 36V 32.4V 32.4V 28.8V 28.8V 25.2V 25.2V 21.6V 21.6V 18V 18V 14.4V 14.4V 1.8V 1.8V 7.2V V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 CSBI SDO SDI SCKI A3 A2 A1 A GPIO2 GPIO1 WDTB MMB TOS V REG V REF V TEMP2 V TEMP1 NC V S1 C1 S2 6822 F17 V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V 5.5V 3.1V 1.5V 1.5V V V 3.6V 3.6V 7.2V Figure 17. Typica Pin Votages for 12 3.6V Ces Advantages of Deta-Sigma ADCs The empoys a deta-sigma anaog-to-digita converter for votage measurement. The architecture of deta-sigma converters can vary consideraby, but the common characteristic is that the input is samped many times over the course of a conversion and then fitered or averaged to produce the digita output code. In contrast, a SAR converter takes a singe snapshot of the input votage and then performs the conversion on this singe sampe. For measurements in a noisy environment, a deta-sigma converter provides distinct advantages over a SAR converter. Whie SAR converters can have high sampe rates, the fupower bandwidth of a SAR converter is often greater than 1MHz, which means the converter is sensitive to noise out to this frequency. And many SAR converters have much higher bandwidths up to 5MHz and beyond. It is possibe to fiter the input, but if the converter is mutipexed to measure severa input channes a separate fiter wi be required for each channe. A ow frequency fiter cannot reside between a mutipexer and an ADC and achieve a high scan rate across mutipe channes. Another consequence of fitering a SAR ADC is that any noise reduction gained by fitering the input cances the benefit of having a high sampe rate in the first pace, since the fiter wi take many conversion cyces to sette. For a given sampe rate, a deta-sigma converter can achieve exceent noise rejection whie setting competey in a singe conversion something that a fitered SAR converter cannot do. Noise rejection is particuary important in high votage switching controers, where switching noise wi invariaby be present in the measured votage. Other advantages of deta sigma converters are that they are inherenty monotonic, meaning they have no missing codes, and they have exceent DC specifications. 3
Appications Information Converter Detais The s ADC has a second-order deta-sigma moduator foowed by a Sinc2, finite impuse response (FIR) digita fiter. The front-end sampe rate is 512ksps, which greaty reduces input fitering requirements. A simpe 16kHz, 1-poe fiter composed of a 1Ω resistor and a.1μf capacitor at each input wi provide adequate fitering for most appications. These component vaues wi not degrade the DC accuracy of the ADC. Each conversion consists of two phases an autozero phase and a measurement phase. The ADC is autozeroed at each conversion, greaty improving CMRR. The second haf of the conversion is the actua measurement. Noise Rejection Figure 18 shows the frequency response of the ADC. The ro-off foows a Sinc2 response, with the first notch at 4kHz. Aso shown is the response of a 1-poe, 85Hz fiter (187μs time constant) which has the same integrated response to wideband noise as the s ADC, which is about 135Hz. This means that if wideband noise is appied to the input, the increase in noise seen at the digita output wi be the same as an ADC with a wide bandwidth (such as a SAR) preceded by a perfect 135Hz brickwa owpass fiter. Thus if an anaog fiter is paced in front of a SAR converter to achieve the same noise rejection as the ADC, the SAR wi have a sower response to input signas. For exampe, a step input appied to the input of the 85Hz fiter wi take 1.55ms to sette to 12 bits of precision, whie the ADC settes in a singe 1ms conversion cyce. This aso means that very high sampe rates do not provide any additiona information because the anaog fiter imits the frequency response. Whie higher order active fiters may provide some improvement, their compexity makes them impractica for high-channe count measurements as a singe fiter woud be required for each input. Aso note that the Sinc2 response has a 2nd order ro-off enveope, providing an additiona benefit over a singe-poe anaog fiter. 1 FILTER GAIN (db) 1 2 3 4 5 6 1 1 1k 1k FREQUENCY (Hz) 1k 6822 F18 Figure 18. Noise Fitering of the ADC 31
Package Description G Package 44-Lead Pastic SSOP (5.3mm) (Reference LTC DWG # 5-8-1754 Rev Ø) 1.25 ±.12 12.5 13.1* (.492.516) 44 43 42 41 4 39 38 37 36 35 34 33 32 31 3 29 28 27 26 25 24 23 7.8 8.2 5.3 5.7 7.4 8.2 (.291.323).25 ±.5 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED.5 BSC 1 2 3 4 5 6 7 8 9 1 11 12 13 14 15 16 17 18 19 2 21 22 5. 5.6* (.197.221) 1.65 1.85 (.65.73) 2. (.79) MAX PARTING LINE.1.25 (.4.1).55.95** (.22.37) 1.25 (.492) REF 8 NOTE: 1.DRAWING IS NOT A JEDEC OUTLINE 2. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 3. DIMENSIONS ARE IN (INCHES) 4. DRAWING NOT TO SCALE 5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN.8mm AT SEATING PLANE.5 (.1968) BSC.2.3 (.8.12) TYP * DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED.15mm PER SIDE ** LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS DO NOT EXCEED.13mm PER SIDE.5 (.2) MIN G44 SSOP 67 REV Ø SEATING PLANE 32
Revision History REV DATE DESCRIPTION PAGE NUMBER A 1/1 Additions to Absoute Maximum Ratings Changes to Eectrica Characteristics Change to Graph G1 Text Changes to Pin Functions Repaced Open-Connection Detection Section Edits to Figures 1, 9 Text Changes to Operation Section Text Changes to Appications Information Section Edits to Tabes 4, 5, 9, 1, 15, 16 2 3, 4 5 8, 9 1, 11, 12 11, 26 13 14, 25, 27 19, 2, 21, 23 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 33
Typica Appication Stacked Daisy-Chain SPI Bus for V BATT IC #3 V REG 1M 1.8k 2.2k 2.2k 2.2k WDT SDI SCKI CSBI NDC72N ALL NPN: CMPT899 ALL PNP: CMPT8599 ALL PN: RS7J ALL SCHOTTKY: CMD5H2-3 SDO V IC #2 V REG 1Ω 2.2k 2.2k 2.2k SDI SCKI CSBI SDO V IC #1 V REG 1Ω 2.2k 2.2k 2.2k SDI SCKI CSBI SDO V R12 2.2k 6822 TA2 CS CK DI DO HOST µp 5kbps MAX DATA RATE Reated Parts PART NUMBER DESCRIPTION COMMENTS LTC682-1 Mutice Battery Stack Monitor with Daisy Chained Seria Interface Functionaity equivaent to, Aows for Mutipe Devices to be Daisy Chained 34 LT 11 REV A PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA 9535-7417 (48) 432-19 FAX: (48) 434-57 www.inear.com LINEAR TECHNOLOGY CORPORATION 29