LTC6803-1/LTC Multicell Battery Stack Monitor APPLICATIONS TYPICAL APPLICATION

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1 FEATURES n Measures Up to 12 Battery Ces in Series n Stackabe Architecture n Supports Mutipe Battery Chemistries and Supercapacitors n Seria Interface Daisy Chains to Adjacent Devices n.2% Maximum Tota Measurement Error n Engineered for ISO26262 Compiant Systems n 13ms to Measure A Ces in a System n Passive Ce Baancing: Integrated Ce Baancing MOSFETs Abiity to Drive Externa Baancing MOSFETs n Onboard Temperature Sensor and Thermistor Inputs n 1MHz Seria Interface with Packet Error Checking n Safe with Random Connection of Ces n Buit-In Sef Tests n Deta-Sigma Converter With Buit-In Noise Fiter n Open-Wire Connection Faut Detection n 12µA Standby Mode Suppy Current n High EMI Immunity n 44-Lead SSOP Package APPLICATIONS n Eectric and Hybrid Eectric Vehices n High Power Portabe Equipment n Backup Battery Systems n Eectric Bicyces, Motorcyces, Scooters DESCRIPTION LTC683-1/LTC683-3 Mutice Battery Stack Monitor The LTC 683 is a 2nd generation, compete battery monitoring IC that incudes a 12-bit ADC, a precision votage reference, a high votage input mutipexer and a seria interface. Each LTC683 can measure up to 12 series-connected battery ces or supercapacitors. Using a unique eve shifting seria interface, mutipe LTC683-1/ LTC683-3 devices can be connected in series, without opto-coupers or isoators, aowing for monitoring of every ce in a ong string of series-connected batteries. Each ce input has an associated MOSFET switch for discharging overcharged ces. The LTC683-1 connects the bottom of the stack to internay. It is pin compatibe with the LTC682 1, providing a drop-in upgrade. The LTC683-3 separates the bottom of the stack from, improving ce 1 measurement accuracy. The LTC683 provides a standby mode to reduce suppy current to 12µA. Furthermore, the LTC683 can be powered from an isoated suppy, providing a technique to reduce battery stack current draw to zero. For appications requiring individuay addressabe seria communications, see the LTC683-2/LTC L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. TYPICAL APPLICATION 12-CELL BATTERY NEXT 12-CELL PACK ABOVE NEXT 12-CELL PACK BELOW V 1k NTC MUX EXTERNAL TEMP 1k LTC683-3 DIE TEMP REGISTERS AND CONTROL 12-BIT Σ ADC VOLTAGE REFERENCE SERIAL DATA TO LTC683-3 ABOVE SERIAL DATA TO LTC683-3 BELOW V ISOLATED DC/DC CONVERTER 12V SUPPLY CURRENT Suppy Current vs Modes of Operation 1mA 1µA 1µA 1µA 1nA 1nA 1nA HW SHUTDOWN STANDBY MEASURE TA1b TA1a 1

2 LTC683-1/LTC683-3 ABSOLUTE MAXIMUM RATINGS Tota Suppy Votage (V to )...7V Input Votage (Reative to ) C....3V to 8V C V to 7V Cn (Note )....3V to Min (8 n, 7V) Sn (Note )....3V to Min (8 n, 7V) CSBO, SCKO, SDOI....3V to 7V A Other Pins....3V to 7V Votage Between Inputs Cn to Cn V to 8V Sn to Cn V to 8V C12 to C8....3V to 2V C8 to C4....3V to 2V C4 to C....3V to 2V (Note 1) Operating Temperature Range LTC683I... 4 C to 8 C LTC683H... 4 C to 12 C Specified Temperature Range LTC683I... 4 C to 8 C LTC683H... 4 C to 12 C Junction Temperature... 1 C Storage Temperature Range... 6 C to 1 C Note: n = 1 to 12 PIN CONFIGURATION LTC683-1 TOP VIEW LTC683-3 TOP VIEW CSBO 1 44 CSBI CSBO 1 44 CSBI SDOI 2 43 SDO SDOI 2 43 SDO SCKO V SDI SCKI SCKO V SDI SCKI C12 4 V MODE C12 4 V MODE S GPIO2 S GPIO2 C GPIO1 C GPIO1 S WDTB S WDTB C NC C TOS S1 1 3 TOS S1 1 3 V REG C V REG C V REF S V REF S V TEMP2 C V TEMP2 C V TEMP1 S8 C7 S V TEMP1 NC S8 C7 S NC C C S1 C S1 S C1 S C1 C S2 C S2 S 2 2 C2 S 2 2 C2 C S3 C S3 S C3 S C3 G PACKAGE 44-LEAD PLASTIC SSOP T JMAX = 1 C, θ JA = 7 C/W G PACKAGE 44-LEAD PLASTIC SSOP T JMAX = 1 C, θ JA = 7 C/W 2

3 LTC683-1/LTC683-3 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFICED TEMPERATURE RANGE LTC683IG-1#PBF LTC683IG-1#TRPBF LTC683G-1 44-Lead Pastic SSOP 4 C to 8 C LTC683IG-3#PBF LTC683IG-3#TRPBF LTC683G-3 44-Lead Pastic SSOP 4 C to 8 C LTC683HG-1#PBF LTC683HG-1#TRPBF LTC683G-1 44-Lead Pastic SSOP 4 C to 12 C LTC683HG-3#PBF LTC683HG-3#TRPBF LTC683G-3 44-Lead Pastic SSOP 4 C to 12 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on non-standard ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 2 C. V = 43.2V, = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Specifications V S Suppy Votage, V Reative to V ERR Specification Met Timing Specification Met V LSB Measurement Resoution Quantization of the ADC 1. mv/bit ADC Offset (Note 2).. mv ADC Gain Error (Note 2) % % V ERR Tota Measurement Error (Note4) V CELL =.3V V CELL = 2.3V V CELL = 2.3V V CELL = 3.6V V CELL = 3.6V, LTC683IG V CELL = 3.6V, LTC683HG V CELL = 4.2V V CELL = 4.2V, LTC683IG V CELL = 4.2V, LTC683HG V CELL = V 2.3V < V TEMP < 4.2V, LTC683IG 2.3V < V TEMP < 4.2V, LTC683HG V CELL Ce Votage Range Fu-Scae Votage Range.3 V V CM Common Mode Votage Range Range of Inputs Cn <.2% Gain Error, 1.8 n V Measured Reative to n = 2 to 11, LTC683IG Range of Inputs C, C1 <.2% Gain Error, V LTC683IG Range of Inputs Cn <.% Gain Error, 1.8 n V n = 2 to 11, LTC683HG Range of Inputs C, C1 <.% Gain Error, V LTC683HG Die Temperature Measurement Error Error in Measurement of 12 C C V REF Reference Pin Votage R LOAD = 1k to Reference Votage Temperature 8 ppm/ C Coefficient Reference Votage Therma Hysteresis 2 C to 8 C and 2 C to 4 C 1 ppm Reference Votage Long-Term Drift 6 ppm/ khr ±2. ± V V mv mv mv mv mv mv mv mv mv mv mv mv V V 3

4 LTC683-1/LTC683-3 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 2 C. V = 43.2V, = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V REF2 2nd Reference Votage V V V REG Reguator Pin Votage 1V < V < V, No Load I LOAD = 4mA V V Reguator Pin Short-Circuit Limit 8 ma I B Input Bias Current In/Out of Pins C1 Through C12 When Measuring Ce When Not Measuring Ce I S Suppy Current, Measure Mode (Note 7) Current Into the V Pin When Measuring Continuous Measuring (CDC = 2) Continuous Measuring (CDC = 2) Measure Every 13ms (CDC = ) Measure Every ms (CDC = 6) Measure Every 2 Seconds (CDC = 7) I QS Suppy Current, Standby Current Into V Pin When In Standby, A Seria Port Pin at Logic 1 LTC683IG LTC683HG I CS Suppy Current, Seria I/O Current Into V Pin During Seria Communications, A Seria Port Pins at Logic. V MODE =, This Current is Added to I S or I QS LTC683IG LTC683HG I SD Suppy Current, Hardware Shutdown Current Out of, V C12 = 43.2V, V Foating (Note 8) µa na µa µa µa µa µa µa µa µa ma ma ma.1 1 µa Discharge Switch-On Resistance V CELL > 3V (Note 3) 1 2 Ω I OW Current Used for Open-Wire Detection µa Therma Shutdown Temperature 14 C Therma Shutdown Hysteresis C Votage Mode Timing Specifications t CYCLE Measurement Cycing Time Required to Measure 12 Ces Time Required to Measure 1 Ces Time Required to Measure 3 Temperatures Time Required to Measure 1 Ce or Temperature t 1 SDI Vaid to SCKI Rising Setup 1 ns t 2 SDI Vaid to SCKI Rising Hod 2 ns t 3 SCKI Low 4 ns t 4 SCKI High 4 ns t CSBI Puse Width 4 ns t 6 CSBI Faing to SCKI Rising 1 ns t 7 CSBI Faing to SDO Vaid 1 ns t 8 SCKI Faing to SDO Vaid 2 ns Cock Frequency 1 MHz Watchdog Timer Timeout Period 1 2. Seconds Timing Specifications t PD1 CSBI to CSBO C CSBO = 1pF 6 ns t PD2 SCKI to SCKO C SCKO = 1pF 3 ns t PD3 SDI to SDOI Write Deay C SDOI = 1pF 3 ns t PD4 SDI to SDOI Read Deay C SDO = 1pF 3 ns ms ms ms ms 4

5 LTC683-1/LTC683-3 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 2 C. V = 43.2V, = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Votage Mode Digita I/O V IH Digita Input Votage High Pins SCKI, SDI and CSBI 2 V V IL Digita Input Votage Low Pins SCKI, SDI and CSBI.8 V V OL Digita Output Votage Low Pin SDO, Sinking µa.3 V I IN Digita Input Current V MODE, TOS, SCKI, SDI, CSBI 1 µa Current Mode Digita I/O I IH1 Digita Input Current High Pins CSBI, SCKI, SDI (Write, Pin Sourcing) 3 1 µa I IL1 Digita Input Current Low CSBI, SCKI, SDI (Write, Pin Sourcing) 1 µa I IH2 Digita Input Current High SDOI (Read, Pin Sinking) 1 µa I IL2 Digita Input Current Low SDOI (Read, Pin Sinking) 1 µa I OH1 Digita Output Current High CSBO, SCKO, SDOI (Write, Pin Sinking) 3 1 µa I OL1 Digita Output Current Low CSBO, SCKO, SDOI(Write, Pin Sinking) µa I OH2 Digita Output Current High SDI (Read, Pin Sourcing) µa I OL2 Digita Output Current Low SDI (Read, Pin Sourcing) 3 1 µa Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: The ADC specifications are guaranteed by the Tota Measurement Error (V ERR ) specification. Note 3: Due to the contact resistance of the production tester, this specification is tested to reaxed imits. The 2Ω imit is guaranteed by design. Note 4: V CELL refers to the votage appied across Cn to Cn 1 for n = 1 to 12. V TEMP refers to the votage appied from V TEMP1 or V TEMP2 to. Note : These absoute maximum ratings appy provided that the votage between inputs do not exceed the absoute maximum ratings. Note 6: Suppy current is tested during continuous measuring. The suppy current during periodic measuring (13ms, ms, 2s) is guaranteed by design. Note 7: The CDC =, 6 and 7 suppy currents are not measured. They are guaranteed by the CDC = 2 suppy current measurement. Note 8: Limit is determined by high speed automated test capabiity. TYPICAL PERFORMANCE CHARACTERISTICS TOTAL UNADJUSTED ERROR (mv) Ce Measurement Error vs Ce Input Votage T A = 12 C T A = 8 C T A = 2 C T A = 4 C CELL INPUT VOLTAGE (V). CELL VOLTAGE ERROR (mv) Ce Measurement Error vs Input RC Vaues C = µf C =. C = C = 3.3µF CELL 1, 13ms CELL MEASUREMENT REPETITION V CELL = 3.3V INPUT RESISTANCE (kω) CELL VOLTAGE ERROR (mv) Ce Measurement Error vs Input RC Vaues C = µf C =. C = C = 3.3µF CELLS 2 TO 12, 13ms CELL MEASUREMENT REPETITION V CELL = 3.3V INPUT RESISTANCE (kω) G G G3

6 LTC683-1/LTC683-3 TYPICAL PERFORMANCE CHARACTERISTICS CELL 12 MEASUREMENT ERROR (mv) CELL MEASUREMENT ERROR (mv) Ce 12 Measurement Error vs V T A = 2 C V CELL = 3.3V V V C12 (V) G4 Ce 1 Votage Measurement Error vs Temperature V CELL =.8V V = 9.6V 4 SAMPLES TEMPERATURE ( C) G7 CELL MEASUREMENT ERROR (mv) CELL MEASUREMENT ERROR (mv) Ce Votage Measurement Error vs Common Mode Votage V CELL = 3.6V T A = 2 C CELL2 ERROR vs V C1 CELL3 ERROR vs V C2 CELLn ERROR VS V Cn 1, n = 4 TO COMMON MODE VOLTAGE (V) G Ce 2 Votage Measurement Error vs Temperature V CELL =.8V V = 9.6V 4 SAMPLES TEMPERATURE ( C) G8 CELL VOLTAGE MEASUREMENT ERROR (mv) CELL MEASUREMENT ERROR (mv) Ce Measurement Error vs Ce Votage ALL OTHER CELLS = 3V CELL V IN CELL6 (V) G6 Ce 3 to Ce 12 Votage Measurement Error vs Temperature 1.2 V CELL =.8V V = 9.6V 4 SAMPLES TEMPERATURE ( C) G9 NUMBER OF UNITS Measurement Gain Error Hysteresis T A = 8 C TO 2 C CHANGE IN GAIN ERROR (ppm) G1 NUMBER OF UNITS Measurement Gain Error Hysteresis T A = 4 C TO 2 C CHANGE IN GAIN ERROR (ppm) G11 REJECTION (db) Ce Measurement Common Mode Rejection V CM(IN) = V P-P 72dB REJECTION CORRESPONDS TO LESS THAN 1 BIT AT ADC OUTPUT k 1k 1k 1M 1M FREQUENCY (Hz) G12 6

7 TYPICAL PERFORMANCE CHARACTERISTICS LTC683-1/LTC683-3 ADC Norma Mode Rejection vs Frequency 2. ADC INL 1. ADC DNL REJECTION (db) INL (BITS) DNL (BITS) k 1k 1k FREQUENCY (Hz) G INPUT (V) G INPUT (V) G1 CELL INPUT BIAS CURRENT (na) Ce Input Bias Current During Standby and Hardware Shutdown 4 CELL INPUT = 3.6V C12 C1 C TEMPERATURE ( C) SUPPLY CURRENT (µa) Standby Suppy Current vs Suppy Votage SUPPLY VOLTAGE (V) 12 C 8 C 2 C 4 C 6 SUPPLY CURRENT (µa) Suppy Current vs Suppy Votage During Continuous Conversions CDC = 2 CONTINUOUS CONVERSION SUPPLY VOLTAGE (V) 12 C 8 C 2 C 4 C G G G18 E = (AMBIENT TEMP-INTERNAL DIE TEMP READING) ( C) 1 1 Interna Die Temperature Measurement Error Using an 8mV/ K Scae Factor 1 SAMPLES TOTAL UNADJUSTED ERROR (mv) Externa Temperature Measurement Tota Unadjusted Error vs Input T A = 12 C T A = 8 C T A = 2 C T A = 4 C TEMPERATURE ( C) TEMPERATURE INPUT VOLTAGE (V) G G2 7

8 LTC683-1/LTC683-3 TYPICAL PERFORMANCE CHARACTERISTICS V REF (V) V REF Output Votage vs Temperature 3.8 REPRESENTATIVE UNITS TEMPERATURE ( C) G21 V REF (V) V REF Load Reguation T A = 8 C T A = 4 C 1 1 SOURCING CURRENT (µa) T A = 2 C G22 V REF (V) V REF Line Reguation NO EXTERNAL LOAD ON V REF, CDC = 2 (CONTINUOUS CELL CONVERSIONS) T A = 2 C T A = 8 C T A = 4 C SUPPLY VOLTAGE (V) G23 V REG (V) V REG Load Reguation V = 43.2V T A = 12 C T A = 8 C T A = 2 C T A = 4 C SUPPLY CURRENT (ma) 1 12 V REG (V) V REG Line Reguation CDC = 2 CONTINUOUS CONVERSIONS SUPPLY VOLTAGE (V) T A = 12 C T A = 8 C T A = 2 C T A = 4 C 6 DISCHARGE RESISTANCE (Ω) Interna Discharge Resistance vs Ce Votage T A = 1 C T A = 8 C T A = 2 C T A = 4 C CELL VOLTAGE (V) G G G2 INCREASE IN DIE TEMPERATURE ( C) Die Temperature Increase vs Discharge Current in Interna FET ALL 12 CELLS AT 3.6V V S = 43.2V T A = 2 C 12 CELLS DISCHARGING 6 CELLS DISCHARGING 1 CELL DISCHARGING DISCHARGE CURRENT PER CELL (ma) G27 CONVERSION TIME (ms) Ce Conversion Time TEMPERATURE ( C) G28 8

9 PIN FUNCTIONS To ensure pin compatibiity with the LTC682-1, the LTC683-1 is configured such that the bottom ce input (C) is connected internay to the negative suppy votage ( ). The LTC683-3 offers a unique pinout with an input for the bottom ce (C). This simpe functiona difference offers the possibiity for enhanced ce 1 measurement accuracy, enhanced SPI noise toerance and simpified wiring. More information is provided in the appications section entited Advantages of Kevin Connections for C. CSBO (Pin 1): Chip Seect Output (Active Low). CSBO is a buffered version of the chip seect input, CSBI. CSBO drives the next IC in the daisy chain. See Seria Port in the Appications Information section. SDOI (Pin 2): Seria Data I/O Pin. SDOI transfers data to and from the next IC in the daisy chain. See Seria Port in the Appications Information section. SCKO (Pin 3): Seria Cock Output. SCKO is a buffered version of SCKI. SCKO drives the next IC in the daisy chain. See Seria Port in the Appications Information section. V (Pin 4): Positive Power Suppy. Pin 4 can be tied to the most positive potentia in the battery stack or an isoated power suppy. V must be greater than the most positive potentia in the battery stack under norma operation. With an isoated power suppy, LTC683 can be turned off by simpy shutting down V. C12, C11, C1, C9, C8, C7, C6, C, C4, C3, C2, C1 (Pins, 7, 9, 11, 13, 1, 17, 19, 21, 23, 2, 27): C1 through C12 are the inputs for monitoring battery ce votages. The negative termina of the bottom ce is tied to pin for LTC683-1, pin C for LTC The next owest potentia is tied to C1 and so forth. See the figures in the Appications Information section for more detais on connecting batteries to the LTC683-1 and LTC The LTC683 can monitor a series connection of up to 12 ces. Each ce in a series connection must have a common mode votage that is greater than or equa to the ces beow it. 1mV negative votages are permitted. LTC683-1/LTC683-3 S12, S11, S1, S9, S8, S7, S6, S, S4, S3, S2, S1 (Pins 6, 8, 1, 12, 14, 16, 18, 2, 22, 24, 26, 28): S1 though S12 pins are used to baance battery ces. If one ce in a series becomes overcharged, an S output can be used to discharge the ce. Each S output has an interna N-channe MOSFET for discharging. See the Bock Diagram. The NMOS has a maximum on resistance of 2Ω. An externa resistor shoud be connected in series with the NMOS to dissipate heat outside of the LTC683 package. When using the interna MOSFETs to discharge ces, the die temperature shoud be monitored. See Power Dissipation and Therma Shutdown in the Appications Information section. The S pins aso feature an interna pu-up PMOS. This aows the S pins to be used to drive the gates of externa MOSFETs for higher discharge capabiity. C (Pin 29 on LTC683-3): Negative Termina of the Bottom Battery Ce. C and form Kevin connections to eiminate effect of votage drop at the trace. (Pin 29 on LTC683-1/ Pin 3 on LTC683-3): Connect to the most negative potentia in the series of ces. NC (Pin 3 on LTC683-1/Pin 31 on LTC683-3 ): This pin is not used and is internay connected to through 1Ω. It can be eft unconnected or connected to on the PCB. V TEMP1, V TEMP2 (Pins 31, 32 on LTC683-1/ Pins 32, 33 on LTC683-3 ): Temperature Sensor Inputs. The ADC measures the votage on V TEMPn with respect to and stores the resut in the TMP registers. The ADC measurements are reative to the V REF pin votage. Therefore a simpe thermistor and resistor combination connected to the V REF pin can be used to monitor temperature. The V TEMP inputs can aso be genera purpose ADC inputs. Any votage from V to.12v referenced to can be measured. V REF (Pin 33 on LTC683-1/ Pin 34 on LTC683-3 ): 3.6V Votage Reference Output. This pin shoud be bypassed with a capacitor. The V REF pin can drive a 1k resistive oad connected to. Larger oads shoud be buffered with an LT63 op amp, or simiar device. 9

10 LTC683-1/LTC683-3 PIN FUNCTIONS V REG (Pin 34 on LTC683-1/ Pin 3 on LTC683-3 ): Linear Votage Reguator Output. This pin shoud be bypassed with a capacitor. The V REG pin is capabe of suppying up to 4mA to an externa oad. The V REG pin does not sink current. TOS (Pin 3 on LTC683-1/Pin 36 on LTC683-3): Top of Stack Input. Tie TOS to V REG when the LTC683-1 or LTC683-3 is the top device in a daisy chain. Tie TOS to otherwise. When TOS is tied to V REG, the LTC683-1 or LTC683-3 ignores the SDOI input and SCKO, CSBO are turned off. When TOS is tied to, the LTC683-1 or LTC683-3 expects data to be passed to and from the SDOI pin. NC (Pin 36 on LTC683-1 ): No Connection. WDTB (Pin 37): Watchdog Timer Output (Active Low). If there is no vaid command received for 1 to 2. seconds, the WDTB output is asserted. The WDTB pin is an open-drain NMOS output. When asserted it pus the output down to and resets the configuration register to its defaut state. GPIO1, GPIO2 (Pins 38, 39): Genera Purpose Input/ Output. By writing a to a GPIO configuration register bit, the open-drain output is activated and the pin is pued to. By writing ogic 1 to the configuration register bit, the corresponding GPIO pin is high impedance. An externa resistor is required to pu the pin up to V REG. By reading the configuration register ocations GPIO1 and GPIO2, the state of the pins can be determined. For exampe, if a is written to register bit GPIO1, a is aways read back because the output N-channe MOSFET pus Pin 38 to. If a 1 is written to register bit GPIO1, the pin becomes high impedance. Either a 1 or a is read back, depending on the votage present at Pin 38. The GPIOs makes it possibe to turn on/off circuitry around the LTC683, or read ogic vaues from a circuit around the LTC683. The GPIO pins shoud be connected to if not used. V MODE (Pin 4): Votage Mode Input. When V MODE is tied to V REG, the SCKI, SDI, SDO and CSBI pins are configured as votage inputs and outputs. This means these pins accept standard TTL ogic eves. Connect V MODE to V REG when the LTC683-1 or LTC683-3 is the bottom device in a daisy chain. When V MODE is connected to, the SCKI, SDI and CSBI pins are configured as current inputs and outputs, and SDO is unused. Connect V MODE to when the LTC683-1 or LTC683-3 is being driven by another LTC683-1 or LTC683-3 in a daisy chain. SCKI (Pin 41): Seria Cock Input. The SCKI pin interfaces to any ogic gate (TTL eves) if V MODE is tied to V REG. SCKI must be driven by the SCKO pin of another LTC683-1 or LTC683-3 if V MODE is tied to. See Seria Port in the Appications Information Section. SDI (Pin 42): Seria Data Input. The SDI pin interfaces to any ogic gate (TTL eves) if V MODE is tied to V REG. SDI must be driven by the SDOI pin of another LTC683-1 or LTC683-3 if V MODE is tied to. See Seria Port in the Appications Information section. SDO (Pin 43): Seria Data Output. The SDO pin is an NMOS open-drain output if V MODE is tied to V REG. A pu-up resistor is needed on SDO. SDO is not used if V MODE is tied to. See Seria Port in the Appications Information section. CSBI (Pin 44): Chip Seect (Active Low) Input. The CSBI pin interfaces to any ogic gate (TTL eves) if V MODE is tied to V REG. CSBI must be driven by the CSBO pin of another LTC683-1 or LTC683-3 if V MODE is tied to. See Seria Port in the Appications Information section. 1

11 LTC683-1/LTC683-3 BLOCK DIAGRAMS LTC ND REFERENCE V REF2 4 V REGULATOR V REG 34 C12 6 S12 WATCHDOG TIMER WDTB 37 7 C11 SCKO 3 24 S3 2 C2 26 S2 MUX Σ A/D CONVERTER 12 RESULTS REGISTER AND COMMUNICATIONS SDOI 2 CSBO 1 CSBI 44 SDO 43 SDI C1 28 S1 29 V 3 NC 1Ω DIE TEMP EXTERNAL TEMP REFERENCE CONTROL SCKI 41 V MODE 4 GPIO2 39 GPIO1 38 NC 36 TOS 3 V TEMP1 V TEMP V REF BD LTC ND REFERENCE V REF2 4 V REGULATOR V REG 3 C12 6 S12 WATCHDOG TIMER WDTB 37 7 C11 SCKO 3 24 S3 2 C2 26 S2 MUX Σ A/D CONVERTER 12 RESULTS REGISTER AND COMMUNICATIONS SDOI 2 CSBO 1 CSBI 44 SDO 43 SDI C1 28 S1 REFERENCE SCKI 41 V MODE 4 29 C 3 1Ω DIE TEMP EXTERNAL TEMP CONTROL GPIO2 39 GPIO1 38 TOS 36 NC V TEMP1 V TEMP2 V REF BD 11

12 LTC683-1/LTC683-3 TIMING DIAGRAM Timing Diagram of the Seria Interface t 1 t 2 t 4 t 6 t 3 t 7 SCKI SDI D3 D2 D1 D D7 D4 D3 t CSBI t 8 SDO D4 D3 D2 D1 D D7 D4 D3 PREVIOUS COMMAND CURRENT COMMAND TD OPERATION THEORY OF OPERATION The LTC683 is a data acquisition IC capabe of measuring the votage of 12 series connected battery ces. An input mutipexer connects the batteries to a 12-bit deta-sigma anaog-to-digita converter (ADC). An interna 8ppm/ C votage reference combined with the ADC give the LTC683 its outstanding measurement accuracy. The inherent benefits of the deta-sigma ADC versus other types of ADCs (e.g., successive approximation) are expained in Advantages of Deta-Sigma ADCs in the Appications Information section. Communication between the LTC683 and a host processor is handed by an SPI compatibe seria interface. As shown in Figure 1, the LTC683-1s or LTC683-3s can pass data up and down a stack of devices using simpe diodes for isoation. This operation is described in Seria Port in the Appications Information section. The LTC683 aso contains circuitry to baance ce votages. Interna MOSFETs can be used to discharge ces. These interna MOSFETs can aso be used to contro externa baancing circuits. Figure 1 iustrates ce baancing by interna discharge. Figure 12 shows the S pin controing an externa baancing circuit. It is important to note that the LTC683 makes no decisions about turning on/off the interna MOSFETs. This is competey controed by the host processor. The host processor writes vaues to 12 a configuration register inside the LTC683 to contro the switches. The watchdog timer inside the LTC683 wi turn off the discharge switches if communication with the host processor is interrupted. The LTC683 has three modes of operation: hardware shutdown, standby and measure. Hardware shutdown is a true zero power mode. Standby mode is a power saving state where a circuits except the seria interface are turned off. In measure mode, the LTC683 is used to measure ce votages and store the resuts in memory. Measure mode wi aso monitor each ce votage for overvotage (OV) and undervotage (UV) conditions. HARDWARE SHUTDOWN MODE The V pin can be disconnected from the C pins and the battery pack. If the V suppy pin is V, the LTC683 wi typicay draw ess than 1nA from the battery ces. A circuits inside the IC are off. It is not possibe to communicate with the IC when V = V. See the Appications Information section for hardware shutdown circuits. STANDBY MODE The LTC683 defauts (powers up) to standby mode. Standby mode is the owest suppy current state with a suppy connected. Standby current is typicay 12µA

13 LTC683-1/LTC683-3 OPERATION BATTERY POSITIVE 3V LTC683-3 IC #8 CSBO SDOI SCKO V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C S C4 S4 CSBI SDO SDI SCKI V MODE GPIO2 GPIO1 WDTB TOS V REG V REF V TEMP2 V TEMP1 NC C S1 C1 S2 C2 S3 C3 BATTERIES #2 TO #84 AND LTC683-3 ICs #3 TO #7 LTC683-3 IC #2 CSBO SDOI SCKO V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C S C4 S4 CSBI SDO SDI SCKI V MODE GPIO2 GPIO1 WDTB TOS V REG V REF V TEMP2 V TEMP1 NC C S1 C1 S2 C2 S3 C3 LTC683-3 IC #1 CSBO SDOI SCKO V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C S C4 S4 CSBI SDO SDI SCKI V MODE GPIO2 GPIO1 WDTB TOS V REG V REF V TEMP2 V TEMP1 NC C S1 C1 S2 C2 S3 C3 V2 OE2 V1 OE1 V2 V1 V2 V1 DIGITAL ISOLATOR 3V 3V MPU CS MISO MISI CLK MODULE IO F1 Figure Ce Battery Stack, Daisy-Chain Interface. This is a Simpified Schematic Showing the Basic Muti-IC Architecture 13

14 LTC683-1/LTC683-3 OPERATION when V = 44V. A circuits are turned off except the seria interface and the votage reguator. For the owest possibe standby current consumption a SPI ogic inputs shoud be set to ogic 1 eve. The LTC683 can be programmed for standby mode by setting the comparator duty cyce configuration bits, CDC[2:], to. If the part is put into standby mode whie ADC measurements are in progress, the measurements wi be interrupted and the ce votage registers wi be in an indeterminate state. To exit standby mode, the CDC bits must be written to a vaue other than. MEASURE MODE The LTC683 is in measure mode when the CDC bits are programmed with a vaue from 1 to 7. When CDC = 1 the LTC683 is on and waiting for a start ADC conversion command. When CDC is 2 through 7 the IC monitors each ce votage and produces an interrupt signa on the SDO pin indicating a ce votages are within the UV and OV imits. The vaue of the CDC bits determines how often the ces are monitored, and how much average suppy current is consumed. There are two methods for indicating the UV/OV interrupt status: togge poing (using a 1kHz output signa) and eve poing (using a high or ow output signa). The poing methods are described in the Seria Port section. The UV/OV imits are set by the V UV and V OV vaues in the configuration registers. When a ce votage exceeds the UV/OV imits a bit is set in the fag register. The UV and OV fag status for each ce can be determined using the Read Fag Register Group. An ADC measurement can be requested at any time when the IC is in measure mode. To initiate ce votage measurements whie in measure mode, a Start A/D Conversion is sent. After the command has been sent, the LTC683 wi indicate the A/D converter status via togge poing or eve poing (as described in the Seria Port section). During ce votage measurement commands, the UV and OV fags (within the fag register group) are aso updated. When the measurements are compete, the part wi continue monitoring UV and OV conditions at the rate designated by the CDC bits. Note that there is a µs window during each UV/OV comparison cyce where an ADC measurement request may be missed. This is an unikey event. 14 For exampe, the comparison cyce is 2 seconds when CDC = 7. Use the CLEAR command to detect missing ADC commands. Operating with Less than 12 Ces If fewer than 12 ces are connected to the LTC683, the unused input channes must be masked. The MCxI bits in the configuration registers are used to mask channes. In addition, the LTC683 can be configured to automaticay bypass the measurements of the top 2 ces, reducing power consumption and measurement time. If the CELL1 bit is high, the inputs for ce 11 and ce 12 are masked and ony the bottom 1 ce votages wi be measured. By defaut, the CELL1 bit is ow, enabing measurement of a 12 ce votages. Additiona information regarding operation with ess than 12 ces is provided in the appications section. ADC RANGE AND OUTPUT FORMAT The ADC outputs a 12-bit code with an offset of x2 (12 decima). The input votage can be cacuated as: V IN = (D OUT 12) V LSB ; V LSB = 1.mV where D OUT is a decima integer. For exampe, a V input wi have an output reading of x2. An ADC reading of x means the input was.768v. The absoute ADC measurement range is.768v to.376v. The resoution is V LSB = 1.mV = ( )/2 12. The usefu range is.3v to V. This range aows monitoring super capacitors, which coud have sma negative votage. Inputs beow.3v exceed the absoute maximum rating of the C pins. If a inputs are negative then the ADC range is reduced to.1v. Inputs above V wi have noisy ADC readings (see Typica Performance Characteristics curves). ADC MEASUREMENTS DURING CELL BALANCING The primary ce votage ADC measurement commands (STCVAD and STOWAD) automaticay turn off a ce s discharge switch whie its votage is being measured. The discharge switches for the ce above and the ce beow wi aso be turned off during the measurement. For exampe, discharge switches S4, S and S6 wi be off whie ce is being measured. The UV/OV comparison conversions in

15 OPERATION CDC modes 2 through 7 aso cause a momentary turn-off of the discharge switch. For exampe, switches S4, S and S6 wi be off whie ce is checked for a UV/OV condition. In some systems it may be desirabe to aow discharging to continue during ce votage measurements. The ce votage ADC conversion commands STCVDC and STOWDC aow the discharge switches to remain on during ce votage measurements. This feature aows the system to perform a sef test to verify the discharge functionaity. ADC REGISTER CLEAR COMMAND The cear command can be used to cear the ce votage registers and temperature registers. The cear command wi set a registers to xfff. This command is used to make sure conversions are being made. When ce votages are stabe, ADC resuts coud stay the same. If a start ADC conversion command is sent to the LTC683 but the PEC fais to match then the command is ignored and the votage register contents aso wi not change. Sending a cear command then reading back register contents is a way to make sure LTC683 is accepting commands and performing new measurements. The cear command takes 1ms to execute. ADC CONVERTER SELF TEST Two sef-test commands can be used to verify the functionaity of the digita portions of the ADC. The sef tests aso verify the ce votage registers and temperature monitoring registers. During these sef tests a test signa is appied to the ADC. If the circuitry is working propery a ce votage and temperature registers wi contain x or xaaa. The time required for the sef-test function is the same as required to measure a ce votages or a temperature sensors. MULTIPLEXER AND REFERENCE SELF TEST The LTC683 uses a mutipexer to measure the 12 battery ce inputs, as we as the temperature signas. A diagnostic command is used to vaidate the function of the mutipexer, the temperature sensor, and the precision reference circuit. Diagnostic registers wi be updated after LTC683-1/LTC683-3 each diagnostic test. The muxfai bit of the registers wi be 1 if the mutipexer sef test fais. A constant votage generated by the 2nd reference circuit wi be measured by the ADC and the resuts written to the diagnostic register. The votage reading shoud be 2.V ±16%. Readings outside this range indicate a faiure of the temperature sensor circuit, the precision reference circuit, or the anaog portion of the ADC. The DAGN command executes in 16.4ms, which is the sum of the 12-ce t CYCLE and 3 temperature t CYCLE. The diagnostic read command can be used to read the registers. USING THE GENERAL PURPOSE INPUTS/OUTPUTS (GPIO1, GPIO2) The LTC683 has two genera purpose digita input/output pins. By writing a GPIO configuration register bit to a ogic ow, the open-drain output can be activated. The GPIOs give the user the abiity to turn on/off circuitry around the LTC683. One exampe might be a circuit to verify the operation of the system. When a GPIO configuration bit is written to a ogic high, the corresponding GPIO pin may be used as an input. The read back vaue of that bit wi be the ogic eve that appears at the GPIO pin. WATCHDOG TIMER CIRCUIT The LTC683 incudes a watchdog timer circuit. The watchdog timer is on for a modes except CDC =. The watchdog timer times out if no vaid command is received for 1 to 2. seconds. When the watchdog timer circuit times out, the WDTB open-drain output is asserted ow and the configuration register bits are reset to their defaut (power-up) state. In the power-up state, CDC is, the S outputs are off and the IC is in the ow power standby mode. The WDTB pin remains ow unti a vaid command is received. The watchdog timer provides a means to turn off ce discharging shoud communications to the MPU be interrupted. There is no need for the watchdog timer at CDC = since discharging is off. The open-drain WDTB output can be wire ORd with other externa open-drain signas. Puing the WDTB signa ow wi not initiate a 1

16 LTC683-1/LTC683-3 OPERATION watchdog event, but the CNFGO bit 7 wi refect the state of this signa. Therefore, the WDTB pin can be used to monitor externa digita events if desired. SERIAL PORT Overview The LTC683 has an SPI bus compatibe seria port. Severa devices can be daisy chained in series. There are two sets of seria port pins, designated as ow side and high side. The ow side and high side ports enabe devices to be daisy chained even when they operate at different power suppy potentias. In a typica configuration, the positive power suppy of the first, bottom device is connected to the negative power suppy of the second, top device, as shown in Figure 1. When devices are stacked in this manner, they can be daisy chained by connecting the high side port of the bottom device to the ow side port of the top device. With this arrangement, the master writes to or reads from the cascaded devices as if they formed one ong shift register. The LTC683-1/LTC683-3 transate the votage eve of the signas between the ow side and high side ports to pass data up and down the battery stack. Physica Layer On the LTC683-1/LTC683-3, seven pins comprise the ow side and high side ports. The ow side pins are CSBI, SCKI, SDI and SDO. The high side pins are CSBO, SCKO and SDOI. CSBI and SCKI are aways inputs, driven by the master or by the next ower device in a stack. CSBO and SCKO are aways outputs that can drive the next higher device in a stack. SDI is a data input when writing to a stack of devices. For devices not at the bottom of a stack, SDI is a data output when reading from the stack. SDOI is a data output when writing to and a data input when reading from a stack of devices. SDO is an open-drain output that is ony used on the bottom device of a stack, where it may be tied with SDI, if desired, to form a singe, bi-directiona port. The SDO pin on the bottom device of a stack requires a pu-up resistor. For devices up in the stack, SDO shoud be tied to the oca or eft foating. To communicate between daisy-chained devices, the high side port pins of a ower device (CSBO, SCKO and SDOI) shoud be connected through high votage diodes to the 16 respective ow side port pins of the next higher device (CSBI, SCKI and SDI). In this configuration, the devices communicate using current rather than votage. To signa a ogic high from the ower device to the higher device, the ower device sinks a smaer current from the higher device pin. To signa a ogic ow, the ower device sinks a arger current. Likewise, to signa a ogic high from the higher device to the ower device, the higher device sources a arger current to the ower device pin. To signa a ogic ow, the higher device sources a smaer current. See Figure 2. Since CSBO, SCKO and SDOI votages are cose to the of high side device, the of the high side device must be at east V higher than that of the ow side device to guarantee current fows of the current mode interface. It is recommended that high votage diodes be paced in series with the SPI daisy-chain signas as shown if Figure 1. These diodes prevent reverse votage stress on the IC if a battery group bus bar is removed. See Battery Interconnection Integrity for additiona information. Standby current consumed in the current mode seria interface is minimized when CSBI, SCKI and SDI are a high. The votage mode pin (V MODE ) determines whether the ow side seria port is configured as votage mode or current mode. For the bottom device in a daisy-chain stack, this pin must be pued high (tied to V REG ). The other devices in the daisy chain must have this pin pued ow (tied to ) to designate current mode communication. To designate the top-of-stack device for poing commands, the TOS V SENSE (WRITE) WRITE LOW SIDE PORT ON HIGHER DEVICE READ 1 HIGH SIDE PORT ON LOWER DEVICE V SENSE (READ) Figure 2. Current Mode Interface F2

17 OPERATION pin on the top device of a daisy chain must be tied high. The other devices in the stack must have TOS tied ow. See Figure 1. Data Link Layer Cock Phase And Poarity: The LTC683 SPI compatibe interface is configured to operate in a system using CPHA = 1 and CPOL = 1. Consequenty, data on SDI must be stabe during the rising edge of SCKI. Data Transfers: Every byte consists of 8 bits. Bytes are transferred with the most significant bit (MSB) first. On a write, the data vaue on SDI is atched into the device on the rising edge of SCKI (Figure 3). Simiary, on a read, the data vaue output on SDO is vaid during the rising edge of SCKI and transitions on the faing edge of SCKI (Figure 4). CSBI must remain ow for the entire duration of a command sequence, incuding between a command byte and subsequent data. On a write command, data is atched in on the rising edge of CSBI. LTC683-1/LTC683-3 Network Layer PEC Byte: The packet error code (PEC) byte is a cycic redundancy check (CRC) vaue cacuated for a of the bits in a register group in the order they are passed, using the initia PEC vaue of 11 (x41) and the foowing characteristic poynomia: x 8 x 2 x 1 To cacuate the 8-bit PEC vaue, a simpe procedure can be estabished: 1. Initiaize the PEC to For each bit DIN coming into the register group, set IN = DIN XOR PEC[7], then IN1=PEC[] XOR IN, IN2 = PEC[1] XOR IN. 3. Update the 8-bit PEC as PEC[7] = PEC[6], PEC[6] = PEC[], PEC[3] = PEC[2], PEC[2] = IN2, PEC[1] = IN1, PEC[] = IN. 4. Go back to step 2 unti a data are shifted. The 8-bit resut is the fina PEC byte. CSBI SCKI SDI MSB (CMD) BIT 6 (CMD) LSB (PEC) MSB (DATA) LSB (PEC) F3 Figure 3. Transmission Format (Write) CSBI SCKI SDI MSB (CMD) BIT 6 (CMD) LSB (PEC) SDO MSB (DATA) LSB (PEC) F4 Figure 4. Transmission Format (Read) 17

18 LTC683-1/LTC683-3 OPERATION An exampe to cacuate the PEC is isted in Tabe 1 and Figure. The PEC of the 1 byte data x1 is computed as xc7 after the ast bit of the byte cocked in. For mutipe byte data, the PEC is vaid at the end (LSB) of the ast byte. LTC683 cacuates PEC byte for any command or data received and compares it with the PEC byte foowing the command or data. The command or data is regarded as vaid ony if the PEC bytes match. LTC683 aso attaches the cacuated PEC byte at the end of the data it shifts out. For daisy-chained LTC683-1/LTC683-3, each device computes the PEC byte based on the data it sends out or receives for itsef. The data passing through for other devices do affect its PEC. On a read command, each device shifts its data out with, and then shifts out the PEC byte it computed, MSB first. For exampe, when reading the fag registers from two stacked devices (bottom device A and top device B), the data wi be output in the foowing order: FLGR(A), FLGR1(A), FLGR2(A), PEC(A), FLGR(B), FLGR1(B), FLGR2(B), PEC(B ) On a write command, each device receives its data and then the PEC byte, MSB first. For exampe, when writing configuration registers to two stacked devices (bottom device A and top device B), the data wi be input in the foowing order: CFGRR(B), CFGR1(B),, CFGR(B), PEC(B), CFGR(A), CFGR1(A),, CFGR(A), PEC(A) Broadcast Commands: A broadcast command is one to which a devices on the bus wi respond, regardess of device address. See the Bus Protocos and Commands sections. In daisy-chained configurations, a devices in the chain receive the command bytes simutaneousy. For exampe, to initiate ADC conversions in a stack of devices, a singe STCVAD command is sent, and a devices wi start conversions at the same time. For read and write commands, a singe command is sent, and then the stacked devices effectivey turn into a cascaded shift register, in which data is shifted through each device to the next higher (on a write) or the next ower (on a read) device in the stack. See the Seria Command Exampes section. Poing Methods: For ADC conversions, three methods can be used to determine ADC competion. First, a controer can start an ADC conversion and wait for the specified conversion time to pass before reading the resuts. The second method is to hod CSBI ow after an ADC start command has been sent. The ADC conversion status wi be output on SDO (Figure 6). A probem with the second method is that the controer is not free to do other seria communication whie waiting for ADC conversions to compete. The third method overcomes this imitation. The controer can send an ADC start command, perform other tasks, and then send a po ADC converter status (PLADC) command to determine the status of the ADC conversions (Figure 7). For OV/UV interrupt status, the po interrupt status (PLINT) command can be used to quicky determine whether any ce in a stack is in an overvotage or undervotage condition (Figure 7). Tabe 1. Procedure to Cacuate PEC Byte CLOCK CYCLE DIN IN IN1 IN2 PEC[7] PEC[6] PEC[] PEC[4] PEC[3] PEC[2] PEC[1] PEC[]

19 LTC683-1/LTC683-3 OPERATION XOR PEC[7] IN DATAIN PEC[] 1 INO = DATAIN XOR PEC[7]; BEGIN PEC[7:] = x41 CLOCK D Q CLK Q DTFF 2 PEC1 = PEC[] XOR IN; INO XOR PEC1 PEC[] PEC[1] D Q CLK Q DTFF PEC Hardware and Software Exampe BEGIN PEC[7:] = x41 1 INO = DATAIN XOR PEC[7]; 2 PEC1 = PEC[] XOR IN; 3 PEC2 = PEC[1] XOR IN; 4 PEC[7:] = {PEC[6:2], PEC2, PEC1, IN}; END 3 PEC2 = PEC[1] XOR IN; 4 PEC[7:] = {PEC[6:2], PEC2, PEC1, IN}; IN XOR PEC2 PEC[2] D Q END PEC[2] PEC[3] PEC[3] PEC[4] PEC[4] D Q D Q PEC[] D Q PEC[6] PEC[] PEC[6] D Q PEC[7] PEC[7] PEC[1] CLK Q DTFF CLK Q DTFF Figure D Q F Q CLK Q DTFF CLK Q DTFF CLK Q DTFF CLK DTFF 19

20 LTC683-1/LTC683-3 OPERATION CSBI t CYCLE SCKI SDI MSB (CMD) BIT6 (CMD) LSB (PEC) SDO TOGGLE OR LEVEL POLL F6 Figure 6. Transmission Format (ADC Conversion and Po) CSBI SCKI SDI MSB (CMD) BIT6 (CMD) LSB (PEC) SDO TOGGLE OR LEVEL POLL F7 Figure 7. Transmission Format (PLADC Conversion or PLINT) Togge Poing: Togge poing aows a robust determination both of device states and of the integrity of the connections between the devices in a stack. Togge poing is enabed when the LVLPL bit is ow. After entering a poing command, the data out ine wi be driven by the save devices based on their status. When poing for the ADC converter status, data out wi be ow when any device is busy performing an ADC conversion and wi togge at 1kHz when no device is busy. Simiary, when poing for interrupt status, the output wi be ow when any device has an interrupt condition and wi togge at 1kHz when none has an interrupt condition. Togge Poing Daisy-Chained Broadcast Poing: The SDO pin (bottom device) or SDI pin (stacked devices) wi be ow if a device is busy/in interrupt. If it is not busy/not in interrupt, the device wi pass the signa from the SDOI input to data out (if not the top-of-stack device) or togge the data out ine at 1kHz (if the top-of-stack device). The master pus CSBI high to exit poing. Leve Poing: Leve poing is enabed when the LVLPL bit is high. After entering a poing command, the data out ine wi be driven by the save devices based on their status. When poing for the ADC converter status, data out wi be ow when any device is busy performing an ADC conversion and wi be high when no device is busy. Simiary, when poing for interrupt status, the output wi be ow when any device has an interrupt condition and wi be high when none has an interrupt condition. Leve Poing Daisy-Chained Broadcast Poing: The SDO pin (bottom device) or SDI pin (stacked devices) wi be ow if a device is busy/in interrupt. If it is not busy/not in interrupt, the device wi pass the eve from the SDOI input to data out (if not the top-of-stack device) or hod the data out ine high (if the top-of-stack device). Therefore, if any device in the chain is busy or in interrupt, the SDO signa at the bottom of the stack wi be ow. If a devices are not busy/not in interrupt, the SDO signa at the bottom of the stack wi be high. The master pus CSBI high to exit poing. 2

21 LTC683-1/LTC683-3 OPERATION Tabe 2. Protoco Key PEC Packet Error Code Master-to-Save N Number of Bits Save-to-Master... Continuation of Protoco Compete Byte of Data Tabe 3. Broadcast Po Command 8 8 Command PEC Po Data Revision Code: The diagnostic register group contains a 2-bit revision code. If software detection of device revision is necessary, then contact the factory for detais. Otherwise, the code can be ignored. In a cases, however, the vaues of a bits must be used when cacuating the packet error code (PEC) byte on data reads. Bus Protocos: There are 3 different protoco formats, depicted in Tabe 3 through Tabe. Tabe 2 is the key for reading the protoco diagrams. Tabe 4. Broadcast Read Command PEC Data Byte Low Data Byte High PEC Shift Byte 1 Shift Byte N Tabe. Broadcast Write Command PEC Data Byte Low Data Byte High PEC Shift Byte 1 Shift Byte N See Seria Command exampes. Tabe 6. Command Codes and PEC Bytes COMMAND DESCRIPTION NAME CODE PEC Write Configuration Register Group WRCFG 1 C7 Read Configuration Register Group RDCFG 2 CE Read A Ce Votage Group RDCV 4 DC Read Ce Votages 1-4 RDCVA 6 D2 Read Ce Votages -8 RDCVB 8 F8 Read Ce Votages 9-12 RDCVC A F6 Read Fag Register Group RDFLG C E4 Read Temperature Register Group RDTMP E EA Start Ce Votage ADC Conversions and Po Status STCVAD A Ce 1 Ce 2 Ce 3 Ce 4 Ce Ce 6 Ce 7 Ce 8 Ce 9 Ce 1 Ce 11 Ce 12 Cear (FF) Sef Test1 Sef Test A 1B 1C 1D 1E 1F B B7 BE B9 AC AB A2 A 88 8F A 9D 21

22 LTC683-1/LTC683-3 OPERATION Tabe 6. Command Codes and PEC Bytes (continued) COMMAND DESCRIPTION NAME CODE PEC Start Open-Wire ADC Conversions and Po Status STOWAD A Ce 1 Ce 2 Ce 3 Ce 4 Ce Ce 6 Ce 7 Ce 8 Ce 9 Ce 1 Ce 11 Ce 12 Start Temperature ADC Conversions and Po Status STTMPAD A Externa1 Externa2 Interna Sef Test 1 Sef Test 2 Po ADC Converter Status PLADC 4 7 Po Interrupt Status PLINT 77 Start Diagnose and Po Status DAGN 2 79 Read Diagnostic Register RDDGNR 4 6B Start Ce Votage ADC Conversions and Po Status, with Discharge Permitted STCVDC Start Open-Wire ADC Conversions and Po Status, with Discharge Permitted STOWDC A Ce 1 Ce 2 Ce 3 Ce 4 Ce Ce 6 Ce 7 Ce 8 Ce 9 Ce 1 Ce 11 Ce 12 A Ce 1 Ce 2 Ce 3 Ce 4 Ce Ce 6 Ce 7 Ce 8 Ce 9 Ce 1 Ce 11 Ce A 2B 2C E 3F A 6B 6C A 7B 7C E 29 3C 3B F E 9 7A 7D E7 E E9 EE FB FC F F2 DF D8 D1 D6 C E 8B 8C 8 82 AF A8 A1 A6 B3 22

23 LTC683-1/LTC683-3 OPERATION Tabe 7. Configuration (CFG) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT BIT 4 BIT 3 BIT 2 BIT 1 BIT CFGR RD/WR WDT GPIO2 GPIO1 LVLPL CELL1 CDC[2] CDC[1] CDC[] CFGR1 RD/WR DCC8 DCC7 DCC6 DCC DCC4 DCC3 DCC2 DCC1 CFGR2 RD/WR MC4I MC3I MC2I MC1I DCC12 DCC11 DCC1 DCC9 CFGR3 RD/WR MC12I MC11I MC1I MC9I MC8I MC7I MC6I MCI CFGR4 RD/WR VUV[7] VUV[6] VUV[] VUV[4] VUV[3] VUV[2] VUV[1] VUV[] CFGR RD/WR VOV[7] VOV[6] VOV[] VOV[4] VOV[3] VOV[2] VOV[1] VOV[] Tabe 8. Ce Votage (CV) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT BIT 4 BIT 3 BIT 2 BIT 1 BIT CVR RD C1V[7] C1V[6] C1V[] C1V[4] C1V[3] C1V[2] C1V[1] C1V[] CVR1 RD C2V[3] C2V[2] C2V[1] C2V[] C1V[11] C1V[1] C1V[9] C1V[8] CVR2 RD C2V[11] C2V[1] C2V[9] C2V[8] C2V[7] C2V[6] C2V[] C2V[4] CVR3 RD C3V[7] C3V[6] C3V[] C3V[4] C3V[3] C3V[2] C3V[1] C3V[] CVR4 RD C4V[3] C4V[2] C4V[1] C4V[] C3V[11] C3V[1] C3V[9] C3V[8] CVR RD C4V[11] C4V[1] C4V[9] C4V[8] C4V[7] C4V[6] C4V[] C4V[4] CVR6 RD CV[7] CV[6] CV[] CV[4] CV[3] CV[2] CV[1] CV[] CVR7 RD C6V[3] C6V[2] C6V[1] C6V[] CV[11] CV[1] CV[9] CV[8] CVR8 RD C6V[11] C6V[1] C6V[9] C6V[8] C6V[7] C6V[6] C6V[] C6V[4] CVR9 RD C7V[7] C7V[6] C7V[] C7V[4] C7V[3] C7V[2] C7V[1] C7V[] CVR1 RD C8V[3] C8V[2] C8V[1] C8V[] C7V[11] C7V[1] C7V[9] C7V[8] CVR11 RD C8V[11] C8V[1] C8V[9] C8V[8] C8V[7] C8V[6] C8V[] C8V[4] CVR12 RD C9V[7] C9V[6] C9V[] C9V[4] C9V[3] C9V[2] C9V[1] C9V[] CVR13 RD C1V[3] C1V[2] C1V[1] C1V[] C9V[11] C9V[1] C9V[9] C9V[8] CVR14 RD C1V[11] C1V[1] C1V[9] C1V[8] C1V[7] C1V[6] C1V[] C1V[4] CVR1* RD C11V[7] C11V[6] C11V[] C11V[4] C11V[3] C11V[2] C11V[1] C11V[] CVR16* RD C12V[3] C12V[2] C12V[1] C12V[] C11V[11] C11V[1] C11V[9] C11V[8] CVR17* RD C12V[11] C12V[1] C12V[9] C12V[8] C12V[7] C12V[6] C12V[] C12V[4] *Registers CVR1, CVR16, and CVR17 can ony be read if the CELL1 bit in register CFGR is ow Tabe 9. Fag (FLG) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT BIT 4 BIT 3 BIT 2 BIT 1 BIT FLGR RD C4OV C4UV C3OV C3UV C2OV C2UV C1OV C1UV FLGR1 RD C8OV C8UV C7OV C7UV C6OV C6UV COV CUV FLGR2 RD C12OV* C12UV* C11OV* C11UV* C1OV C1UV C9OV C9UV * Bits C11UV, C12UV, C11OV and C12OV are aways ow if the CELL1 bit in register CFGR is high 23

24 LTC683-1/LTC683-3 OPERATION Tabe 1. Temperature (TMP) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT BIT 4 BIT 3 BIT 2 BIT 1 BIT TMPR RD ETMP1[7] ETMP1[6] ETMP1[] ETMP1[4] ETMP1[3] ETMP1[2] ETMP1[1] ETMP1[] TMPR1 RD ETMP2[3] ETMP2[2] ETMP2[1] ETMP2[] ETMP1[11] ETMP1[1] ETMP1[9] ETMP1[8] TMPR2 RD ETMP2[11] ETMP2[1] ETMP2[9] ETMP2[8] ETMP2[7] ETMP2[6] ETMP2[] ETMP2[4] TMPR3 RD ITMP[7] ITMP[6] ITMP[] ITMP[4] ITMP[3] ITMP[2] ITMP[1] ITMP[] TMPR4 RD NA NA NA THSD ITMP[11] ITMP[1] ITMP[9] ITMP[8] Tabe 11. Packet Error Code (PEC) REGISTER RD/WR BIT 7 BIT 6 BIT BIT 4 BIT 3 BIT 2 BIT 1 BIT PEC RD PEC[7] PEC[6] PEC[] PEC[4] PEC[3] PEC[2] PEC[1] PEC[] Tabe 12. Diagnostic Register Group REGISTER RD/WR BIT 7 BIT 6 BIT BIT 4 BIT 3 BIT 2 BIT 1 BIT DGNR RD REF[7] REF[6] REF[] REF[4] REF[3] REF[2] REF[1] REF[] DGNR1 RD REV[1] REV[] MUXFAIL NA REF[11] REF[1] REF[9] REF[8] Tabe 13. Memory Bit Descriptions NAME DESCRIPTION VALUES CDC Comparator Duty Cyce CDC (defaut) UV/OV COMPARATOR PERIOD N/A (Comparator Off) Standby Mode CELL1 1-Ce Mode = 12-ce mode (defaut); 1 = 1-ce mode LVLPL Leve Poing Mode = togge poing (defaut); 1 = eve poing V REF POWERED DOWN BETWEEN MEASUREMENTS Yes CELL VOLTAGE MEASUREMENT TIME 1 N/A (Comparator Off) No 13ms 2 13ms No 13ms 3 13ms No 13ms 4 ms No 13ms 13ms Yes 21ms 6 ms Yes 21ms 7 2ms Yes 21ms GPIO1 GPIO1 Pin Contro Write: = GPIO1 pin pu-down on; 1 = GPIO1 pin pu-down off (defaut) Read: = GPIO1 pin at ogic ; 1 = GPIO1 pin at ogic 1 GPIO2 GPIO2 Pin Contro Write: = GPIO2 pin pu-down on; 1 = GPIO2 pin pu-down off (defaut) Read: = GPIO2 pin at ogic ; 1 = GPIO2 pin at ogic 1 WDT Watchdog Timer Read: = WDT pin at ogic ; 1 = WDT pin at ogic 1 DCCx Discharge Ce x x = = turn off shorting switch for ce x (defaut); 1 = turn on shorting switch V UV Undervotage Comparison Votage* Comparison votage = (V U 31) 16 1.mV V OV Overvotage Comparison Votage* Comparison votage = (V O 32) 16 1.mV MUXFAIL Mutipexer Sef Test Resut Read: = test passed; 1 = test faied N/A 24

25 LTC683-1/LTC683-3 OPERATION Tabe 13. Memory Bit Descriptions (continued) NAME DESCRIPTION VALUES MCxI CxV CxUV CxOV Mask Ce x Interrupts Ce x Votage* Ce x Undervotage Fag Ce x Overvotage Fag x = = enabe interrupts for ce x (defaut) 1 = turn off interrupts and cear fags for ce x x = bit ADC measurement vaue for ce x ce votage for ce x = (Cx 12) 1.mV reads as xfff whie A/D conversion in progress x = ce votage compared to V UV comparison votage = ce x not fagged for undervotage condition; 1 = ce x fagged x = ce votage compared to V OV comparison votage = ce x not fagged for overvotage condition; 1 = ce x fagged ETMPx Externa Temperature Measurement* Temperature measurement votage = (ETMPx 12) 1.mV THSD Therma Shutdown Status = therma shutdown has not occurred; 1 = therma shutdown has occurred Status ceared to on read of Therma Register Group REV Revision Code Device revision code ITMP Interna Temperature Measurement* Temperature measurement votage = (ITMP 12) 1.mV = 8mV * T( K) PEC Packet Error Code Cycic redundancy check (CRC) vaue REF Reference Votage for Diagnostics This reference votage = (REF 12) 1.mV. Norma range is within 2.1V to 2.9V *Votage equations use the decima vaue of the registers, to 49 for 12-bit and to 2 for 8-bit registers SERIAL COMMAND EXAMPLES Exampes beow use a configuration of three stacked LTC683-1 or LTC683-3 devices: bottom (B), midde (M), and top (T) Write Configuration Registers (Figure 8) 1. Pu CSBI ow 2. Send WRCFG command and its PEC byte 3. Send CFGR byte for top device, then CFGR1 (T), CFGR (T), PEC of CFGR(T) to CFGR(T) 4. Send CFGR byte for midde device, then CFGR1 (M) CFGR (M) ), PEC of CFGR(M) to CFGR(M). Send CFGR byte for bottom device, then CFGR1 (B), CFGR (B) ), PEC of CFGR(B) to CFGR(B) 6. Pu CSBI high; data atched into a devices on rising edge of CSBI. S pins respond as data atched. Cacuation of seria interface time for sequence above: Number of devices in stack = N Number of bytes in sequence = B = 2 command byte and 7 data bytes per device = 2 7 N Seria port frequency per bit = F Time = (1/F) B 8 bits/byte = (1/F) (2 7 N) 8 Time for 3-ce exampe above, with 1MHz seria port = (1/1) (2 7 3) 8 = 184µs 2

26 LTC683-1/LTC683-3 OPERATION CSBI SCKI SDI WRCFG CFGR PEC t d t d < 2µs IF Sn IS UNLOADED Sn (n = 1 TO 12) Figure 8. S Pin Action and SPI Transmission Sn, DISCHARGE PIN STATE F8 Read Ce Votage Registers (12 Ce Mode) 1. Pu CSBI ow 2. Send RDCV command and PEC 3. Read CVR byte of bottom device, then CVR1 (B), CVR2 (B), CVR17 (B), and then PEC (B) 4. Read CVR byte of midde device, then CVR1 (M), CVR2 (M), CVR17 (M), and then PEC (M). Read CVR byte for top device, then CVR1 (T), CVR2 (T), CVR17 (T), and then PEC (T) 6. Pu CSBI high Cacuation of seria interface time for sequence above: Number of devices in stack = N Number of bytes in sequence = B = 2 command byte, and 18 data bytes pus 1 PEC byte per device = 2 19 N Seria port frequency per bit = F Time = (1/F) B 8 bits/byte = (1/F) (2 19 N) 8 Time for 3-ce exampe above, with 1MHz seria port = (1/1) (2 19 3) 8 = 472µs Start Ce Votage ADC Conversions and Po Status (Togge Poing) 1. Pu CSBI ow 2. Send STCVAD command byte and PEC (a devices in stack start ADC conversions simutaneousy) 3. SDO output from bottom device pued ow for approximatey 12ms 4. SDO output togges at 1kHz rate, indicating conversions compete for a devices in daisy chain. Pu CSBI high to exit poing Start Ce Votage ADC Conversions and Po Status (Broadcast Command with Togge Poing) 1. Pu CSBI ow 2. Send STCVAD command and PEC (a devices in stack start ADC conversions simutaneousy) 3. SDO output of a devices in parae pued ow for approximatey 12ms 4. SDO output togges at 1kHz rate, indicating conversions compete for a devices in the daisy chain. Pu CSBI high to exit poing Po Interrupt Status (Leve Poing) 1. Pu CSBI ow 2. Send PLINT command and PEC 3. SDO output from bottom device pued ow if any device has an interrupt condition; otherwise, SDO high 4. Pu CSBI high to exit poing 26

27 LTC683-1/LTC683-3 APPLICATIONS INFORMATION DIFFERENCE BETWEEN THE LTC683-1 AND LTC683 3 The ony difference between the LTC683-1 and the LTC683-3 is the bonding of the and C pins. The and C are separate signas on every LTC683 die. In the LTC683-1 package, the and C signas are shorted together by bonding these signas to the same pin. In the LTC683 3 package, and C are separate pins. Therefore, the LTC683-1 is pin compatibe with the LTC For new designs the LTC683-3 pinout aows a Kevin connection to C (Figure 24). CELL VOLTAGE FILTERING The LTC683 empoys a samping system to perform its anaog-to-digita conversions and provides a conversion resut that is essentiay an average over the.ms conversion window, provided there isn t noise aiasing with respect to the deta-sigma moduator rate of 12kHz. This indicates that a owpass fiter with 3dB attenuation at khz may be beneficia. Since the deta-sigma integration bandwidth is about 1kHz, the fiter corner need not be ower than this to assure accurate conversions. Series resistors of 1Ω may be inserted in the input paths without introducing meaningfu measurement error. Shunt capacitors may be added from the ce inputs to, creating RC fitering as shown in Figure 9. The ce baancing MOSFET in Figure 12 can cause a sma transient when it switches on and off. Keeping the cutoff frequency of the RC fiter reativey high wi aow adequate setting prior to the actua conversion. A deay of about µs is provided in the ADC timing, so a 16kHz LPF is optima (1Ω,.) and offers 3dB of noise rejection. 1Ω 1nF 1Ω 1nF 7.V F9 Figure 9. Adding RC Fitering to the Ce Inputs (One Ce Connection Shown) Cn C(n 1) Larger series resistors and shunt capacitors can be used to ower the fiter bandwidth. The measurement error due to the arger component vaues is a compex function of the component vaues. The error aso depends on how often measurements are made. Tabe 14 is an exampe. In each exampe a 3.6V ce is being measured and the error is dispayed in miivots. There is a RC fiter in series with inputs C1 through C12 for the LTC There is an RC fiter in series with inputs C through C12 for the LTC Tabe 14. Ce Measurement Errors vs Input RC Vaues R = 1Ω, C =. R = 1k, C =. R = 1k, C = R = 1k, C = 3.3µF Ce 1 Error (mv, LTC683-1) Ce 2 to Ce 12 (mv) For the LTC683-1, no resistor shoud be paced in series with the pin. Because the suppy current fows from the pin, any resistance on this pin coud generate a significant conversion error for ce 1, and the error of ce 1 caused by the RC fiter differs from errors of ce 2 to ce 12. OPEN CONNECTION DETECTION When a ce input (C pin) is open, it affects two ce measurements. Figure 1 shows an open connection to C3, in an appication without externa fitering between the C pins and the ces. During norma ADC conversions (that is, using the STCVAD command), the LTC683 wi give near zero readings for B3 and B4 when C3 is open. The zero reading for B3 occurs because during the measurement of B3, the ADC input resistance wi pu C3 to the C2 potentia. Simiary, during the measurement of B4, the ADC input resistance pus C3 to the C4 potentia. Figure 11 shows an open connection at the same point in the ce stack as Figure 1, but this time there is an externa fitering network sti connected to C3. Depending on the vaue of the capacitor remaining on C3, a norma measurement of B3 and B4 may not give near-zero readings, since the C3 pin is not truy open. In fact, with a arge externa capacitance on C3, the C3 votage wi be charged midway 27

28 LTC683-1/LTC683-3 APPLICATIONS INFORMATION B4 B3 B4 B3 between C2 and C4 after severa cyces of measuring ces B3 and B4. Thus the measurements for B3 and B4 may indicate a vaid ce votage when in fact the exact state of B3 and B4 is unknown. To reiaby detect an open connection, the command STOWAD is provided. With this command, two 1µA current sources are connected to the ADC inputs and turned on during a ce conversions. Referring again to Figure 11, with the STOWAD command, the C3 pin wi be pued down by the 1µA current source during the B3 ce measurement and during the B4 ce measurement. This wi tend to decrease the B3 measurement resut and increase the B4 measurement resut reative to the norma STCVAD command. The biggest change is observed in the B4 measurement when C3 is open. So, the best method to detect an open wire at input C3 is to ook for an increase 28 C F4 C F C4 C3 C2 C1 MUX Figure 1. Open Connection C4 C3 C2 27 C1 29 MUX 1µA LTC F1 1µA Figure 11. Open Connection with RC Fitering LTC F11 in the vaue of battery connected between inputs C3 and C4 (battery B4). The foowing agorithm can be used to detect an open connection to ce pin Cn: 1. Issue a STOWAD command (with 1µA sources connected). 2. Issue a RDCV command and store a ce measurements into array CELLA(n). 3. Issue the 2nd STOWAD command (with 1µA sources connected). 4. Issue the 2nd RDCV command and store a ce measurements into array CELLB(n).. For battery ces, if CELLA(1) < or CELLB(1) <, must be open. If CELLA(12) < or CELLB(12) <, C12 must be open. For n = 2 to 11, if CELLB(n1) CELLA(n1) > 2mV, or CELLB(n1) reaches the fu scae of.37v, then Cn is open. The 2mV threshod is chosen to provide toerance for measurement errors. For a system with the capacitor connected to Cn arger than.µf, repeating step 3 severa times wi discharge the externa capacitor enough to meet the criteria. If the top C pin is open yet V is sti connected, then the best way to detect an open connection to the top C pin is by comparing the sum of a ce measurements using the STCVAD command to an auxiiary measurement of the sum of a the ces, using a method simiar to that shown in Figure 21. A significanty ower resut for the sum of a 12 ces suggests an open connection to the top C pin, provided it was aready determined that no other C pin is open. USING THE S PINS AS DIGITAL OUTPUTS OR GATE DRIVERS The S outputs incude an interna pu-up PMOS. Therefore the S pins wi behave as a digita output when oaded with a high impedance, e.g., the gate of an externa MOSFET. For appications requiring high battery discharge currents, connect a discrete PMOS switch device and suitabe

29 APPLICATIONS INFORMATION discharge resistor to the ce, and the gate termina to the S output pin, as iustrated in Figure 12. Si231DS 33Ω 1W Figure 12. Externa Discharge FET Connection (One Ce Shown) POWER DISSIPATION AND THERMAL SHUTDOWN The MOSFETs connected to the pins S1 through S12 can be used to discharge battery ces. An externa resistor shoud be used to imit the power dissipated by the MOSFETs. The maximum power dissipation in the MOSFETs is imited by the amount of heat that can be toerated by the LTC683. Excessive heat resuts in eevated die temperatures. The eectrica characteristics for the LTC683 I-grade are guaranteed for die temperatures up to 8 C. Litte or no degradation wi be observed in the measurement accuracy for die temperatures up to 1 C. Damage may occur above 1 C, therefore the recommended maximum die temperature is 12 C. To protect the LTC683 from damage due to overheating, a therma shutdown circuit is incuded. Overheating of the device can occur when dissipating significant power in the ce discharge switches. The probem is exacerbated when the therma conductivity of the system is poor. The therma shutdown circuit is enabed whenever the device is not in standby mode (see Modes of Operation). It wi aso be enabed when any current mode input or output is sinking or sourcing current. If the temperature detected on the device goes above approximatey 14 C, the configuration registers wi be reset to defaut states, turning off a discharge switches and disabing ADC conversions. When a therma shutdown has occurred, the THSD bit in the temperature register group wi go high. The bit is ceared by performing a read of the temperature registers (RDTMP command). 3.3k F12 C (n) S (n) C (n 1) LTC683-1/LTC683-3 Since therma shutdown interrupts norma operation, the interna temperature monitor shoud be used to determine when the device temperature is approaching unacceptabe eves. USING THE LTC683 WITH LESS THAN 12 CELLS If the LTC683 is powered by the stacked ces, the minimum number of ces is governed by the suppy votage requirements of the LTC683. The sum of the ce votages must be 1V to guarantee that a eectrica specifications are met. Figure 13 shows an exampe of the LTC683 when used to monitor seven ces. The owest C inputs connect to theseven ces and the upper C inputs connect to C12. Other configurations, e.g., 9 ces, woud be configured in the same way: the owest C inputs connected to the battery ces and the unused C inputs connected to C12. The unused inputs wi resut in a reading of V for those channes. The ADC can aso be commanded to measure a stack of 1 or 12 ces, depending on the state of the CELL1 bit in the contro register. The ADC can aso be commanded to measure any individua ce votage. FAULT PROTECTION Care shoud aways be taken when using high energy sources such as batteries. There are numerous ways that systems can be misconfigured when considering the assemby and service procedures that might affect a battery system during its usefu ifespan. Tabe 1 shows the various situations that shoud be considered when panning protection circuitry. The first five scenarios are to be anticipated during production and appropriate protection is incuded within the LTC683-1/LTC683-3 device itsef. BATTERY INTERCONNECTION INTEGRITY The FMEA scenarios invoving a break in the stack of battery ces are potentiay the most damaging. In the case where the battery stack has a discontinuity between groupings of ces monitored by LTC683 ICs, any oad wi force a arge reverse potentia on the daisy-chain connection. This 29

30 LTC683-1/LTC683-3 APPLICATIONS INFORMATION NEXT HIGHER GROUP OF 7 CELLS NEXT HIGHER GROUP OF 7 CELLS 1 V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 LTC683-1 C6 S6 1 C S C4 S4 C3 S3 C2 S2 C1 S1 V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 LTC683-3 C6 S6 C S C4 S4 C3 S3 C2 S2 C1 S1 C NEXT LOWER GROUP OF 7 CELLS NEXT LOWER GROUP OF 7 CELLS F13 Tabe 1. LTC683-1/LTC683-3 Faiure Mechanism Effect Anaysis Figure 13. Monitoring 7 Ces with the LTC683-1/LTC683-3 SCENARIO EFFECT DESIGN MITIGATION Ce input open-circuit (random). Power-up sequence at IC inputs. Camp diodes at each pin to V and (within IC) provide aternate power path. Ce input open-circuit (random). Differentia input votage overstress. Zener diodes across each ce votage input pair (within IC) imits stress. Disconnection of a harness between a group of battery ces and the IC (in a system of stacked groups). Loss of suppy connection to the IC. Separate power may be suppied by a oca suppy. Data ink disconnection between stacked LTC683 units. Ce-pack integrity, break between stacked units. Ce-pack integrity, break between stacked units. Ce-pack integrity, break within stacked unit. Ce-pack integrity, break within stacked unit. Break of "daisy-chain" communication (no stress to ICs). Communication wi be ost to devices above the disconnection. The devices beow the disconnection are sti abe to communicate and perform a functions, however, the poing feature is disabed. Daisy-chain votage reversa up to fu stack potentia during pack discharge. A units above the disconnection wi enter standby mode within 2 seconds of disconnect. Discharge switches are disabed in standby mode. Use series protection diodes with top-port I/O connections (RS7J for up to 6V). Use isoated data ink at bottommost data port. Daisy-chain positive overstress during charging. Add redundant current path ink. See Figure 14. Ce input reverse overstress during discharge. Ce input positive overstress during charge. Add parae Schottky diodes across each ce for oadpath redundancy. Diode and connections must hande fu operating current of stack, wi imit stress on IC. Add SCR across each ce for charge-path redundancy. SCR and connections must hande fu charging current of stack, wi imit stress on IC by seection of trigger Zener. 3

31 APPLICATIONS INFORMATION situation might occur in a moduar battery system during initia instaation or a service procedure. The daisy-chain ports are protected from the reverse potentia in this scenario by externa series high votage diodes required in the upper port data connections as shown in Figure 14. During the charging phase of operation, this faut woud ead to forward biasing of daisy-chain ESD camps that woud aso ead to part damage. An aternative connection to carry current during this scenario wi avoid this stress from being appied (Figure 14). PROTECT AGAINST BREAK HERE OPTIONAL REDUNDANT CURRENT PATH V LTC683-1 (NEXT HIGHER IN STACK) SDI SCKI CSBI Figure 14. Reverse-Votage Protection for the Daisy Chain (One Link Connection Shown) RSO7J 3 Interna Protection Diodes Each pin of the LTC683 has protection diodes to hep prevent damage to the interna device structures caused by externa appication of votages beyond the suppy rais as shown in Figure 1. The diodes shown are conventiona siicon diodes with a forward breakdown votage of.v. The unabeed Zener diode structures have a reversebreakdown characteristic which initiay breaks down at 12V then snaps back to a 7V camping potentia. The Zener diodes abeed Z CLAMP are higher votage devices with an initia reverse breakdown of 3V snapping back to 2V. The forward votage drop of a Zeners is.v. Refer to Figure 1 in the event of unpredictabe votage camping or current fow. Limiting the current fow at any pin to ±1mA wi prevent damage to the IC. SDO SDOI SCKO CSBO LTC683-1 (NEXT LOWER IN STACK) F14 4 V C12 6 S12 7 C11 8 S11 LTC683-1/LTC C1 Z CLAMP 1 S1 11 C9 12 S9 13 C8 14 S8 1 C7 16 S7 17 C6 Z CLAMP 18 S6 19 C 2 S 21 C4 22 S4 23 C3 24 S3 2 C2 26 S2 Z CLAMP 27 C1 28 S1 C 29 3 LTC683-3 Z CLAMP Z CLAMP Z CLAMP Z CLAMP Z CLAMP Z CLAMP NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 3 Figure 1. Interna Protection Diodes READING EXTERNAL TEMPERATURE PROBES SCKO SDOI CSBO V REG V REF V TEMP2 V TEMP1 CSBI SDO SDI SCKI V MODE GPIO2 GPIO1 WDTB TOS F1 The LTC683 incudes two channes of ADC input, V TEMP1 and V TEMP2, that are intended to monitor thermistors (tempco about 4%/ C generay) or diodes ( 2.2mV/ C typica) ocated within the ce array. Sensors can be powered directy from V REF as shown in Figure 16 (up to 6µA tota). 31

32 LTC683-1/LTC683-3 APPLICATIONS INFORMATION For sensors that require higher drive currents, a buffer op amp may be used as shown in Figure 17. Power for the sensor is actuay sourced indirecty from the V REG pin in this case. Probe oads up to about 1mA maximum are supported in this configuration. Since V REF is shutdown during the LTC683 ide and shutdown modes, the thermistor drive is aso shut off and thus power dissipation minimized. Since V REG remains aways on, the buffer op amp (LT6 shown) is seected for its utraow power consumption (12µA). LTC683-1 V REG V REF V TEMP2 V TEMP1 NC LT6 1k 1k NTC F17 1k 1k NTC Expanding Probe Count As shown Figure 18, a dua 4:1 mutipexer is used to expand the genera purpose V TEMP1 and V TEMP2 ADC inputs to accept 8 different probe signas. The channe is seected by setting the genera purpose digita outputs GPIO1 and GPIO2 and the resutant signas are buffered by sections of the LT64 micropower dua operationa ampifier. The probe excitation circuitry wi vary with probe type and is not shown here. Another method of mutipe sensor support is possibe without the use of any GPIO pins. If the sensors are PN diodes and severa used in parae, then the hottest diode wi produce the owest forward votage and effectivey estabish the input signa to the V TEMP input(s). The hottest diode wi therefore dominate the readout from the V TEMP inputs that the diodes are connected to. In this scenario, the specific ocation or distribution of heat is not known, but such information may not be important in practice. Figure 19 shows the basic concept. In any of the sensor configurations shown, a fu-scae cod readout woud be an indication of a faied open-sensor connection to the LTC683. LTC683-1 V REG V REF V TEMP2 V TEMP1 NC 1k 1k NTC 1k 1k NTC CPO2 GPO1 V REG V TEMP2 V TEMP1 Figure 17. Buffering V REF for Higher Current Sensors /2 LT64 7 1/2 LT Figure 18. Expanding Sensor Count with Mutipexing LTC683-1 V REG V REF V TEMP2 V TEMP1 NC Y Y2 Y Y3 Y1 INH V EE GND 74HC42 Figure 19. Using Diode Sensors as Hot Spot Detectors 2k V CC X2 X1 X X X3 A B 2k F F18 PROBE8 PROBE7 PROBE6 PROBE PROBE4 PROBE3 PROBE2 PROBE F16 Figure 16. Driving Thermistors Directy from V REF 32

33 APPLICATIONS INFORMATION ADDING CALIBRATION AND FULL-STACK MEASUREMENTS The genera purpose V TEMP ADC inputs may be used to digitize any signas from V to 4V with accuracy corresponding cosey with that of the ce 1 ADC input. One usefu signa to provide is a high accuracy votage reference, such as 3.3V from an LTC From periodic readings of this signa, the host software can provide correction of the LTC683 readings to improve the accuracy over that of the interna LTC683 reference and/or vaidate ADC operation. Figure 2 shows a means of seectivey powering an LTC from the battery stack, under the contro of the GPIO1 output of the LTC Since the operationa power of the reference IC woud add significant LTC683-1/LTC683-3 therma oading to the LTC683 if powered from V REG, an externa high votage NPN pass transistor is used to form a oca 4.4V (V be beow V REG ) from the battery stack. The GPIO1 signa contros a PMOS FET switch to activate the reference when caibration is to be performed. Since GPIO signas defaut to ogic high in shutdown, the reference wi automaticay turn off during ide periods. Another usefu signa is a measure of the tota stack potentia. This provides a redundant operationa measurement of the ces in the event of a mafunction in the norma acquisition process, or as a faster means of monitoring the entire stack potentia. Figure 21 shows how a resistive divider is used to derive a scaed representation of a fu ce group potentia. A MOSFET is used to disconnect TOP CELL POTETNTIAL CZT1 LTC683-1 GPIO1 38 V REG 34 V TEMP M Si231DS 1nF LTC SHDN GND V IN V OUT_F GND V OUT_S GND GND F2 Figure 2. Providing Measurement of Caibration Reference CELL GROUP WDTB V REG 499k 1M 2N72K V TEMP1 1 1/2 LT64 2 1nF k CELL GROUP F21 Figure 21. Using a V TEMP Input for Fu-Stack Readings 33

34 LTC683-1/LTC683-3 APPLICATIONS INFORMATION the resistive oading on the ce group when the IC enters standby mode (i.e., when WDTB goes ow). An LT64 micropower operationa ampifier section is shown for buffering the divider signa to preserve accuracy. This circuit has the virtue that it can be converted about four times more frequenty than the entire battery array, thus offering a higher sampe rate option at the expense of some precision/accuracy, reserving the high resoution ce readings for caibration and baancing data. PROVIDING HIGH SPEED ISOLATION OF THE SPI DATA PORT Isoation techniques that are capabe of supporting the 1Mbps data rate of the LTC683 require more power on the isoated (battery) side than can be furnished by the V REG output of the LTC683. To keep battery drain minima, this means that a DC/DC function must be impemented aong with a suitabe data isoation circuit, such as shown in Figure 22. A quad (3 1) data isoator Si8441AB-C-IS is used to provide non-gavanic SPI signa connections between a host microprocessor and an LTC683. An inexpensive isoated DC/DC converter provides power- ing of the isoator function competey from the host V power suppy. A quad three-state buffer is used to aow SPI inputs at the LTC683 to rise to ogic high eve when the isoator circuitry powers down, assuring the owest power consumption in the standby condition. The puups to V REG are seected to match the interna oading on V REG by ICs operating with a current mode SPI interface, thus baancing the current in a ces during operation. The additiona pu-up on the SDO ine (1k resistor and Schottky diode) is to improve rise time, in ower data-rate appications this may not be needed. SUPPLY DECOUPLING IF BATTERY-STACK POWERED As shown in Figure 23, the LTC683-3 can have fitering on both V and, so differentia bypassing to the ce group potentias is recommended. The Zener suppresses overvotages from reaching the IC suppy pins. A sma ferrite-bead inductor provides protection for the Zener, particuary from energetic ESD strikes. Since the LTC683-1 cannot have a series resistance to, additiona Schottky diodes are needed to prevent ESD-induced reverse-suppy (substrate) currents to fow. V_HOST SPI_CLOCK SPI_CHIPSELECT SPI_MASTEROUT SPI_MASTERIN GND_HOST 47pF 2.k 1Ω 1Ω 1Ω 1Ω 1 LTC IN1 V CC1 2 7 GND1 OUT1 3 6 IN2 V CC2 4 GND2 OUT2 Si8441AB-C-IS QUAD ISOLATOR V DD1 GND1 A1 A2 A3 A4 EN1 GND1 V DD2 GND2 B1 B2 B3 B4 EN2 GND nF PE BAT4S CMDSH /4 74ABT /4 74ABT /4 74ABT /4 74ABT126 1k 74ABT126 SUPPLY SHARED WITH ISOLATOR V DD2 and GND2 4.22k 4.22k 4.22k 4.22k F22 V REG SCKI CSB1 SCI SDO 1.k Figure 22. Providing an Isoated High Speed Data Interface 34

35 LTC683-1/LTC683-3 APPLICATIONS INFORMATION CELLGROUP BLM31PG33SN1L 1Ω V V TP61K CMHZ26B BAT46W CELLGROUP LTC683-1 Configuration F23 1nF LTC683-3 IC #3 C12 DZ1 1V 1M CELLGROUP BLM31PG33SN1L 1Ω V C D1 CELLGROUP CMHZ26B 1nF 1Ω LTC683-3 Configuration Figure 23. Suppy Decouping V C12 LTC683-3 IC #2 TP61K DZ2 1V 1M ADVANTAGES OF KELVIN CONNECTION ON C The trace resistance can cause an observabe votage drop between the negative end of the bottom battery ce and pin of LTC683. This votage drop wi add to the measurement error of the bottom ce votage for LTC The LTC683-3 separates C from, aowing Kevin connection on C as shown in Figure 24. Any votage drop on trace wi not affect the bottom ce votage measurement. The Kevin connection wi aso aow RC fitering on as shown in Figure 23. BATTERY STACK R I SUPPLY C1 LTC683-1 BATTERY STACK I SUPPLY Figure 24. Kevin Connection on C Improving Bottom Ce Votage Measurement Accuracy R LTC683-3 C1 C F24 HARDWARE SHUTDOWN To competey shut down the LTC683 a PMOS switch can be connected to V, or V can be driven from an isoated power suppy. Figure 2 shows an exampe of a switched LTC683-3 IC #1 C V C12 C TP61K DZ3 1V DZ4 1.8V DZ1, DZ2, DZ3: MMSZ24B DZ4: MMSZ4678T1 ALL NPN: MMBTA42 ALL PN: RS7J V. The breakdown votage of DZ4 is about 1.8V. If SHDN < 1.8V, no current wi fow through the stacked MMBTA42s and the 1M resistors. TP61Ks wi be competey shut off. If SHDN > 2.V, M7 wi be turned on and a TP61Ks wi be turned on. Figure 26 is an exampe of isoated power suppy. This circuit provides power for two LTC683s used to monitor 24 series connected battery ces. When V is removed, the LTC683s wi draw 1nA from the battery ces. Note that use of an externa V suppy wi not protect daisy-chain SPI operation at ow tota stack potentias (beow V). D2 1M k SHDN F2 Figure 2. Hardware Shutdown Circuit Reduces Tota Suppy Current of LTC683 to Less Than 1nA 3

36 LTC683-1/LTC683-3 APPLICATIONS INFORMATION INPUT V 9mA TYP 1 16 BAT4S BAT4S BAT4S BAT4S 1k IMC121ER EACH OUTPUT 61V TYP V1 V GND 1k LTC IN1 V CC1 GND1 OUT1 IN2 V CC2 GND2 OUT2 22pF 33.2k EPF8119S BAT4S BAT4S BAT4S BAT4S 1V 1k IMC121ER 1V CMHZ26B COM1 V2 CMHZ26B F26 COM2 Figure 26. LTC683 Powered by Isoated Power Suppies PCB LAYOUT CONSIDERATIONS The V REG and V REF pins shoud be bypassed with a capacitor for best performance. The LTC683 is capabe of operation with as much as V between V and. Care shoud be taken on the PCB ayout to maintain physica separation of traces at different potentias. The pinout of the LTC683-1 and LTC683-3 were chosen to faciitate this physica separation. There is no more than.v between any two adjacent pins. The package body is used to separate the highest votage (e. g., 43.2V) from the owest votage (V). As an exampe, Figure 27 shows the DC votage on each pin with respect to when tweve 3.6V battery ces are connected to the LTC ADVANTAGES OF DELTA-SIGMA ADCS The LTC683 empoys a deta-sigma anaog-to-digita converter for votage measurement. The architecture of deta sigma converters can vary consideraby, but the common characteristic is that the input is samped many times over the course of a conversion and then fitered or averaged to produce the digita output code. In contrast, a SAR converter takes a singe snapshot of the input votage and then performs the conversion on this singe sampe. For measurements in a noisy environment, a deta sigma converter provides distinct advantages over a SAR converter. 42.V 42.V 42.V 43.2V 43.2V 43.2V 39.6V 39.6V 36V 36V 32.4V 32.4V 28.8V 28.8V 2.2V 2.2V V 18V 14.4V 14.4V CSBO SDOI SCKO V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C S C4 S4 LTC683-3 CSBI SDO SDI SCKI V MODE GPIO2 GPIO1 WDTB TOS V REG V REF V TEMP2 V TEMP1 NC C S1 C1 S2 C2 S3 C F27 V TO.V V TO.V V TO.V V TO.V V TO.V V TO.V V TO.V V TO.V V TO.V V 3.1V 1.V 1.V V V V 3.6V 3.6V 7.2V 7.2V 1.8V 1.8V Figure 27. Typica Pin Votages for Tweve 3.6V Ces Whie SAR converters can have high sampe rates, the fupower bandwidth of a SAR converter is often greater than 1MHz, which means the converter is sensitive to noise out to this frequency. And many SAR converters have much higher bandwidths up to MHz and beyond. It is possibe to fiter the input, but if the converter is mutipexed to measure severa input channes a separate fiter wi be 36

37 APPLICATIONS INFORMATION required for each channe. A ow frequency fiter cannot reside between a mutipexer and an ADC and achieve a high scan rate across mutipe channes. Another consequence of fitering a SAR ADC is that any noise reduction gained by fitering the input cances the benefit of having a high sampe rate in the first pace, since the fiter wi take many conversion cyces to sette. For a given sampe rate, a deta-sigma converter can achieve exceent noise rejection whie setting competey in a singe conversion something that a fitered SAR converter cannot do. Noise rejection is particuary important in high votage switching controers, where switching noise wi invariaby be present in the measured votage. Other advantages of deta-sigma converters are that they are inherenty monotonic, meaning they have no missing codes, and they have exceent DC specifications. Converter Detais The LTC683 s ADC has a second order deta-sigma moduator foowed by a SINC2, finite impuse response (FIR) digita fiter. The front-end sampe rate is 12ksps, which greaty reduces input fitering requirements. A simpe 16kHz, 1-poe fiter composed of a 1Ω resistor and a. capacitor at each input wi provide adequate fitering for most appications. These component vaues wi not degrade the DC accuracy of the ADC. Each conversion consists of two phases an autozero phase and a measurement phase. The ADC is autozeroed at each conversion, greaty improving CMRR. The second haf of the conversion is the actua measurement. Noise Rejection Figure 28 shows the frequency response of the ADC. The ro-off foows a SINC2 response, with the first notch at 4kHz. Aso shown is the response of a 1-poe, 8Hz fiter (187µs time constant) which has the same integrated response to wideband noise as the LTC683 s ADC, which FILTER GAIN (db) 1 LTC683-1/LTC k 1k FREQUENCY (Hz) 1k F28 Figure 28. Noise Fitering of the LTC683 ADC is about 13Hz. This means that if wideband noise is appied to the LTC683 input, the increase in noise seen at the digita output wi be the same as an ADC with a wide bandwidth (such as a SAR) preceded by a perfect 13Hz brick wa owpass fiter. Thus if an anaog fiter is paced in front of a SAR converter to achieve the same noise rejection as the LTC683 ADC, the SAR wi have a sower response to input signas. For exampe, a step input appied to the input of the 8Hz fiter wi take 1.ms to sette to 12 bits of precision, whie the LTC683 ADC settes in a singe 1ms conversion cyce. This aso means that very high sampe rates do not provide any additiona information because the anaog fiter imits the frequency response. Whie higher order active fiters may provide some improvement, their compexity makes them impractica for high channe count measurements as a singe fiter woud be required for each input. Aso note that the SINC2 response has a 2nd order rooff enveope, providing an additiona benefit over a singe poe anaog fiter. 37

38 LTC683-1/LTC683-3 PACKAGE DESCRIPTION G Package 44-Lead Pastic SSOP (.3mm) (Reference LTC DWG # Rev Ø) 1.2 ± * ( ) ( ).2 ±. RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED. BSC * ( ) (.6.73) 2. (.79) MAX PARTING LINE.1.2 (.4.1)..9** (.22.37) 1.2 (.492) REF 8 NOTE: 1.DRAWING IS NOT A JEDEC OUTLINE 2. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 3. DIMENSIONS ARE IN (INCHES) 4. DRAWING NOT TO SCALE. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN.8mm AT SEATING PLANE. (.1968) BSC.2.3 (.8.12) TYP * DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED.1mm PER SIDE ** LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS DO NOT EXCEED.13mm PER SIDE. (.2) MIN G44 SSOP 67 REV Ø SEATING PLANE 38

39 LTC683-1/LTC683-3 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 8/12 Carification to UV/OV Operation 14, 1 Correction to 12-Ce Li-Ion Appication Circuit 4 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 39

40 LTC683-1/LTC683-3 TYPICAL APPLICATION CELL12 IMC121ER1K MMZ26B Cascadabe 12-Ce Li-Ion Battery Monitor BAT46W BAT46W 1nF 1Ω REPEAT INPUT CIRCUITS FOR CELL3 TO CELL12 CELL2 CELL1 CASCADED SPI PORT TO NEXT LTC683-1 C12FILTER DC12 C11FILTER C1FILTER C9FILTER C8FILTER C7FILTER C6FILTER CFILTER C4FILTER DC11 DC1 DC9 DC8 DC7 DC6 DC DC4 C3FILTER DC3 33Ω 33Ω RQJ33PGDQA 47Ω RQJ33PGDQA 47Ω CSBI SDI SCKI 1 44 CSBO CSBI 2 43 SDOI SDO 3 42 SCKO SDI 4 V 41 SCKI 4 C12 V MODE M S12 GPIO M C11 GPIO M S11 WDTB 9 36 C1 LTC683-1 NC 1 3 S1 TOS C9 V REG S9 V REF C8 V TEMP S8 V TEMP1 1 3 C7 NC 16 S C6 S S6 C C S2 2 2 S C C4 S S4 C3 1Ω 1Ω 1nF 3.3k 1nF 3.3k C2FILTER PDZ7.B PDZ7.B DC2 C1FILTER DC1 1M 1M /2 LT64 1M CSBI SDO* SDI SCKI 4 8 1/2 LT64 4 MAIN SPI PORT TO HOST µp OR NEXT LTC683-1 *REQUIRES 1k PULL-UP RESISTOR AT HOST DEVICE (SIGNAL NOT USED FOR INTER-IC COMMUNCATION) 7 1 1k 1k 1Ω 1nF 1Ω 1nF TA2 NTC2 NTC1 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC681 Independent Mutice Battery Stack Faut Monitor Monitors Up to 12 Series-Connected Battery Ces for Undervotage or Overvotage. Companion to LTC682 and LTC683 Famiy LTC682-1 LTC682-2 LTC683-2/ LTC683-4 Mutice Battery Stack Monitor with Parae Addressed Seria Interface Mutice Battery Stack Monitor with an Individuay Addressabe Seria Interface Mutice Battery Stack Monitor with an Individuay Addressabe Seria Interface Functionay Equivaent to the LTC683-1 and LTC683-3, Pin Compatibe with the LTC683-1 Functionay Equivaent to LTC683-2/LTC683-4, Pin Compatibe with the LTC683-2 Functionaity Equivaent to LTC683-1/LTC683-3, Aows for Parae Communication Battery Stack Topoogies 4 LT 812 REV A PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION 211