LTC2630 Single 12-/10-/8-Bit Rail-to- Rail DACs with 10ppm/ C Reference in SC70 Description. Features. Applications. Block Diagram

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1 Features n Integrated Precision Reference 2.5V Fu Scae 1ppm/ C (LTC263-L) 4.96V Fu Scae 1ppm/ C (LTC263-H) n Maximum INL Error: 1 LSB (LTC263A-12) n Low Noise:.7mV P-P,.1Hz to 2kHz n Guaranteed Monotonic over Temperature n Seectabe Interna Reference or Suppy as Reference n 2.7V to 5.5V Suppy Range (LTC263-L) n Low Power Operation: 18µA at 3V n Power Down to 1.8µA Maximum (C and I Grades) n Power-on Reset to Zero or Mid-Scae Options n SPI Seria Interface n Doube-Buffered Data Latches n Tiny 6-Lead SC7 Package Appications n Mobie Communications n Process Contro and Industria Automation n Automatic Test Equipment n Portabe Equipment n Automotive Bock Diagram LTC263 Singe 12-/1-/8-Bit Rai-to- Rai DACs with 1ppm/ C Reference in SC7 Description The LTC 263 is a famiy of 12-, 1-, and 8-bit votageoutput DACs with an integrated, high-accuracy, ow-drift reference in a 6-ead SC7 package. It has a rai-to-rai output buffer and is guaranteed monotonic. The LTC263-L has a fu-scae output of 2.5V, and operates from a singe 2.7V to 5.5V suppy. The LTC263-H has a fu-scae output of 4.96V, and operates from a 4.5V to 5.5V suppy. Each DAC can aso operate in suppy as reference mode, which sets the fu-scae output to the suppy votage. The parts use a simpe SPI/MICROWIRE compatibe 3-wire seria interface which operates at cock rates up to 5MHz. The LTC263 incorporates a power-on reset circuit. Options are avaiabe for reset to zero or reset to mid-scae after power-up. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Protected by U.S. Patents, incuding , , , and SDI INTERNAL REFERENCE V CC Integra Noninearity (LTC263A-LZ12) 1. VCC = 3V V FS = 2.5V CONTROL DECODE LOGIC RESISTOR DIVIDER.5 SCK 24-BIT SHIFT REGISTER INL (LSB) INPUT REGISTER DAC REGISTER DACREF DAC GND V OUT CODE 263 TA BD 263ff 1

2 LTC263 Absoute Maximum Ratings (Notes 1, 2) Suppy Votage (V CC )....3V to 6V, SCK, SDI....3V to 6V V OUT....3V to min(v CC +.3V, 6V) Operating Temperature Range LTC263C... C to 7 C LTC263I... 4 C to 85 C LTC263H (Note 3)... 4 C to 125 C Maximum Junction Temperature C Storage Temperature Range C to 15 C Lead Temperature (Sodering, 1 sec)...3 C Pin Configuration 1 SCK 2 SDI 3 TOP VIEW 6 V OUT 5 GND 4 V CC SC6 PACKAGE 6-LEAD PLASTIC SC7 T JMAX = 15 C (Note 6), θ JA = 3 C/W Order Information LTC263 A C SC6 L M 12 #TRM PBF LEAD FREE DESIGNATOR TAPE AND REEL TR = 2,5-Piece Tape and Ree TRM = 5-Piece Tape and Ree RESOLUTION 12 = 12-Bit 1 = 1-Bit 8 = 8-Bit POWER-ON RESET M = Reset to Mid-Scae Z = Reset to Zero-Scae FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE L = 2.5V H = 4.96V PACKAGE TYPE SC6 = 6-Lead SC7 TEMPERATURE GRADE C = Commercia Temperature Range ( C to 7 C) I = Industria Temperature Range ( 4 C to 85 C) H = Automotive Temperature Range ( 4 C to 125 C) ELECTRICAL GRADE (OPTIONAL) A = ±1 LSB Maximum INL (12-Bit) PRODUCT PART NUMBER Consut LTC Marketing for information on non-standard ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: ff

3 LTC263 Product Seection Guide PART NUMBER PART MARKING* V FS WITH INTERNAL REFERENCE POWER-ON RESET TO CODE RESOLUTION V CC MAXIMUM INL LTC263A-LM12 LTC263A-LZ12 LTC263A-HM12 LTC263A-HZ12 LCZB LCSB LCWR LCZC 2.5V (495/496) 2.5V (495/496) 4.96V (495/496) 4.96V (495/496) Mid-Scae Zero Mid-Scae Zero 12-Bit 12-Bit 12-Bit 12-Bit 2.7V 5.5V 2.7V 5.5V 4.5V 5.5V 4.5V 5.5V ±1LSB ±1LSB ±1LSB ±1LSB LTC263-LM12 LTC263-LM1 LTC263-LM8 LCZB LCZF LCYW 2.5V (495/496) 2.5V (123/124) 2.5V (255/256) Mid-Scae Mid-Scae Mid-Scae 12-Bit 1-Bit 8-Bit 2.7V 5.5V 2.7V 5.5V 2.7V 5.5V ±2LSB ±1LSB ±.5LSB LTC263-LZ12 LTC263-LZ1 LTC263-LZ8 LCSB LCZD LCYV 2.5V (495/496) 2.5V (123/124) 2.5V (255/256) Zero Zero Zero 12-Bit 1-Bit 8-Bit 2.7V 5.5V 2.7V 5.5V 2.7V 5.5V ±2LSB ±1LSB ±.5LSB LTC263-HM12 LTC263-HM1 LTC263-HM8 LCWR LCZH LCYY 4.96V (495/496) 4.96V (123/124) 4.96V (255/256) Mid-Scae Mid-Scae Mid-Scae 12-Bit 1-Bit 8-Bit 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V ±2LSB ±1LSB ±.5LSB LTC263-HZ12 LTC263-HZ1 LTC263-HZ8 LCZC LCZG LCYX 4.96V (495/496) 4.96V (123/124) 4.96V (255/256) Zero Zero Zero 12-Bit 1-Bit 8-Bit 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V ±2LSB ±1LSB ±.5LSB *The temperature grade is identified by a abe on the shipping container. 263ff 3

4 LTC263 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V CC = 2.7V to 5.5V, V OUT unoaded uness otherwise specified. LTC263-LM12/-LM1/-LM8/-LZ12/-LZ1/-LZ8, LTC263A-LM12/-LZ12 (V FS = 2.5V) SYMBOL PARAMETER CONDITIONS LTC263-8 LTC263-1 LTC LTC263A-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX DC Performance Resoution Bits Monotonicity V CC = 3V, Interna Ref. (Note 4) Bits DNL Differentia Noninearity V CC = 3V, Interna Ref. (Note 4) ±.5 ±.5 ±1 ±1 LSB INL Integra Noninearity V CC = 3V, Interna Ref. (Note 4) ±.5 ±.5 ±.2 ±1 ±1 ±2 ±.5 ±1 LSB ZSE Zero Scae Error V CC = 3V, Interna Ref., Code = mv V OS Offset Error V CC = 3V, Interna Ref. (Note 5) ±.5 ±5 ±.5 ±5 ±.5 ±5 ±.5 ±5 mv V OSTC V OS Temperature V CC = 3V, Interna Ref. (Note 5) ±1 ±1 ±1 ±1 µv/ C Coefficient FSE Fu Scae Error V CC = 3V, Interna Ref. ±.2 ±.8 ±.2 ±.8 ±.2 ±.8 ±.2 ±.8 %FSR V FSTC Fu Scae Votage Temperature Coefficient V CC = 3V, Interna Ref. (Note 1) C-Grade I-Grade H-Grade Load Reguation Interna Ref., Mid-Scae, V CC = 3V ±1%, 5mA I OUT 5mA V CC = 5V ±1%, 1mA I OUT 1mA R OUT DC Output Impedance Interna Ref., Mid-Scae, V CC = 3V ±1%, 5mA I OUT 5mA V CC = 5V ±1%, 1mA I OUT 1mA ±1 ±1 ± ±1 ±1 ± ±1 ±1 ± ±1 ±1 ± UNITS ppm/ C ppm/ C ppm/ C LSB/mA LSB/mA Ω Ω SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OUT DAC Output Span Suppy as Reference Interna Reference V to V CC V to 2.5 PSR Power Suppy Rejection V CC = 3V ±1% or 5V ±1% 8 db I SC Short Circuit Output Current (Note 6) Sinking Sourcing Power Suppy V FS = V CC = 5.5V Zero Scae; V OUT Shorted to V CC Fu Scae; V OUT Shorted to GND V CC Power Suppy Votage For Specified Performance V I CC Suppy Current (Note 7) V CC = 3V, Suppy as Reference V CC = 3V, Interna Reference V CC = 5V, Suppy as Reference V CC = 5V, Interna Reference I SD Suppy Current in Power-Down Mode (Note 7) Digita I/O V CC = 5V, C-Grade, I-Grade V CC = 5V, H-Grade V IH Digita Input High Votage V CC = 3.6V to 5.5V V CC = 2.7V to 3.6V V IL Digita Input Low Votage V CC = 4.5V to 5.5V V CC = 2.7V to 4.5V I LK Digita Input Leakage V IN = GND to V CC ±1 µa C IN Digita Input Capacitance (Note 8) 2.5 pf V V ma ma µa µa µa µa µa µa V V V V 4 263ff

5 LTC263 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V CC = 2.7V to 5.5V, V OUT unoaded uness otherwise specified. LTC263-LM12/-LM1/-LM8/-LZ12/-LZ1/-LZ8, LTC263A-LM12/-LZ12 (V FS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AC Performance t S Setting Time V CC = 3V (Note 9) ±.39% (±1LSB at 8 Bits) ±.98% (±1LSB at 1 Bits) ±.24% (±1LSB at 12 Bits) µs µs µs Votage Output Sew Rate 1. V/µs Capacitive Load Driving 5 pf Gitch Impuse At Mid-Scae Transition 2 nv s e n Output Votage Noise Density At f = 1kHz, Suppy as Reference At f = 1kHz, Suppy as Reference At f = 1kHz, Interna Reference At f = 1kHz, Interna Reference Output Votage Noise.1Hz to 1Hz, Suppy as Reference.1Hz to 1Hz, Interna Reference.1Hz to 2kHz, Suppy as Reference.1Hz to 2kHz, Interna Reference nv/ Hz nv/ Hz nv/ Hz nv/ Hz µv P-P µv P-P µv P-P µv P-P Timing Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V CC = 2.7V to 5.5V. (See Figure 1) (Note 8). LTC263-LM12/-LM1/-LM8/-LZ12/-LZ1/-LZ8, LTC263A-LM12/-LZ12 (V FS = 2.5V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t 1 SDI Vaid to SCK Setup 4 ns t 2 SDI Vaid to SCK Hod 4 ns t 3 SCK High Time 9 ns t 4 SCK Low Time 9 ns t 5 Puse width 1 ns t 6 SCK High to High 7 ns t 7 Low to SCK High 7 ns t 1 High to SCK Positive Edge 7 ns SCK Frequency 5% Duty Cyce 5 MHz 263ff 5

6 LTC263 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V CC = 4.5V to 5.5V, V OUT unoaded uness otherwise specified. LTC263-HM12/-HM1/-HM8/-HZ12/-HZ1/-HZ8, LTC263A-HM12/-HZ12 (V FS = 4.96V) SYMBOL PARAMETER CONDITIONS LTC263-8 LTC263-1 LTC LTC263A-12 MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX DC Performance Resoution Bits Monotonicity V CC = 5V, Interna Ref. (Note 4) Bits DNL Differentia Noninearity V CC = 5V, Interna Ref. (Note 4) ±.5 ±.5 ±1 ±1 LSB INL Integra Noninearity V CC = 5V, Interna Ref. (Note 4) ±.5 ±.5 ±.2 ±1 ±1 ±2 ±.5 ±1 LSB ZSE Zero Scae Error V CC = 5V, Interna Ref., Code = mv V OS Offset Error V CC = 5V, Interna Ref. (Note 5) ±.5 ±5 ±.5 ±5 ±.5 ±5 ±.5 ±5 mv V OSTC V OS Temperature V CC = 5V, Interna Ref. (Note 5) ±1 ±1 ±1 ±1 µv/ C Coefficient FSE Fu Scae Error V CC = 5V, Interna Ref. ±.2 ±.8 ±.2 ±.8 ±.2 ±.8 ±.2 ±.8 %FSR V FSTC Fu Scae Votage Temperature Coefficient V CC = 5V, Interna Ref. (Note 1) C-Grade I-Grade H-Grade ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 ±1 UNITS ppm/ C ppm/ C ppm/ C Load Reguation V CC = 5V ±1%, Interna Ref., Mid-Scae, 1mA I OUT 1mA LSB/ ma R OUT DC Output Impedance V CC = 5V ±1%, Interna Ref., Mid-Scae, 1mA I OUT 1mA Ω SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V OUT DAC Output Span Suppy as Reference Interna Reference V to V CC V to 4.96 PSR Power Suppy Rejection V CC = 5V ±1% 8 db I SC Short Circuit Output Current (Note 6) Sinking Sourcing Power Suppy V FS = V CC = 5.5V Zero Scae; V OUT Shorted to V CC Fu Scae; V OUT Shorted to GND V CC Power Suppy Votage For Specified Performance V I CC Suppy Current (Note 7) V CC = 5V, Suppy as Reference V CC = 5V, Interna Reference I SD Suppy Current in Power-Down Mode (Note 7) Digita I/O V CC = 5V, C-Grade, I-Grade V CC = 5V, H-Grade V IH Digita Input High Votage 2.4 V V IL Digita Input Low Votage.8 V I LK Digita Input Leakage V IN = GND to V CC ±1 µa C IN Digita Input Capacitance (Note 8) 2.5 pf V V ma ma µa µa µa µa 6 263ff

7 LTC263 Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V CC = 4.5V to 5.5V, V OUT unoaded uness otherwise specified. LTC263-HM12/-HM1/-HM8/-HZ12/-HZ1/-HZ8, LTC263A-HM12/-HZ12 (V FS = 4.96V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS AC Performance t S Setting Time V CC = 5V (Note 9) ±.39% (±1LSB at 8 Bits) ±.98% (±1LSB at 1 Bits) ±.24% (±1LSB at 12 Bits) µs µs µs Votage Output Sew Rate 1. V/µs Capacitive Load Driving 5 pf Gitch Impuse At Mid-Scae Transition 2.4 nv s e n Output Votage Noise Density At f = 1kHz, Suppy as Reference At f = 1kHz, Suppy as Reference At f = 1kHz, Interna Reference At f = 1kHz, Interna Reference Output Votage Noise.1Hz to 1Hz, Suppy as Reference.1Hz to 1Hz, Interna Reference.1Hz to 2kHz, Suppy as Reference.1Hz to 2kHz, Interna Reference nv/ Hz nv/ Hz nv/ Hz nv/ Hz µv P-P µv P-P µv P-P µv P-P Timing Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V CC = 4.5V to 5.5V. (See Figure 1) (Note 8). LTC263-HM12/-HM1/-HM8/-HZ12/-HZ1/-HZ8, LTC263A-HM12/-HZ12 (V FS = 4.96V) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t 1 SDI Vaid to SCK Setup 4 ns t 2 SDI Vaid to SCK Hod 4 ns t 3 SCK High Time 9 ns t 4 SCK Low Time 9 ns t 5 Puse width 1 ns t 6 SCK High to High 7 ns t 7 Low to SCK High 7 ns t 1 High to SCK Positive Edge 7 ns SCK Frequency 5% Duty Cyce 5 MHz Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: A votages are with respect to GND. Note 3: High temperatures degrade operating ifetimes. Operating ifetime is derated at temperatures greater than 15 C. Note 4: Linearity and monotonicity are defined from code k L to code 2 N 1, where N is the resoution and k L is given by k L =.16 (2 N / V FS ), rounded to the nearest whoe code. For V FS = 2.5V and N = 12, k L = 26 and inearity is defined from code 26 to code 4,95. For V FS = 4.96V and N = 12, k L = 16 and inearity is defined from code 16 to code 4,95. Note 5: Inferred from measurement at code 16 (LTC263-12), code 4 (LTC263-1) or code 1 (LTC263-8). Note 6: This IC incudes current imiting that is intended to protect the device during momentary overoad conditions. Junction temperature can exceed the rated maximum during current imiting. Continuous operation above the specified maximum operating junction temperature may impair device reiabiity. Note 7: Digita inputs at V or V CC. Note 8: Guaranteed by design and not production tested. Note 9: Interna Reference mode. DAC is stepped 1/4 scae to 3/4 scae and 3/4 scae to 1/4 scae. Load is 2kW in parae with 1pF to GND. Note 1: Temperature coefficient is cacuated by dividing the maximum change in output votage by the specified temperature range. 263ff 7

8 LTC263 Typica Performance Characteristics LTC263-LM12/-LZ12 (V FS = 2.5V) 1. Integra Noninearity (INL) V CC = 3V 1. Differentia Noninearity (DNL) V CC = 3V.5.5 INL (LSB) DNL (LSB) CODE CODE G1 263 G2 1. INL vs Temperature V CC = 3V 1. DNL vs Temperature V CC = 3V 2.52 Fu-Scae Output Votage vs Temperature V CC = 3V INL (LSB).5.5 INL (POS) INL (NEG) DNL (LSB).5.5 DNL (POS) DNL (NEG) FS OUTPUT VOLTAGE (V) TEMPERATURE ( C) TEMPERATURE ( C) TEMPERATURE ( C) G3 263 G4 263 G5 Setting to ±1LSB Setting to ±1LSB 2V/DIV V OUT 1LSB/DIV 3/4 SCALE TO 1/4 SCALE STEP V CC = 3V, V FS = 2.5V R L = 2k, C L = 1pF AVERAGE OF 256 EVENTS 4.4µs 3.6µs V OUT 1LSB/DIV 1/4 SCALE TO 3/4 SCALE STEP V CC = 3V, V FS = 2.5V R L = 2k, C L = 1pF AVERAGE OF 256 EVENTS 2V/DIV 2µs/DIV 2µs/DIV 263 G7 263 G ff

9 Typica Performance Characteristics LTC263-HM12/-HZ12 (V FS = 4.96V) Integra Noninearity (INL) 1. V CC = 5V Differentia Noninearity (DNL) 1. V CC = 5V LTC INL (LSB) DNL (LSB) CODE CODE G8 263 G9 1. INL vs Temperature V CC = 5V 1. DNL vs Temperature V CC = 5V Fu-Scae Output Votage vs Temperature V CC = 5V INL (LSB).5.5 INL (POS) INL (NEG) DNL (LSB).5.5 DNL (POS) DNL (NEG) FS OUTPUT VOLTAGE (V) TEMPERATURE ( C) TEMPERATURE ( C) TEMPERATURE ( C) G1 263 G G12 Setting to ±1LSB Setting to ±1LSB 2V/DIV V OUT 1LSB/DIV 4.8µs V OUT 1LSB/DIV 4.µs 1/4 SCALE TO 3/4 SCALE STEP V CC = 5V, V FS = 4.96V R L = 2k, C L = 1pF AVERAGE OF 256 EVENTS 2V/DIV 1/4 SCALE TO 3/4 SCALE STEP V CC = 5V, V FS = 4.96V R L = 2k, C L = 1pF AVERAGE OF 256 EVENTS 2µs/DIV 2µs/DIV 263 G G13 263ff 9

10 LTC263 Typica Performance Characteristics LTC Integra Noninearity (INL) V CC = 5V V FS = 4.96V 1..5 Differentia Noninearity (DNL) V CC = 5V V FS = 4.96V INL (LSB) DNL (LSB) CODE CODE 123 LTC G G Integra Noninearity (INL) V CC = 3V V FS = 2.5V.5.25 Differentia Noninearity (DNL) V CC = 3V V FS = 2.5V INL (LSB) DNL (LSB) CODE CODE 255 LTC G G18 ΔV OUT (mv) Load Reguation V CC = 5V (LTC263-H) V CC = 5V (LTC263-L) V CC = 3V (LTC263-L) 6 8 INTERNAL REF. CODE = MIDSCALE I OUT (ma) V OUT (V) Current Limiting V CC = 5V (LTC263-H) V CC = 5V (LTC263-L) V CC = 3V (LTC263-L).15 INTERNAL REF. CODE = MIDSCALE I OUT (ma) OFFSET ERROR (mv) Offset Error vs Temperature TEMPERATURE ( C) 263 G G2 263 G ff

11 Typica Performance Characteristics LTC263 LTC263 Large-Signa Response Mid-Scae-Gitch Impuse INTERNAL REF Power-On Reset Gitch LTC263-L 5V/DIV V CC 2V/DIV.5V/DIV LTC263-H12, V CC = 5V: 2.4nV-s TYP V FS = V CC = 5V 1/4 SCALE TO 3/4 SCALE V OUT 5mV/DIV LTC263-L12, V CC = 3V: 2.nV-s TYP V OUT 2mV/DIV ZERO-SCALE 2µs/DIV 2µs/DIV 2µs/DIV 263 G G G24 V OUT (V) Headroom at Rais vs Output Current 5V SOURCING 3V (LTC263-L) SOURCING 3V (LTC263-L) SINKING 5V SINKING NOISE VOLTAGE (nv/ Hz) Noise Votage vs Frequency CODE = MIDSCALE LTC263-H (V CC = 5V) LTC263-L (V CC = 4V) 1µV/DIV.1Hz to 1Hz Votage Noise V CC = 4V, V FS = 2.5V CODE = MIDSCALE I OUT (ma) 1 1k 1k 1k FREQUENCY (Hz) 1M 1s/DIV 263 G G G26 2V/DIV Exiting Power-Down to Mid-Scae 1..8 Suppy Current vs Logic Votage SWEEP SCK, SDI, BETWEEN V AND V CC V OUT.5V/DIV I CC (ma) V CC = 3V (LTC263-L) V CC = 5V 4µs/DIV LTC263-H 263 G LOGIC VOLTAGE (V) 263 G29 263ff 11

12 LTC263 Pin Functions (Pin 1): Seria Interface Chip Seect/Load Input. When is ow, SCK is enabed for shifting data on SDI into the register. When is taken high, SCK is disabed and the specified command (see Tabe 1) is executed. SCK (Pin 2): Seria Interface Cock Input. CMOS and TTL compatibe. SDI (Pin 3): Seria Interface Data Input. Data on SDI is cocked into the DAC on the rising edge of SCK. The LTC263 accepts input word engths of either 24 or 32 bits. V CC (Pin 4): Suppy Votage Input. 2.7V V CC 5.5V (LTC263-L) or 4.5V V CC 5.5V (LTC263-H). Aso used as the reference input when the part is programmed to operate in suppy as reference mode. Bypass to GND with a.1µf capacitor. GND (Pin 5): Ground. V OUT (Pin 6): DAC Anaog Votage Output. Bock Diagram INTERNAL REFERENCE V CC SDI CONTROL DECODE LOGIC RESISTOR DIVIDER SCK 24-BIT SHIFT REGISTER DACREF INPUT REGISTER DAC REGISTER DAC V OUT GND 263 BD ff

13 Timing Diagram LTC263 t 1 t 2 t 3 t 4 t 6 SCK t 1 SDI t 5 t F1 Figure 1. Seria Interface Timing Operation The LTC263 is a famiy of singe votage output DACs in 6-ead SC7 packages. Each DAC can operate rai-to-rai referenced to the input suppy, or with its fu-scae votage set by an integrated reference. Tweve combinations of accuracy (12-, 1-, and 8-bit), power-on reset vaue (zero or mid-scae), and fu-scae votage (2.5V or 4.96V) are avaiabe. The LTC263 is controed using a 3-wire SPI/ MICROWIRE compatibe interface. Power-On Reset The LTC263-HZ/-LZ cear the output to zero scae when power is first appied, making system initiaization consistent and repeatabe. For some appications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC263 contains circuitry to reduce the power-on gitch: the anaog output typicay rises ess than 5mV above zero scae during power on if the power suppy is ramped to 5V in 1ms or more. In genera, the gitch ampitude decreases as the power suppy ramp time is increased. See Power-On Reset Gitch in the Typica Performance Characteristics section. The LTC263-HM/-LM provide an aternative reset, setting the output to mid-scae when power is first appied. Transfer Function The digita-to-anaog transfer function is V OUT(IDEAL) = k V REF 2 N where k is the decima equivaent of the binary DAC input code, N is the resoution, and V REF is either 2.5V (LTC263-L) or 4.96V (LTC263-H) in interna reference mode, and V CC in Suppy as reference mode. Tabe 1. Command Codes Command* C3 C2 C1 C Write to Input Register 1 Update (Power up) DAC Register 1 1 Write to and Update (Power up) DAC Register 1 Power down 1 1 Seect Interna Reference (Power-on Reset Defaut) Seect Suppy as Reference (V REF = V CC ) *Command codes not shown are reserved and shoud not be used. 263ff 13

14 LTC263 OPERATION INPUT WORD (LTC263-12) COMMAND 4 DON'T-CARE BITS DATA (12 BITS + 4 DON'T-CARE BITS) C3 C2 C1 C X X X X D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X X X MSB LSB INPUT WORD (LTC263-1) COMMAND 4 DON'T-CARE BITS DATA (1 BITS + 6 DON'T-CARE BITS) C3 C2 C1 C X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X X X X X MSB LSB INPUT WORD (LTC263-8) COMMAND 4 DON'T-CARE BITS DATA (8 BITS + 8 DON'T-CARE BITS) C3 C2 C1 C X X X X D7 D6 D5 D4 D3 D2 D1 D X X X X X X X X MSB LSB 263 F2 Figure 2. Command and Data Input Format Seria Interface The input is eve triggered. When this input is taken ow, it acts as a chip-seect signa, enabing the SDI and SCK buffers and the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C, is oaded first; then 4 don t-care bits; and finay the 16-bit data word. The data word comprises the 12-, 1- or 8-bit input code, ordered MSB-to-LSB, foowed by 4, 6 or 8 don t-care bits (LTC263-12, -1 and -8 respectivey; see Figure 2). Data can ony be transferred to the device when the signa is ow, beginning on the first rising edge of SCK. SCK may be high or ow at the faing edge of. The rising edge of ends the data transfer and causes the device to execute the command specified in the 24-bit input sequence. The compete sequence is shown in Figure 3a. The command (C3-C) assignments are shown in Tabe 1. The first three commands in the tabe consist of write and update operations. A Write operation oads a 16-bit data word from the 24-bit shift register into the input register. In an Update operation, the input register is copied to the DAC register and converted to an anaog votage at the DAC output. Write to and Update combines the first two commands. The Update operation aso powers up the DAC if it had been in power-down mode. The data path and registers are shown in the Bock Diagram. Whie the minimum input sequence is 24-bits, it may optionay be extended to 32-bits to accommodate microprocessors that have a minimum word width of 16-bits (2 bytes). To use the 32-bit width, 8 don t-care bits are transferred to the device first, foowed by the 24-bit sequence described. Figure 3b shows the 32-bit sequence ff

15 OPERATION The 16-bit data word is ignored for a commands that do not incude a Write operation. Power-Down Mode For power-constrained appications, power-down mode can be used to reduce the suppy current whenever the DAC output is not needed. When in power-down, the buffer ampifier, bias circuit, and reference circuit are disabed and draw essentiay zero current. The DAC output is put into a high-impedance state, and the output pin is passivey pued to ground through a 2kΩ resistor. Input and DAC register contents are not disturbed during power-down. The DAC can be put into power-down mode by using command 1. The suppy current is reduced to 1.8µA maximum when the DAC is powered down. Norma operation resumes after executing any command that incudes a DAC update, as shown in Tabe 1. The DAC is powered up and its votage output is updated. Norma setting is deayed whie the bias, reference, and ampifier circuits are re-enabed. The power-up deay time is 18µs for setting to 12-bits. Reference Modes For appications where an accurate externa reference is not avaiabe, the LTC263 has a user-seectabe, integrated reference. The LTC263-LM and LTC263-LZ provide a fu-scae output of 2.5V. The LTC263-HM and LTC263- HZ provide a fu-scae output of 4.96V. The interna reference can be usefu in appications where the suppy votage is poory reguated. Interna Reference mode can be seected by using command 11, and is the power-on defaut. LTC263 The DAC can aso operate in suppy as reference mode using command 111. In this mode, V CC suppies the DAC s reference votage and the suppy current is reduced. Votage Output The LTC263 s integrated rai-to-rai ampifier has guaranteed oad reguation when sourcing or sinking up to 1mA at 5V, and 5mA at 3V. Load reguation is a measure of the ampifier s abiity to maintain the rated votage accuracy over a wide range of oad current. The measured change in output votage per change in forced oad current is expressed in LSB/mA. DC output impedance is equivaent to oad reguation, and may be derived from it by simpy cacuating a change in units from LSB/mA to ohms. The ampifier s DC output impedance is.1ω when driving a oad we away from the rais. When drawing a oad current from either rai, the output votage headroom with respect to that rai is imited by the 5Ω typica channe resistance of the output devices (e.g., when sinking 1mA, the minimum output votage is 5Ω 1mA, or 5mV). See the graph Headroom at Rais vs. Output Current in the Typica Performance Characteristics section. The ampifier is stabe driving capacitive oads of up to 5pF. 263ff 15

16 LTC263 OPERATION Rai-to-Rai Output Considerations In any rai-to-rai votage output device, the output is imited to votages within the suppy range. Since the anaog output of the DAC cannot go beow ground, it may imit for the owest codes as shown in Figure 4b. Simiary, imiting can occur near fu scae when using the suppy as reference. If V FS = V CC and the DAC fu-scae error (FSE) is positive, the output for the highest codes imits at V CC, as shown in Figure 4. No fu-scae imiting can occur if V FS is ess than V CC FSE. Offset and inearity are defined and tested over the region of the DAC transfer function where no output imiting can occur. Board Layout The PC board shoud have separate areas for the anaog and digita sections of the circuit. A singe, soid ground pane shoud be used, with anaog and digita signas carefuy routed over separate areas of the pane. This keeps digita signas away from sensitive anaog signas and minimizes the interaction between digita ground currents and the anaog section of the ground pane. The resistance from the LTC263 GND pin to the ground pane shoud be as ow as possibe. Resistance here wi add directy to the effective DC output impedance of the device (typicay.1ω). Note that the LTC263 is no more susceptibe to this effect than any other parts of this type; on the contrary, it aows ayout-based performance improvements to shine rather than imiting attainabe performance with excessive interna resistance. Another technique for minimizing errors is to use a separate power ground return trace on another board ayer. The trace shoud run between the point where the power suppy is connected to the board and the DAC ground pin. Thus the DAC ground pin becomes the common point for anaog ground, digita ground, and power ground. When the LTC263 is sinking arge currents, this current fows out the ground pin and directy to the power ground trace without affecting the anaog ground pane votage. It is sometimes necessary to interrupt the ground pane to confine digita ground currents to the digita portion of the pane. When doing this, make the gap in the pane ony as ong as it needs to be to serve its purpose and ensure that no traces cross over the gap ff

17 LTC263 OPERATION Optoisoated 4mA to 2mA Process Controer Figure 5 shows how to use an LTC263HZ to make an optoisoated, digitay-controed 4mA to 2mA transmitter. The transmitter circuitry, incuding optoisoation, is powered by the oop votage which has a wide range of 5.4V to 8V. The 5V output of the LT 31-5 is used to set the 4mA offset current and V OUT is used to digitay contro the ma to 16mA signa current. The suppy current for the reguator, DAC, and op amp is we beow the 4mA budget at zero scae. R S senses the tota oop current, which incudes the quiescent suppy current and additiona current through Q1. Note that at the maximum oop votage of 8V, Q1 wi dissipate 1.6W when I OUT = 2mA and must have an appropriate heat sink. R OFFSET and R GAIN are the cosest.1% vaues to idea for controing a 4mA to 2mA output as the digita input varies from zero scae to fu scae. Aternativey, R OFFSET can be a 365k, 1% resistor in series with a 2k trim pot and R GAIN can be a 75.k, 1% resistor in series with a 5k trim pot. The optoisoators shown wi imit the speed of the seria bus; the 6N139 is an aternative that wi aow higher data rates. SCK SDI C3 C2 C1 C X X X X D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X X X 263 F3a COMMAND WORD 4 DON T-CARE BITS DATA WORD 24-BIT INPUT WORD Figure 3a. 24-Bit Load Sequence (Minimum Input Word) LTC SDI Data Word: 12-Bit Input Code + 4 Don t-care Bits (Shown); LTC263-1 SDI Data Word: 1-Bit Input Code + 6 Don t-care Bits; LTC263-8 SDI Data Word: 8-Bit Input Code + 8 Don t-care Bits SCK SDI X X X X X X X X C3 C2 C1 C X X X X D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X X X 8 DON T-CARE BITS COMMAND WORD 4 DON T-CARE BITS DATA WORD 32-BIT INPUT WORD 263 F3b Figure 3b. 32-Bit Load Sequence LTC SDI Data Word: 12-Bit Input Code + 4 Don t-care Bits (Shown); LTC263-1 SDI Data Word: 1-Bit Input Code + 6 Don t-care Bits; LTC263-8 SDI Data Word: 8-Bit Input Code + 8 Don t-care Bits 263ff 17

18 LTC263 OPERATION OUTPUT VOLTAGE NEGATIVE OFFSET V INPUT CODE (b) VREF = V CC OUTPUT VOLTAGE V 2,48 4,95 INPUT CODE (a) Figure 4. Effects of Rai-to-Rai Operation on a DAC Transfer Curve (Shown for 12-Bits). (a) Overa Transfer Function (b) Effect of Negative Offset for Codes Near Zero (c) Effect of Positive Fu-Scae Error for Codes Near Fu Scae V REF = V CC INPUT CODE (c) POSITIVE FSE OUTPUT VOLTAGE 263 F ff

19 Typica Appication LTC Bit, 2.7V to 5.5V Singe Suppy, Votage Output DAC 2.7V TO 5.5V.1µF µp SDI SCK V CC LTC263-LZ12 GND V OUT OUTPUT V TO 2.5V OR V TO V CC 263 TA1 263ff 19

20 LTC263 Package Description Pease refer to for the most recent package drawings. SC6 Package 6-Lead SC6 Package Pastic SC7 (Reference 6-Lead LTC DWG Pastic # SC7 Rev B) (Reference LTC DWG # Rev B).47 MAX.65 REF (NOTE 4) 1. REF 2.8 BSC 1.8 REF (NOTE 4) INDEX AREA (NOTE 6) PIN 1 RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR BSC PLCS (NOTE 3) GAUGE PLANE.15 BSC 1. MAX..1 REF (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED.254mm 6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE INDEX AREA 7. EIAJ PACKAGE REFERENCE IS EIAJ SC-7 8. JEDEC PACKAGE REFERENCE IS MO-23 VARIATION AB SC6 SC7 125 REV B 2 263ff

21 LTC263 Revision History (Revision history begins at Rev F) REV DATE DESCRIPTION PAGE NUMBER F 6/12 Corrected units on parameter V OSTC from mv/ C to µv/ C 6 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 263ff 21

22 LTC263 Typica Appication V LOOP 5.4V TO 8V LT31-5 IN OUT SHDN SENSE + 1µF R OFFSET 374k.1% 1µF GND FROM OPTO- ISOLATED INPUTS V CC SDI LTC263-HZ SCK V OUT R GAIN 76.8k.1% 3.1k + LTC254 1k Q1 2N344 1k 1 P F 5V R S 1Ω SDI SCK OPTO-ISOLATORS 5Ω 4N28 1k SDI SCK I OUT 263 TA2 Figure 5. An Optoisoated 4mA to 2mA Process Controer Reated Parts PART NUMBER DESCRIPTION COMMENTS LTC166/LTC1665 Octa 1-/8-Bit V OUT DACs in 16-Pin Narrow SSOP V CC = 2.7V to 5.5V, Micropower, Rai-to-Rai Output LTC1663 Singe 1-Bit V OUT DAC in SOT-23 V CC = 2.7V to 5.5V, 6µA, Interna reference, SMBus Interface LTC1664 Quad 1-Bit V OUT DAC in 16-Pin Narrow SSOP V CC = 2.7V to 5.5V, Micropower, Rai-to-Rai Output LTC1669 Singe 1-Bit V OUT DAC in SOT-23 V CC = 2.7V to 5.5V, 6µA, Interna reference, I 2 C Interface LTC1821 Parae 16-Bit Votage Output DAC Precision 16-Bit Setting in 2µs for 1V Step LTC26/LTC261/LTC262 Octa 16-/14-/12-Bit V OUT DACs in 16-Lead SSOP 25µA per DAC, 2.5V to 5.5V Suppy Range, Rai-to-Rai Output, SPI Seria Interface LTC261/LTC2611/LTC2621 Singe 16-/14-/12-Bit V OUT DACs in 1-Lead DFN 3µA per DAC, 2.5V to 5.5V Suppy Range, Rai-to-Rai Output, SPI Seria Interface LTC262/LTC2612/LTC2622 Dua 16-/14-/12-Bit V OUT DACs in 8-Lead MSOP 3µA per DAC, 2.5V to 5.5V Suppy Range, Rai-to-Rai Output, SPI Seria Interface LTC264/LTC2614/LTC2624 Quad 16-/14-/12-Bit V OUT DACs in 16-Lead SSOP 25µA per DAC, 2.5V to 5.5V Suppy Range, Rai-to-Rai Output, SPI Seria Interface LTC2631 Singe 12-/1-/8-Bit I 2 C V OUT DACs with 1ppm/ C Reference in ThinSOT 18µA per DAC, 2.7V to 5.5V Suppy Range, 1ppm/ C Reference, Seectabe Externa Ref. Mode, Rai-to-Rai Output, I 2 C Interface LTC264 Singe 12-/1-/8-Bit SPI V OUT DACs with 1ppm/ C Reference in ThinSOT 18µA per DAC, 2.7V to 5.5V Suppy Range, 1ppm/ C Reference, Seectabe Externa Ref. Mode, Rai-to-Rai Output, SPI Interface 22 LT 612 REV F PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION ff