Dual Low Voltage Ideal Diode Controller. Applications. Typical Application

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1 Dua Low Votage Idea Diode Controer Features n Low Loss Repacement for Power Diodes n Contros N-Channe MOSFETs n V to 18V Suppy ORing or Hodup n 1µs Gate Turn-On and Turn-Off Time n Enabe Inputs n MOSFET On-Status Outputs n 16-Lead MSOP and DFN (4mm 3mm) Packages Appications n Redundant Power Suppies n Suppy Hodup n High Avaiabiity Systems and Servers n Teecom and Network Infrastructure L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks and Hot Swap, PowerPath and ThinSOT are trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Protected by U.S. Patents, incuding and Description The LTC 4353 contros externa N-channe MOSFETs to impement an idea diode function. It repaces two high power Schottky diodes and their associated heat sinks, saving power and board area. The idea diode function permits ow oss power suppy ORing and suppy hodup appications. The reguates the forward-votage drop across the MOSFET to ensure smooth current transfer in diode-or appications. A fast turn-on reduces the oad votage droop during suppy switchover. If the input suppy fais or is shorted, a fast turn-off minimizes reverse-current transients. The controer operates with suppies from 2.9V to 18V. If both suppies are beow 2.9V, an externa suppy is needed at the pin. Enabe inputs can be used to turn off the MOSFET and put the controer in a ow current state. Status outputs indicate whether the MOSFETs are on or off. Typica Appication 2.9V to 18V, 1A Idea Diode-OR Output Maintained with Faiing Input Suppy 2.9V TO 18V *.1µF EN1 GND ONST1 MOSFET ON-STATUS OUTPUTS V OUT 1A VOLTAGE 2V/DIV * 2.9V TO 18V *OPTIONAL FOR FAST TURN-ON 4353 TA1a = 5.2V = 5V I L = 8A C L = 1µF V OUT 5µs/DIV 4353 TA1b 1

2 Absoute Maximum Ratings,,, Votages... 2V to 24V Votage....3V to 6.5V, Votages (Note 3)....3V to 34V, Votages (Note 3)....3V to 34V EN1,, ONST1, Votages....3V to 24V, Average Current...1mA ONST1, Currents...5mA (Notes 1, 2) Operating Ambient Temperature Range C... C to 7 C I... 4 C to 85 C Storage Temperature Range C to 15 C Lead Temperature (Sodering, 1 sec) MS Package...3 C Pin Configuration TOP VIEW EN1 15 GND ONST1 DE PACKAGE 16-LEAD (4mm 3mm) PLASTIC DFN T JMAX = 125 C, θ JA = 43 C/W EXPOSED PAD (PIN 17) PCB GND CONNECTION OPTIONAL TOP VIEW MS PACKAGE 16-LEAD PLASTIC MSOP T JMAX = 125 C, θ JA = 125 C/W 16 EN1 15 GND ONST1 Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE CDE#PBF CDE#TRPBF Pin (4mm 3mm) Pastic DFN C to 7 C IDE#PBF IDE#TRPBF Pin (4mm 3mm) Pastic DFN 4 C to 85 C CMS#PBF CMS#TRPBF Pin Pastic MSOP C to 7 C IMS#PBF IMS#TRPBF Pin Pastic MSOP 4 C to 85 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: 2

3 Eectrica Characteristics The denotes those specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. = = 12V, OUT = V IN, Open, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Suppies V IN, Operating Range V With Externa Suppy V (EXT) Externa Suppy Operating Range, V (REG) Reguated Votage V I IN, Current Enabed, Higher Suppy Enabed, Lower Suppy Pu-Up Disabed Other V IN = 11.7V, Both EN = V Other V IN = 12.3V, Both EN = V Both V IN = V, = 5V, Both EN = V Both EN = 1V ma µa µa µa I CC Current Enabed Disabed = 5V, Both V IN = 1.2V, Both EN = V = 5V, Both V IN = 1.2V, Both EN = 1V (UVLO) Undervotage Lockout Threshod Rising V Δ(HYST) Undervotage Lockout Hysteresis mv Idea Diode Contro V FR Forward Reguation Votage (V IN OUT) V IN = 1.2V, = 5V V IN = 12V ΔV GATE MOSFET Gate Drive (GATE V IN ) V FWD =.2V; I =, 1μA; Highest V IN =12V V FWD =.2V; I =, 1μA; Highest V IN =2.9V t ON(GATE), Turn-On Propagation Deay V FWD (= V IN OUT) Step:.3V to.3v.4 1 µs t OFF(GATE), Turn-Off Propagation Deay V FWD Step:.3V to.3v.3 1 µs I GATE, Fast Pu-Up Current, Fast Pu-Down Current, Off Pu-Down Current V FWD =.4V, ΔV GATE = V, CPO = 17V V FWD =.8V, ΔV GATE = 5V Corresponding EN = 1V, ΔV GATE = 2.5V A A µa Input/Output Pins V EN(TH) EN1, Threshod Votage EN Faing mv ΔV EN(TH) EN1, Threshod Hysteresis mv I EN EN1, Current At.6V ±1 µa I OUT, Current Enabed Disabed OUTn = V, 12V; Both EN = V Both EN = 1V µa µa I CPO(UP), Pu-Up Current CPO = V IN µa V OL ONST1, Output Low Votage I = 1mA I = 3mA V OH ONST1, Output High Votage I = 1μA V I ONST ONST1, Leakage Current At 12V ±1 µa ΔV GATE(ON) MOSFET On-Detect Threshod (GATE V IN ) ONST Pus Low V ma µa mv mv V V V V Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: A currents into device pins are positive; a currents out of device pins are negative. A votages are referenced to GND uness otherwise specified. Note 3: Interna camps imit the GATE and CPO pins to a minimum of 1V above, and a diode beow the corresponding V IN pin. Driving these pins to votages beyond the camp may damage the device. 3

4 Typica Performance Characteristics uness otherwise noted. T A = 25 C, = = 12V, OUT = V IN, open, V IN Current vs Votage 2.5 OTHER V IN = V V IN Current vs Votage with Externa = 6V OTHER V IN = V Current vs Votage 1.75 BOTH V IN = V 1.5 I IN (ma) I IN (µa) 15 1 I CC (ma) OTHER V IN = 12V V IN (V) G V IN (V) G (V) 4353 G3 I OUT (µa) OUT Current vs Votage V FR (mv) Forward Reguation Votage vs V IN Votage with Externa = 3.3V = 5V V GATE V IN (V) V GATE Votage vs Current 14 OUT = V IN.1V 12 1 V IN = 18V V IN = 2.9V V OUT (V) G V IN (V) G I GATE (µa) 4353 G6 14 V GATE and Votages vs V IN Votage 8 ONST Output Low Votage vs Current 5 ONST Output High Votage vs Current V GATE V IN, (V) V GATE V OL (mv) V OH (V) V IN (V) 4353 G I ONST (ma) G I ONST (µa) G9 4

5 Typica Performance Characteristics uness otherwise noted. T A = 25 C, = = 12V, OUT = V IN, open, Start-Up Waveform on Power-Up Fast Gate Switchover From Faiing Suppy 2V/DIV VOLTAGE 5V/DIV OUT 2V/DIV V 5V/DIV V 1V/DIV = 5.2V = 5V C L = 1µF I L = 8A 5ms/DIV 4353 G1 5µs/DIV 4353 G11 Pin Functions, : Charge Pump Output. Connect a capacitor from this pin to the corresponding V IN pin. The vaue of this capacitor shoud be approximatey 1 the gate capacitance (C ISS ) of the MOSFET switch. The charge stored on this capacitor is used to pu-up the gate during a fast turn-on. Leave this pin open if fast turn-on is not needed. EN1, : Enabe Input. Keep this pin beow.6v to enabe diode contro on the corresponding suppy. Driving this pin high shuts off the MOSFET gate (current can sti fow through its body diode). The comparator has a buit-in hysteresis of 8mV. Having both EN pins high owers the current consumption of the controer. Exposed Pad (DE Package Ony): This pin may be eft open or connected to device ground., : MOSFET Gate Drive Output. Connect this pin to the gate of the externa N-channe MOSFET switch. An interna camp imits the gate votage to 12V above, and a diode beow the input suppy. During fast turn-on, a 1.4A pu-up current charges GATE from CPO. During fast turn-off, a 1.4A pu-down current discharges GATE to V IN. GND: Device Ground. ONST1, : MOSFET Status Output. This pin is pued ow by an interna switch when GATE is more than.7v above V IN to indicate an on MOSFET. An interna 5k resistor pus this pin up to a diode beow. It may be pued above using an externa pu-up. Tie to GND or eave open if unused., : Output Votage Sense Input. Connect this pin to the oad side of the MOSFET. The votage sensed at this pin is used to contro the MOSFET gate. : Low Votage Suppy. Connect a.1μf capacitor from this pin to ground. For V IN 2.9V, this pin provides decouping for an interna reguator that generates a 5V suppy. For appications where both V IN < 2.9V, aso connect an externa suppy votage in the 2.9V to 6V range to this pin., : Votage Sense and Suppy Input. Connect this pin to the suppy side of the MOSFET. The ow votage suppy is generated from the higher of and. The votage sensed at this pin is used to contro the MOSFET gate. 5

6 Functiona Diagram V DISABLE1 16 EN1 + CP1 LDO + V FR1 SA1 + CHARGE PUMP1 f = 3MHz.7V + + 5k ONST LOW OFF CP4 2.55V + CP2 OFF 5k.7V V 1 + CP3 DISABLE2 + V FR2 + SA2 CHARGE PUMP2 f = 3MHz CP5 Z EXPOSED GND PAD* BD *DE PACKAGE ONLY 6

7 Operation The contros N-channe MOSFETs to emuate two idea diodes. When enabed, each servo ampifier (SA1, SA2) contros the gate of the externa MOSFET to servo its forward votage drop (V FWD = V IN OUT) to V FR. The gate votage rises to enhance the MOSFET if the oad current causes the drop to exceed V FR. For arge output currents, the MOSFET gate is driven fuy on and the votage drop is equa to I FET R DS(ON). In the case of an input suppy short-circuit, when the MOSFET is conducting, a arge reverse current starts fowing from the oad towards the input. SA detects this faiure condition as soon as it appears, and turns off the MOSFET by rapidy puing down its gate. SA quicky pus up the gate whenever it senses a arge forward votage drop. An externa capacitor between the CPO and V IN pins is needed for fast gate pu-up. This capacitor is charged up, at device power-up, by the interna charge pump. The stored charge is used for the fast gate pu-up. The GATE pin sources current from the CPO pin and sinks current to the V IN and GND pins. Camps imit the GATE and CPO votages to 12V above and a diode beow V IN. Interna switches pu the ONST pins ow when the GATE to V IN votage exceeds.7v to indicate that power is passing through the MOSFET. LDO is a ow dropout reguator that generates a 5V suppy at the pin from the highest V IN input. When both V IN are beow 2.9V, an externa suppy in the 2.9V to 6V range is required at the pin. and EN pin comparators, CP1 to CP3, contro power passage. The MOSFET is hed off whenever the EN pin is above.6v, or the pin is beow 2.55V. A high on both EN pins owers the current consumption of the device. 7

8 Appications Information High avaiabiity systems often empoy parae connected power suppies or battery feeds to achieve redundancy and enhance system reiabiity. ORing diodes have been a popuar means of connecting these suppies at the point of oad. Diodes foowed by storage capacitors aso hod up suppy votages when an input votage sags or has a brownout. The disadvantage of these approaches is the diode s significant forward-votage drop and the resuting power oss. The soves these probems by using an externa N-channe MOSFET as the pass eement (see Figure 1). The MOSFET is turned on when power is being passed, aowing for a ow votage drop from the suppy to the oad. When the input source votage drops beow the output common suppy votage it turns off the MOSFET, thereby matching the function and performance of an idea diode. Power Suppy Configuration The can operate with input suppies down to V. This requires powering the pin with an eary externa suppy in the 2.9V to 6V range. In this range of operation V IN shoud be ower than. If powers up after V IN and backfeeding of by the interna 5V LDO is a concern, then a series resistor (few 1Ω) or Schottky diode imits device power dissipation and backfeeding of a ow suppy when any V IN is high. A.1µF bypass capacitor shoud aso be connected between the and GND pins, cose to the device. Figure 2 iustrates this. If either V IN operates above 2.9V, the externa suppy at is not needed. The.1µF capacitor is sti required for bypassing. 12V C1 M1 C VCC.1µF EN1 GND ONST1 D1 D2 R1 2.7k R2 2.7k C L OUT 1A C2 12V D1, D2: GREEN LED LN1351C M F1 Figure 1. 12V Idea Diode-OR with Status Lights V TO M1 2.9V TO 18V (V TO 18V) M1 OPTIONAL OR HERE 2.9V TO 6V C VCC.1µF C VCC.1µF V TO M2 V TO 18V (2.9V TO 18V) M F2 8 Figure 2. Power Suppy Configurations

9 Appications Information MOSFET Seection The drives N-channe MOSFETs to conduct the oad current. The important features of the MOSFET are its maximum drain-source votage BV DSS, maximum gatesource votage V GS(MAX), and the on-resistance R DS(ON). If an input is connected to ground, the fu suppy votage can appear across the MOSFET. To survive this, the BV DSS must be higher than the suppy votages. The V GS(MAX) rating of the MOSFET shoud exceed 14V since that is the upper imit of the interna GATE to V IN camp. The R DS(ON) of the MOSFET dictates the maximum votage drop (I L R DS(ON) ) and the power dissipated (I 2 L R DS(ON) ) in the MOSFET. Note that the minimum MOSFET votage drop is controed by the servo ampifier reguation votage, hence, picking a very ow R DS(ON) (beow V FR /I L ) may not be beneficia. CPO Capacitor Seection The recommended vaue of the capacitor between the CPO and V IN pins is approximatey 1 the input capacitance C ISS of the MOSFET. A arger capacitor takes a correspondingy onger time to be charged by the interna charge pump. A smaer capacitor suffers more votage drop during a fast gate turn-on event as it shares charge with the MOSFET gate capacitance. Externa CPO Suppy The interna charge pump takes miiseconds to charge up the CPO capacitor especiay during device power-up. This time can be shortened by connecting an externa suppy to the CPO pin. A series resistor is needed to imit the current into the interna camp between CPO and V IN pins. The CPO suppy shoud aso be higher than the main input suppy to meet the gate drive requirements of the MOSFET. Figure 3 shows such a 3.3V idea diode appication, where a 12V suppy is connected to the CPO pins through a 1k resistor. The 1k imits the current into the CPO pin, when the V IN pin is grounded. For the 8.7V gate drive (12V 3.3V), ogic-eve MOSFETs woud be an appropriate choice for M1 and M2. Input Transient Protection When the capacitances at the input and output are very sma, rapid changes in current can cause transients that exceed the 24V absoute maximum rating of the V IN and OUT pins. In ORing appications, one surge suppressor connected from OUT to ground camps a the inputs. In the absence of a surge suppressor, an output capacitance of 1μF is sufficient in most appications to prevent the transient from exceeding 24V. V INA 3.3V C1 M1 12V 1k 1k C2 V INB 3.3V M F3 Figure V Idea Diode with Externa 12V Suppy Powering CPO for Faster Start-Up and Refresh 9

10 Appications Information Design Exampe The foowing design exampe demonstrates the cacuations invoved for seecting components in a 12V system with 1A maximum oad current (see Figure 1). First, cacuate the R DS(ON) of the MOSFET to achieve the desired forward drop at fu oad. Assuming a V DROP of 3mV: R DS(ON) V DROP = 3mV I LOAD 1A = 3mΩ The offers a good soution in a SO-8 sized package with a 2.8mΩ maximum R DS(ON), 3V BV DSS, and 2V V GS(MAX). The maximum power dissipation in the MOSFET is: P = I 2 LOAD R DS(ON) = (1A) 2 2.8mΩ =.3W With a maximum steady-state therma resistance θ JA of 35 C/W,.3W causes a modest 11 C rise in junction temperature of the above the ambient. The input capacitance, C ISS, of the is about 55pF. Foowing the 1 recommendation, a capacitor is seected for C1 and C2. LEDs, D1 and D2, require around 3mA for good uminous intensity. Accounting for a 2V diode drop and.6v V OL, R1 and R2 are set to 2.7k. PCB Layout Considerations Connect the V IN and OUT pin traces as cose as possibe to the MOSFET s terminas. Keep the traces to the MOS- FET wide and short to minimize resistive osses. The PCB traces associated with the power path through the MOSFET shoud have ow resistance (see Figure 4). It is aso important to put C VCC, the bypass capacitor for the pin, as cose as possibe between and GND. Pace C1 and C2 near the CPO and V IN pins. Surge suppressors, when used, shoud be mounted cose to the using short ead engths. M1 SO-8 CURRENT FLOW S D FROM SUPPLY A W S S D D TO LOAD G D VIA TO GROUND PLANE C VCC MSOP-16 S D TRACK WIDTH W:.3 PER AMPERE ON 1oz Cu FOIL DRAWING IS NOT TO SCALE! FROM SUPPLY B W S S G M2 SO-8 D D D CURRENT FLOW TO LOAD 4353 F4 1 Figure 4. Recommended PCB Layout for M1, M2, C VCC

11 Typica Appications 12V Suppy with Capacitive Reservoir for Data Backup on Power Fai for Disk Drive and Soid-State Drive Appications 12V C1 M1 EN1 R CHRG 1k C VCC.1µF GND ONST1 BUCK REG. STORAGE DEVICE C2 C RESV 3F M TA2 C RESV : 3 PARALLEL STRINGS, EACH WITH 3 SERIES PM-5RV35-R 3.3V Main and Auxiiary Suppy Diode-OR (Auxiiary Idea Diode Disabed if Main Above 2.95V) 3.3V MAIN C1 M1 EN1 R3 39.2k C VCC.1µF GND ONST1 OUT R4 1k C2 3.3V AUX M TA3 11

12 Typica Appications Pug-in Card Suppy Hodup Using Idea Diode at 12V and 3.3V Inputs 12V M1 + C HOLDUP1 12V OUT C2 3.3V BACKPLANE CONNECTORS PLUG-IN CARD M2 + C HOLDUP2 3.3V OUT 4353 TA4 12

13 Typica Appications Redundant Power Suppy System with ORing on Backpane, as in MicroTCA POWER SUPPLY MODULE 1 LOAD CARD 1 EN1 12V.1µF GND ONST1 LOAD CARD 2 POWER SUPPLY MODULE 2 EN1 12V.1µF GND ONST TA5 13

14 Package Description Pease refer to for the most recent package drawings. DE Package 16-Lead Pastic DFN (4mm 3mm) (Reference LTC DWG # Rev Ø).7 ± ± ± ± ±.5 PACKAGE OUTLINE 3.15 REF.25 ±.5.45 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4. ±.1 (2 SIDES) R =.5 TYP 9 R =.115 TYP 16.4 ±.1 PIN 1 TOP MARK (SEE NOTE 6).2 REF 3. ±.1 (2 SIDES).75 ± ± ± REF BOTTOM VIEW EXPOSED PAD 1.23 ±.5.45 BSC PIN 1 NOTCH R =.2 OR CHAMFER (DE16) DFN 86 REV Ø NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT ILUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFEREE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 14

15 Package Description Pease refer to for the most recent package drawings. MS Package 16-Lead Pastic MSOP (Reference LTC DWG # Rev Ø).889 ±.127 (.35 ±.5) 5.23 (.26) MIN ( ).35 ±.38 (.12 ±.15) TYP.5 (.197) BSC RECOMMENDED SOLDER PAD LAYOUT 4.39 ±.12 (.159 ±.4) (NOTE 3) ±.76 (.11 ±.3) REF.254 (.1) DETAIL A 6 TYP 4.9 ±.152 (.193 ±.6) 3. ±.12 (.118 ±.4) (NOTE 4) GAUGE PLANE.18 (.7) DETAIL A NOTE: 1. DIMENSIONS IN MILLIMETER/(IH) 2. DRAWING NOT TO SCALE.53 ±.152 (.21 ±.6) SEATING PLANE 1.1 (.43) MAX (.7.11) TYP (.197) BSC 3. DIMENSION DOES NOT ILUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED.152mm (.6") PER SIDE 4. DIMENSION DOES NOT ILUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED.152mm (.6") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE.12mm (.4") MAX.86 (.34) REF.116 ±.58 (.4 ±.2) MSOP (MS16) 117 REV Ø Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 15

16 Typica Appication 1.2V Idea Diode-OR V INA 1.2V EN1 5V.1µF GND ONST1 TO LOAD V INB 1.2V 4353 TA6 Reated Parts PART NUMBER DESCRIPTION COMMENTS LTC1473/LTC1473L Dua PowerPath Switch Driver N-Channe, 4.75V to 3V/3.3V to 1V, SSOP-16 Package LTC1479 PowerPath Controer for Dua Battery Systems Three N-Channe Drivers, 6V to 28V, SSOP-36 Package LTC4352 Low Votage Idea Diode Controer with Monitoring N-Channe, V to 18V, UV, OV, MSOP-12 and DFN-12 Packages LTC4354 Negative Votage Diode-OR Controer and Monitor Dua N-Channe, 4.5V to 8V, SO-8 and DFN-8 Packages LTC4355 Positive High Votage Idea Diode-OR with Suppy and Dua N-Channe, 9V to 8V, SO-16 and DFN-14 Packages Fuse Monitors LTC4357 Positive High Votage Idea Diode Controer N-Channe, 9V to 8V, MSOP-8 and DFN-6 Packages LTC4358 5A Idea Diode Interna N-Channe, 9V to 26.5V, TSSOP-16 and DFN-14 Packages LTC437 Two-Suppy Diode-OR Current Sharing Controer Dua N-Channe, V to 18V, MSOP-16 and DFN-16 Packages LTC A Low Loss Idea Diode in ThinSOT Interna P-Channe, 2.6V to 5.5V, 4μA I Q, SOT-23 Package LTC4412/LTC4412HV Low Loss PowerPath Controer in ThinSOT P-Channe, 2.5V to 28V/36V, 11μA I Q, SOT-23 Package LTC4413/LTC Dua 2.6A, 2.5V to 5.5V, Idea Diodes in DFN-1 Dua Interna P-Channe, 2.5V to 5.5V, DFN-1 Package LTC V Low Loss PowerPath Controer for Large P-Channe, 3V to 36V, 3μA I Q, MSOP-8 Package P-Channe MOSFETs LTC4415 Dua 4A Idea Diodes with Adjustabe Current Limit Dua P-Channe 5mΩ Idea Diodes, 1.7V to 5.5V, 15mV Forward Drop, MSOP-16 and DFN-16 Packages LTC4416/LTC V Low Loss Dua PowerPath Controer for Large P-Channe MOSFETs Dua P-Channe, 3.6V to 36V, 7μA I Q, MSOP-1 Package 16 LT 512 PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION 212