LTC6803-2/LTC Multicell Battery Stack Monitor APPLICATIONS TYPICAL APPLICATION

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1 FEATURES n Measures Up to 12 Battery Ces in Series n Stackabe Architecture n Supports Mutipe Battery Chemistries and Supercapacitors n Individuay Addressabe Seria Interface n.25% Maximum Tota Measurement Error n Engineered for ISO26262 Compiant Systems n 13ms to Measure A Ces in a System n Passive Ce Baancing: Integrated Ce Baancing MOSFETs Abiity to Drive Externa Baancing MOSFETs n Onboard Temperature Sensor and Thermistor Inputs n 1MHz Seria Interface with Packet Error Checking n Safe with Random Connection of Ces n Buit-In Sef Tests n Deta-Sigma Converter With Buit-In Noise Fiter n Open-Wire Connection Faut Detection n 12µA Standby Mode Suppy Current n High EMI Immunity n 44-Lead SSOP Package APPLICATIONS n Eectric and Hybrid Eectric Vehices n High Power Portabe Equipment n Backup Battery Systems n Eectric Bicyces, Motorcyces, Scooters LTC683-2/LTC683-4 Mutice Battery Stack Monitor DESCRIPTION The LTC 683 is a 2nd generation, compete battery monitoring IC that incudes a 12-bit ADC, a precision votage reference, a high votage input mutipexer and a seria interface. Each LTC683 can measure up to 12 series connected battery ces or supercapacitors. Many LTC683 devices can be stacked to measure the votage of each ce in a ong battery string. Each LTC683-2/LTC683-4 has an individuay addressabe seria interface, aowing up to 16 LTC683-2/LTC683-4 devices to interface to one contro processor and operate simutaneousy. Each ce input has an associated MOSFET switch for discharging overcharged ces. The LTC683-2 connects the bottom of the stack to internay. It is pin compatibe with the LTC682-2, providing a drop-in upgrade. The LTC683-4 separates the bottom of the stack from, improving ce 1 measurement accuracy. The LTC683 provides a standby mode to reduce suppy current to 12µA. Furthermore, the LTC683 can be powered from an isoated suppy, providing a technique to reduce battery stack current draw to zero. The reated LTC683-1 and LTC683-3 offer a seria interface that aows the seria ports of mutipe LTC683-1 or LTC683-3 devices to be daisy chained without optocoupers or isoators. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. TYPICAL APPLICATION NEXT 12-CELL PACK ABOVE V LTC683-4 Suppy Current vs Modes of Operation 12-CELL BATTERY OR CAPACITOR STRING NEXT 12-CELL PACK BELOW 1k NTC MUX EXTERNAL TEMP 1k DIE TEMP REGISTERS AND CONTROL 12-BIT Σ ADC VOLTAGE REFERENCE SERIAL DATA 4-BIT ADDRESS 5V ISOLATED DC/DC CONVERTER 12V SUPPLY CURRENT 1mA 1µA 1µA 1µA 1nA 1nA 1nA HW SHUTDOWN STANDBY MEASURE TA1b TA1a 1

2 LTC683-2/LTC683-4 ABSOLUTE MAXIMUM RATINGS Tota Suppy Votage (V to )...75V Input Votage (Reative to ) C....3V to 8V C V to 75V Cn (Note 5)....3V to Min (8 n, 75V) Sn (Note 5)....3V to Min (8 n, 75V) A Other Pins....3V to 7V Votage Between Inputs Cn to Cn V to 8V Sn to Cn V to 8V C12 to C8....3V to 25V C8 to C4....3V to 25V C4 to C....3V to 25V (Note 1) Operating Temperature Range LTC683I... 4 C to 85 C LTC683H... 4 C to 125 C Specified Temperature Range LTC683I... 4 C to 85 C LTC683H... 4 C to 125 C Junction Temperature C Storage Temperature Range C to 15 C Note: n = 1 to 12 PIN CONFIGURATION LTC683-2 TOP VIEW LTC683-4 TOP VIEW V 1 44 CSBI V 1 44 CSBI C SDO C SDO S SDI S SDI C SCKI C SCKI S A3 S A3 C A2 C A2 S A1 S A1 C A C A S GPIO2 S GPIO2 C GPIO1 C GPIO1 S WDTB S WDTB C NC C TOS S TOS S V REG C V REG C V REF S V REF S V TEMP2 C V TEMP2 C V TEMP1 S5 C4 S V TEMP1 NC S5 C4 S NC C C S1 C S1 S C1 S C1 C S2 C S2 G PACKAGE 44-LEAD PLASTIC SSOP T JMAX = 15 C, θ JA = 7 C/W G PACKAGE 44-LEAD PLASTIC SSOP T JMAX = 15 C, θ JA = 7 C/W 2

3 LTC683-2/LTC683-4 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC683IG-2#PBF LTC683IG-2#TRPBF LTC683G-2 44-Lead Pastic SSOP 4 C to 85 C LTC683IG-4#PBF LTC683IG-4#TRPBF LTC683G-4 44-Lead Pastic SSOP 4 C to 85 C LTC683HG-2#PBF LTC683HG-2#TRPBF LTC683G-2 44-Lead Pastic SSOP 4 C to 125 C LTC683HG-4#PBF LTC683HG-4#TRPBF LTC683G-4 44-Lead Pastic SSOP 4 C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on non-standard ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V = 43.2V, = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Specifications V S Suppy Votage, V Reative to V ERR Specification Met Timing Specification Met V LSB Measurement Resoution Quantization of the ADC 1.5 mv/bit ADC Offset (Note 2).5.5 mv ADC Gain Error (Note 2) % % V ERR Tota Measurement Error (Note4) V CELL =.3V V CELL = 2.3V V CELL = 2.3V V CELL = 3.6V V CELL = 3.6V, LTC683IG V CELL = 3.6V, LTC683HG V CELL = 4.2V V CELL = 4.2V, LTC683IG V CELL = 4.2V, LTC683HG V CELL = 5V 2.3V < V TEMP < 4.2V, LTC683IG 2.3V < V TEMP < 4.2V, LTC683HG V CELL Ce Votage Range Fu-Scae Votage Range.3 5 V V CM Common Mode Votage Range Range of Inputs Cn <.25% Gain Error, n V Measured Reative to n = 2 to 11, LTC683IG Range of Inputs C, C1 <.25% Gain Error, 5 V LTC683IG Range of Inputs Cn <.5% Gain Error, n V n = 2 to 11, LTC683HG Range of Inputs C, C1 <.5% Gain Error, 5 V LTC683HG Die Temperature Measurement Error Error in Measurement of 125 C 5 C ±2.5 ± V V mv mv mv mv mv mv mv mv mv mv mv mv 3

4 LTC683-2/LTC683-4 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V = 43.2V, = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V REF Reference Pin Votage R LOAD = 1k to V V Reference Votage Temperature 8 ppm/ C Coefficient Reference Votage Therma Hysteresis 25 C to 85 C and 25 C to 4 C 1 ppm Reference Votage Long-Term Drift 6 ppm/ khr V REF2 2nd Reference Votage V REG Reguator Pin Votage 1V < V < 5V, No Load I LOAD = 4mA V V 5.5 V V Reguator Pin Short-Circuit Limit 8 ma I B Input Bias Current In/Out of Pins C1 Through C12 When Measuring Ce When Not Measuring Ce I S Suppy Current, Measure Mode (Note 7) Current Into the V Pin When Measuring Continuous Measuring (CDC = 2) Continuous Measuring (CDC = 2) Measure Every 13ms (CDC = 5) Measure Every 5ms (CDC = 6) Measure Every 2 Seconds (CDC = 7) I QS Suppy Current, Standby Current Into V Pin When In Standby, A Seria Port Pin at Logic 1 LTC683IG LTC683HG I SD Suppy Current, Hardware Shutdown Current Out of, V C12 = 43.2V, V Foating (Note 8) µa na µa µa µa µa µa µa µa µa.1 1 µa Discharge Switch-On Resistance V CELL > 3V (Note 3) 1 2 Ω I OW Current Used for Open-Wire Detection µa Therma Shutdown Temperature 145 C Therma Shutdown Hysteresis 5 C Votage Mode Timing Specifications t CYCLE Measurement Cycing Time Required to Measure 12 Ces Time Required to Measure 1 Ces Time Required to Measure 3 Temperatures Time Required to Measure 1 Ce or Temperature t 1 SDI Vaid to SCKI Rising Setup 1 ns t 2 SDI Vaid to SCKI Rising Hod 25 ns t 3 SCKI Low 4 ns t 4 SCKI High 4 ns t 5 CSBI Puse Width 4 ns t 6 CSBI Faing to SCKI Rising 1 ns t 7 CSBI Faing to SDO Vaid 1 ns t 8 SCKI Faing to SDO Vaid 25 ns Cock Frequency 1 MHz Watchdog Timer Timeout Period Seconds ms ms ms ms 4

5 LTC683-2/LTC683-4 ELECTRICAL CHARACTERISTICS The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. V = 43.2V, = V, uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Votage Mode Digita I/O V IH Digita Input Votage High Pins SCKI, SDI and CSBI 2 V V IL Digita Input Votage Low Pins SCKI, SDI and CSBI.8 V V OL Digita Output Votage Low Pin SDO, Sinking 5µA.3 V I IN Digita Input Current V MODE, TOS, SCKI, SDI, CSBI 1 µa Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: The ADC specifications are guaranteed by the Tota Measurement Error (V ERR ) specification. Note 3: Due to the contact resistance of the production tester, this specification is tested to reaxed imits. The 2Ω imit is guaranteed by design. Note 4: V CELL refers to the votage appied across Cn to Cn 1 for n = 1 to 12. V TEMP refers to the votage appied from V TEMP1 or V TEMP2 to. Note 5: These absoute maximum ratings appy provided that the votage between inputs do not exceed the absoute maximum ratings. Note 6: Suppy current is tested during continuous measuring. The suppy current during periodic measuring (13ms, 5ms, 2s) is guaranteed by design. Note 7: The CDC = 5, 6 and 7 suppy currents are not measured. They are guaranteed by the CDC = 2 suppy current measurement. Note 8: Limit is determined by high speed automated test capabiity. TYPICAL PERFORMANCE CHARACTERISTICS TOTAL UNADJUSTED ERROR (mv) Ce Measurement Error vs Ce Input Votage T A = 125 C T A = 85 C T A = 25 C T A = 4 C CELL INPUT VOLTAGE (V) 5. CELL VOLTAGE ERROR (mv) Ce Measurement Error vs Input RC Vaues C = µf C =.1µF C = 1µF C = 3.3µF CELL 1, 13ms CELL MEASUREMENT REPETITION V CELL = 3.3V INPUT RESISTANCE (kω) CELL VOLTAGE ERROR (mv) Ce Measurement Error vs Input RC Vaues C = µf C =.1µF C = 1µF C = 3.3µF CELLS 2 TO 12, 13ms CELL MEASUREMENT REPETITION V CELL = 3.3V INPUT RESISTANCE (kω) G G G3 5

6 LTC683-2/LTC683-4 TYPICAL PERFORMANCE CHARACTERISTICS CELL 12 MEASUREMENT ERROR (mv) Ce 12 Measurement Error vs V T A = 25 C V CELL = 3.3V V V C12 (V) G4 CELL MEASUREMENT ERROR (mv) Ce Votage Measurement Error vs Common Mode Votage V CELL = 3.6V T A = 25 C CELL2 ERROR vs V C1 CELL3 ERROR vs V C2 CELLn ERROR VS V Cn 1, n = 4 TO COMMON MODE VOLTAGE (V) G5 CELL VOLTAGE MEASUREMENT ERROR (mv) Ce Measurement Error vs Ce Votage ALL OTHER CELLS = 3V CELL V IN CELL6 (V) G6 CELL MEASUREMENT ERROR (mv) Ce 1 Votage Measurement Error vs Temperature V CELL =.8V V = 9.6V 4 SAMPLES TEMPERATURE ( C) G7 CELL MEASUREMENT ERROR (mv) Ce 2 Votage Measurement Error vs Temperature V CELL =.8V V = 9.6V 4 SAMPLES TEMPERATURE ( C) G8 CELL MEASUREMENT ERROR (mv) Ce 3 to Ce 12 Votage Measurement Error vs Temperature 1.25 V CELL =.8V V = 9.6V 4 SAMPLES TEMPERATURE ( C) G9 NUMBER OF UNITS Measurement Gain Error Hysteresis T A = 85 C TO 25 C CHANGE IN GAIN ERROR (ppm) G1 NUMBER OF UNITS Measurement Gain Error Hysteresis T A = 45 C TO 25 C CHANGE IN GAIN ERROR (ppm) G11 REJECTION (db) Ce Measurement Common Mode Rejection V CM(IN) = 5V P-P 72dB REJECTION CORRESPONDS TO LESS THAN 1 BIT AT ADC OUTPUT k 1k 1k 1M 1M FREQUENCY (Hz) G12 6

7 TYPICAL PERFORMANCE CHARACTERISTICS LTC683-2/LTC683-4 ADC Norma Mode Rejection vs Frequency 2. ADC INL 1. ADC DNL REJECTION (db) INL (BITS) DNL (BITS) k 1k 1k FREQUENCY (Hz) G INPUT (V) G INPUT (V) G15 CELL INPUT BIAS CURRENT (na) Ce Input Bias Current During Standby and Hardware Shutdown CELL INPUT = 3.6V C12 C1 C TEMPERATURE ( C) SUPPLY CURRENT (µa) Standby Suppy Current vs Suppy Votage SUPPLY VOLTAGE (V) 125 C 85 C 25 C 4 C 6 SUPPLY CURRENT (µa) Suppy Current vs Suppy Votage During Continuous Conversions CDC = 2 CONTINUOUS CONVERSION SUPPLY VOLTAGE (V) 125 C 85 C 25 C 4 C G G G18 E = (AMBIENT TEMP-INTERNAL DIE TEMP READING) ( C) Interna Die Temperature Measurement Error Using an 8mV/ K Scae Factor 1 SAMPLES TOTAL UNADJUSTED ERROR (mv) Externa Temperature Measurement Tota Unadjusted Error vs Input T A = 125 C T A = 85 C T A = 25 C T A = 4 C TEMPERATURE ( C) TEMPERATURE INPUT VOLTAGE (V) G G2 7

8 LTC683-2/LTC683-4 TYPICAL PERFORMANCE CHARACTERISTICS V REF (V) V REF Output Votage vs Temperature 5 REPRESENTATIVE UNITS TEMPERATURE ( C) G21 V REF (V) V REF Load Reguation T A = 85 C T A = 4 C 1 1 SOURCING CURRENT (µa) T A = 25 C G22 V REF (V) V REF Line Reguation NO EXTERNAL LOAD ON V REF, CDC = 2 (CONTINUOUS CELL CONVERSIONS) T A = 25 C T A = 85 C T A = 4 C SUPPLY VOLTAGE (V) G23 V REG (V) V REG Load Reguation V = 43.2V T A = 125 C T A = 85 C T A = 25 C T A = 4 C SUPPLY CURRENT (ma) G24 V REG (V) V REG Line Reguation CDC = 2 CONTINUOUS CONVERSIONS SUPPLY VOLTAGE (V) T A = 125 C T A = 85 C T A = 25 C T A = 4 C G25 DISCHARGE RESISTANCE (Ω) Interna Discharge Resistance vs Ce Votage T A = 15 C T A = 85 C T A = 25 C T A = 45 C CELL VOLTAGE (V) G26 INCREASE IN DIE TEMPERATURE ( C) Die Temperature Increase vs Discharge Current in Interna FET ALL 12 CELLS AT 3.6V V S = 43.2V T A = 25 C 12 CELLS DISCHARGING 6 CELLS DISCHARGING 1 CELL DISCHARGING DISCHARGE CURRENT PER CELL (ma) G27 CONVERSION TIME (ms) Ce Conversion Time TEMPERATURE ( C) G28 8

9 PIN FUNCTIONS To ensure pin compatibiity with LTC682-2, the LTC683 2 is configured such that the bottom ce input (C) is connected internay to the negative suppy votage ( ). The LTC683-4 offers a unique pinout with an input for the bottom ce (C). This simpe functiona difference offers the possibiity for enhanced ce 1 measurement accuracy, enhanced SPI noise toerance and simpified wiring. More information is provided in the Appications Information section entited Advantages of Kevin Connection for C. V (Pin 1): Positive Power Suppy. Pin 1 can be tied to the most positive potentia in the battery stack or an isoated power suppy. V must be greater than the most positive potentia in the battery stack under norma operation. With an isoated power suppy, LTC683 can be turned off by simpy shutting down V. C12, C11, C1, C9, C8, C7, C6, C5, C4, C3, C2, C1 (Pins 2, 4, 6, 8, 1, 12, 14, 16, 18, 2, 22, 24): C1 through C12 are the inputs for monitoring battery ce votages. The negative termina of the bottom ce shoud be tied to the pin for the LTC683-2, and the C pin for the LTC The next owest potentia is tied to C1 and so forth. See the figures in the Appications Information section for more detais on connecting batteries to the LTC683-2 and LTC The LTC683 can monitor a series connection of up to 12 ces. Each ce in a series connection must have a common mode votage that is greater than or equa to the ces beow it. 1mV negative votages are permitted. C (Pin 26 on LTC683-4): Negative Termina of the Bottom Battery Ce. C and form a Kevin connection to eiminate effect of votage drop at the trace. S12, S11, S1, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25): S1 though S12 pins are used to baance battery ces. If one ce in a series becomes overcharged, an S output can be used to discharge the ce. Each S output has an interna N-channe MOSFET for discharging. See the Bock Diagram. The NMOS has a maximum on-resistance of 2Ω. An externa resistor LTC683-2/LTC683-4 shoud be connected in series with the NMOS to dissipate heat outside of the LTC683 package. When using the interna MOSFETs to discharge ces, the die temperature shoud be monitored. See Power Dissipation and Therma Shutdown in the Appications Information section. The S pins aso feature an interna pu-up PMOS. This aows the S pins to be used to drive the gates of externa MOSFETs for higher discharge capabiity. (Pin 26 on LTC683-2/Pin 27 on LTC683-4): Connect to the most negative potentia in the series of ces. NC (Pin 27 on LTC683-2/Pin 28 on LTC683-4): This pin is not used and is internay connected to through 1Ω. It can be eft unconnected or connected to on the PCB. V TEMP1, V TEMP2 (Pins 28, 29 on LTC683-2/Pins 29, 3, on LTC683-4): Temperature Sensor Inputs. The ADC wi measure the votage on V TEMPn with respect to and store the resut in the TMP register. The ADC measurements are reative to the V REF pin votage. Therefore a simpe thermistor and resistor combination connected to the V REF pin can be used to monitor temperature. The V TEMP inputs can aso be genera purpose ADC inputs. V REF (Pin 3 on LTC683-2/Pin 31 on LTC683-4): 3.65V Votage Reference Output. This pin shoud be bypassed with a 1µF capacitor. The V REF pin can drive a 1k resistive oad connected to. Larger oads shoud be buffered with an LT63 op amp, or a simiar device. V REG (Pin 31 on LTC683-2/Pin 32 on LTC683-4): Linear Votage Reguator Output. This pin shoud be bypassed with a 1µF capacitor. The V REG is capabe of sourcing up to 4mA to an externa oad. The V REG pin does not sink current. TOS (Pin 32 on LTC683-2/Pin 33 on LTC683-4): Top of Stack Input. The TOS pin can be tied to V REG or for the LTC683. The state of the TOS pin aters the operation of the SDO pin in the togge poing mode. See the Seria Port description. NC (Pin 33 on LTC683-2): No Connection. 9

10 LTC683-2/LTC683-4 PIN FUNCTIONS WDTB (Pin 34): Watchdog Timer Output (Active Low). If there is no vaid command received in 1 to 2.5 seconds, the WDTB output is asserted. The WDTB pin is an open-drain NMOS output. When asserted it pus the output down to and resets the configuration register to its defaut state. GPIO1, GPIO2 (Pins 35, 36): Genera Purpose Input/ Output. By writing a to a GPIO configuration register bit, the open-drain output is activated and the pin is pued to. By writing a ogic 1 to the configuration register bit, the corresponding GPIO pin is high impedance. An externa resistor is required to pu the pin up to V REG. By reading the configuration register ocations GPIO1 and GPIO2, the state of the pins can be determined. For exampe, if a is written to register bit GPIO1, a is aways read back because the output N-channe MOSFET pus Pin 35 to. If a 1 is written to register bit GPIO1, the pin becomes high impedance. Either a 1 or a is read back, depending on the votage present at Pin 35. The GPIOs makes it possibe to turn-on/off circuitry around the LTC683-4, or read ogic vaues from a circuit around the LTC The GPIO pins shoud be connected to if not used. A, A1, A2, A3 (Pins 37, 38, 39, 4): Address Inputs. These pins are tied to V REG or. The state of the address pins (V REG = 1, = ) determines the LTC683 address. See Address Commands in the Seria Port subsection of the Appications Information section. SCKI (Pin 41): Seria Cock Input. The SCKI pin interfaces to any ogic gate (TTL eves). See Seria Port in the Appications Information section. SDI (Pin 42): Seria Data Input. The SDI pin interfaces to any ogic gate (TTL eves). See Seria Port in the Appications Information section. SDO (Pin 43): Seria Data Output. The SDO pin is an NMOS open-drain output. A pu-up resistor is needed on SDO. See Seria Port in the Appications Information section. CSBI (Pin 44): Chip Seect (Active Low) Input. The CSBI pin interfaces to any ogic gate (TTL eves). See Seria Port in the Appications Information section. 1

11 BLOCK DIAGRAMS LTC683-2/LTC LTC683-2 C12 2nd REFERENCE V REF2 1 V REGULATOR V REG 31 3 S12 WATCHDOG TIMER WDTB 34 4 C11 21 S3 22 C2 MUX Σ A/D CONVERTER 12 RESULTS REGISTER AND COMMUNICATIONS A3 A2 A1 A CSBI S2 24 C1 25 S1 REFERENCE SDO 43 SDI 42 SCKI 41 GPIO V CONTROL GPIO1 38 DIE TEMP EXTERNAL TEMP NC V TEMP1 V TEMP V REF 3 TOS BD 11

12 LTC683-2/LTC683-4 BLOCK DIAGRAMS LTC V 2nd REFERENCE V REF2 REGULATOR V REG 32 2 C12 3 S12 WATCHDOG TIMER WDTB 34 4 C11 21 S3 22 C2 23 S2 24 C1 25 S1 MUX Σ A/D CONVERTER REFERENCE 12 RESULTS REGISTER AND COMMUNICATIONS A3 A2 A1 A CSBI SDO SDI SCKI GPIO C CONTROL GPIO DIE TEMP EXTERNAL TEMP TOS 33 NC V TEMP1 V TEMP2 V REF BD TIMING DIAGRAM Timing Diagram of the Seria Interface t 1 t 2 t 4 t 6 t 3 t 7 SCKI SDI D3 D2 D1 D D7 D4 D3 t 5 CSBI t 8 SDO D4 D3 D2 D1 D D7 D4 D3 PREVIOUS COMMAND CURRENT COMMAND 6834 TD 12

13 OPERATION THEORY OF OPERATION The LTC683 is a data acquisition IC capabe of measuring the votage of 12 series connected battery ces. An input mutipexer connects the batteries to a 12-bit deta-sigma anaog-to-digita converter (ADC). An interna 8ppm/ C votage reference combined with the ADC give the LTC683 its outstanding measurement accuracy. The inherent benefits of the deta-sigma ADC versus other types of ADCs (e.g., successive approximation) are expained in Advantages of Deta-Sigma ADCs in the Appications Information section. Communication between the LTC683 and a host processor is handed by a SPI compatibe seria interface. Mutipe LTC683s can be connected to a singe seria interface. As shown in Figure 1, the LTC683-2s or LTC683-4s are isoated from one another using digita isoators. A unique addressing scheme aows a the LTC683-2s or LTC683 4s to connect to the same seria port of the host processor. Further expanation of the LTC683-2/LTC683-4 can be found in the Seria Port section of the data sheet. The LTC683 aso contains circuitry to baance ce votages. Interna MOSFETs can be used to discharge ces. These interna MOSFETs can aso be used to contro externa baancing circuits. Figure 1 iustrates ce baancing by interna discharge. Figure 3 shows the S pin controing an externa baancing circuit. It is important to note that the LTC683 makes no decisions about turning on/off the interna MOSFETs. This is competey controed by the host processor. The host processor writes vaues to a configuration register inside the LTC683 to contro the switches. The watchdog timer on the LTC683 can be used to turn off the discharge switches if communication with the host processor is interrupted. Since the LTC683-4 separates C and, C can have higher potentia than. This feature is very usefu for super capacitors and fue ces whose votages can go to zero or sighty negative. In such a case, the stacked ces can t power the LTC In Figure 1, an isoated 36V and 3.6V provides power to each LTC This aows the C1 to C12 pins to go up to 3.6V beow C. LTC683-2/LTC683-4 The LTC683 has three modes of operation: hardware shutdown, standby and measure. Hardware shutdown is a true zero power mode. Standby mode is a power saving state where a circuits except the seria interface are turned off. In measure mode, the LTC683 is used to measure ce votages and store the resuts in memory. Measure mode wi aso monitor each ce votage for overvotage (OV) and undervotage (UV) conditions. HARDWARE SHUTDOWN MODE The V pin can be disconnected from the C pins and the battery pack. If the V suppy pin is V, the LTC683 wi typicay draw ess than 1nA from the battery ces. A circuits inside the IC are off. It is not possibe to communicate with the IC when V = V. See the Appications Information section for hardware shutdown circuits. STANDBY MODE The LTC683 defauts (powers up) to standby mode. Standby mode is the owest suppy current state with a suppy connected. Standby current is typicay 12µA when V = 44V. A circuits are turned off except the seria interface and the votage reguator. For the owest possibe standby current consumption, a SPI ogic inputs shoud be set to ogic 1 eve. The LTC683 can be programmed for standby mode by setting the comparator duty cyce configuration bits, CDC[2:], to. If the part is put into standby mode whie ADC measurements are in progress, the measurements wi be interrupted and the ce votage registers wi be in an indeterminate state. To exit standby mode, the CDC bits must be written to a vaue other than. MEASURE MODE The LTC683 is in measure mode when the CDC bits are programmed with a vaue from 1 to 7. When CDC = 1 the LTC683 is on and waiting for a start ADC conversion command. When CDC is 2 through 7 the IC monitors each ce votage and produces an interrupt signa on the SDO pin indicating a ce votages are within the UV and OV imits. The vaue of the CDC bits determines how often the ces are monitored, and, how much average suppy current is consumed. 13

14 LTC683-2/LTC683-4 OPERATION V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 LTC683-4 IC #1 CSBI SDO SDI SCKI A3 A2 A1 A GPIO2 GPIO1 WDTB TOS V REG V REF V TEMP2 V TEMP1 NC C S1 C1 S2 ADDRESS1 V2 OE2 V1 OE1 V2 V1 V2 V1 DIGITAL ISOLATOR ISOLATED DC/DC CONVERTER 3V 12V V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 LTC683-4 IC #7 CSBI SDO SDI SCKI A3 A2 A1 A GPIO2 GPIO1 WDTB TOS V REG V REF V TEMP2 V TEMP1 NC C S1 C1 S2 ADDRESS7 V2 OE2 V1 OE1 V2 V1 V2 V1 DIGITAL ISOLATOR ISOLATED DC/DC CONVERTER 3V 12V F1 3V V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 LTC683-4 IC # CSBI SDO SDI SCKI A3 A2 A1 A GPIO2 GPIO1 WDTB TOS V REG V REF V TEMP2 V TEMP1 NC C S1 C1 S2 ADDRESS V2 OE2 V1 OE1 V2 V1 V2 V1 DIGITAL ISOLATOR ISOLATED DC/DC CONVERTER 3V 12V MPU MISO CS MSI CLK MODULE IO Figure 1. Simpified 96-Ce Battery or Supercapacitor, Isoated Interface. In this Diagram the Battery Negative is Isoated from the Modue Ground. Isoated Power Suppies Each LTC Opto-Coupers or Digita Isoators Aow Each IC to Be Addressed Individuay 14

15 OPERATION There are two methods for indicating the UV/OV interrupt status: togge poing (using a 1kHz output signa) and eve poing (using a high or ow output signa). The poing methods are described in the Seria Port section. The UV/OV imits are set by the V UV and V OV vaues in the configuration registers. When a ce votage exceeds the UV/OV imits a bit is set in the fag register. The UV and OV fag status for each ce can be determined using the Read Fag Register Group. An ADC measurement can be requested at any time when the IC is in measure mode. To initiate ce votage measurements whie in measure mode, a Start A/D Conversion command is sent. After the command has been sent, the LTC683 wi indicate the A/D converter status via togge poing or eve poing (as described in the Seria Port section). During ce votage measurement commands, the UV and OV fags (within the fag register group) are aso updated. When the measurements are compete, the part wi continue monitoring UV and OV conditions at the rate designated by the CDC bits. Note that there is a 5µs window during each UV/OV comparison cyce where an ADC measurement request may be missed. This is an unikey event. For exampe, the comparison cyce is 2 seconds when CDC = 7. Use the CLEAR command to detect missing ADC commands. Operating with Less than 12 Ces If fewer than 12 ces are connected to the LTC683, the unused input channes must be masked. The MCxI bits in the configuration registers are used to mask channes. In addition, the LTC683 can be configured to automaticay bypass the measurements of the top 2 ces, reducing power consumption and measurement time. If the CELL1 bit is high, the inputs for ce 11 and ce 12 are masked and ony the bottom 1-ce votages wi be measured. By defaut, the CELL1 bit is ow, enabing measurement of a 12-ce votages. Additiona information regarding operation with ess than 12 ces is provided in the appications section. LTC683-2/LTC683-4 ADC RANGE AND OUTPUT FORMAT The ADC outputs a 12-bit code with an offset of x2 (512 decima). The input votage can be cacuated as: V IN = (DOUT 512) V LSB ; V LSB = 1.5mV where DOUT is a decima integer. For exampe, a V input wi have an output reading of x2. An ADC reading of x means the input was.768v. The absoute ADC measurement range is.768v to 5.376V. The resoution is V LSB = 1.5mV = ( )/2 12. The usefu range is.3v to 5V. This range aows monitoring supercapacitors which coud have sma negative votage. Inputs beow.3v exceed the absoute maximum rating of the C pins. If a inputs are negative, the ADC range is reduced to.1v. Inputs above 5V wi have noisy ADC readings (see Typica Performance Characteristics). ADC MEASUREMENTS DURING CELL BALANCING The primary ce votage ADC measurement commands (STCVAD and STOWAD) automaticay turn off a ce s discharge switch whie its votage is being measured. The discharge switches for the ce above and the ce beow wi aso be turned off during the measurement. For exampe, discharge switches S4, S5 and S6 wi be off whie ce 5 is being measured. The UV/OV comparison conversions in CDC modes 2 through 7 aso cause a momentary turn-off of the discharge switch. For exampe, switches S4, S5 and S6 wi be off whie ce 5 is checked for a UV/OV condition. In some systems it may be desirabe to aow discharging to continue during ce votage measurements. The ce votage ADC conversion commands STCVDC and STOWDC aow the discharge switches to remain on during ce votage measurements. This feature aows the system to perform a sef test to verify the discharge functionaity. 15

16 LTC683-2/LTC683-4 OPERATION ADC REGISTER CLEAR COMMAND The cear command can be used to cear the ce votage registers and temperature registers. The cear command wi set a registers to xfff. This command is used to make sure conversions are being made. When ce votages are stabe, ADC resuts coud stay the same. If a start ADC conversion command is sent to the LTC683 but the PEC fais to match then the command is ignored and the votage register contents aso wi not change. Sending a cear command then reading back register contents is a way to make sure LTC683 is accepting commands and performing new measurements. The cear command takes 1ms to execute. ADC CONVERTER SELF TEST Two sef-test commands can be used to verify the functionaity of the digita portions of the ADC. The sef tests aso verify the ce votage registers and temperature monitoring registers. During these sef tests a test signa is appied to the ADC. If the circuitry is working propery a ce votage and temperature registers wi contain x555 or xaaa. The time required for the sef-test function is the same as required to measure a ce votages or a temperature sensors. MULTIPLEXER AND REFERENCE SELF TEST The LTC683 uses a mutipexer to measure the 12 battery ce inputs as we as the temperature signas. A diagnostic command is used to vaidate the function of the mutipexer, the temperature sensor, and the precision reference circuit. Diagnostic registers wi be updated after each diagnostic test. The muxfai bit of the registers wi be 1 if the mutipexer sef test fais. A constant votage generated by the 2nd reference circuit wi be measured by the ADC and the resuts written to the diagnostic register. The votage reading shoud be 2.5V ±16%. Readings outside this range indicate a faiure of the temperature sensor circuit, the precision reference circuit, or the anaog portion of the ADC. The DAGN command executes in 16.4ms, which is the sum of the 12-ce t CYCLE and the 3 temperature t CYCLE. The diagnostic read command can be used to read the registers. 16 USING THE GENERAL PURPOSE INPUTS/OUTPUTS (GPIO1, GPIO2) The LTC683 has two genera purpose digita input/output pins. By writing a GPIO configuration register bit to a ogic ow, the open-drain output can be activated. The GPIOs give the user the abiity to turn on/off circuitry around the LTC683. One exampe might be a circuit to verify the operation of the system. When a GPIO configuration bit is written to a ogic high, the corresponding GPIO pin may be used as an input. The read back vaue of that bit wi be the ogic eve that appears at the GPIO pins. WATCHDOG TIMER CIRCUIT The LTC683 incudes a watchdog timer circuit. The watchdog timer is on for a modes except CDC =. The watchdog timer times out if no vaid command is received for 1 to 2.5 seconds. When the watchdog timer circuit times out, the WDTB open-drain output is asserted ow and the configuration register bits are reset to their defaut (power-up) state. In the power-up state, CDC is, the S outputs are off and the IC is in the ow power standby mode. The WDTB pin remains ow unti a vaid command is received. The watchdog timer provides a means to turn off ce discharging shoud communications to the MPU be interrupted. There is no need for the watchdog timer at CDC = since discharging is off. The open-drain WDTB output can be wire ORd with other externa open-drain signas. Puing the WDTB signa ow wi not initiate a watchdog event, but the CNFGO bit 7 wi refect the state of this signa. Therefore, the WDTB pin can be used to monitor externa digita events if desired. SERIAL PORT Overview The LTC683-2/LTC683-4 has an SPI bus compatibe seria port. Devices can be connected in parae, using digita isoators. Mutipe devices are uniquey identified by a part address determined by the A to A3 pins. Physica Layer on the LTC683-2/LTC683-4, four pins comprise the seria interface: CSBI, SCKI, SDI and SDO. The SDO

17 OPERATION and SDI may be tied together, if desired, to form a singe, bi-directiona port. Four address pins (A to A3) set the part address for address commands. The TOS pin designates the top device (ogic high) for poing commands. A interface pins are votage mode, with votage eves sensed with respect to the suppy. See Figure 1. Data Link Layer Cock Phase And Poarity: The LTC683 SPI compatibe interface is configured to operate in a system using CPHA = 1 and CPOL = 1. Consequenty, data on SDI must be stabe during the rising edge of SCKI. Data Transfers: Every byte consists of 8 bits. Bytes are transferred with the most significant bit (MSB) first. On a write, the data vaue on SDI is atched into the device on the rising edge of SCKI (Figure 2). Simiary, on a read, the data vaue output on SDO is vaid during the rising edge of SCKI and transitions on the faing edge of SCKI (Figure 3). CSBI must remain ow for the entire duration of a command sequence, incuding between a command byte and subsequent data. On a write command, data is atched in on the rising edge of CSBI. LTC683-2/LTC683-4 Network Layer PEC Byte: The packet error code (PEC) byte is a cycic redundancy check (CRC) vaue cacuated for a of the bits in a register group in the order they are passed, using the initia PEC vaue of 11 and the foowing characteristic poynomia: x 8 x 2 x 1 To cacuate the 8-bit PEC vaue, a simpe procedure can be estabished: 1. Initiaize the PEC to For each bit DIN coming into the register group, set IN = DIN XOR PEC[7], then IN1 = PEC[] XOR IN, IN2 = PEC[1] XOR IN. 3. Update the 8-bit PEC as PEC[7] = PEC[6], PEC[6] = PEC[5], PEC[3] = PEC[2], PEC[2] = IN2, PEC[1] = IN1, PEC[] = IN. 4. Go back to step 2 unti a data are shifted. The 8-bit resut is the fina PEC byte. CSBI SCKI SDI MSB (CMD) BIT 6 (CMD) LSB (CMD) MSB (DATA) LSB (DATA) 6834 F2 Figure 2. Transmission Format (Write) CSBI SCKI SDI MSB (CMD) BIT 6 (CMD) LSB (CMD) SDO MSB (DATA) LSB (DATA) 6834 F3 Figure 3. Transmission Format (Read) 17

18 LTC683-2/LTC683-4 OPERATION An exampe to cacuate the PEC is isted in Tabe 1 and Figure 4. The PEC of the 1 byte data x1 is computed as xc7 after the ast bit of the byte streamed in. For mutipe byte data, PEC is vaid at the end (LSB) of the ast byte. LTC683 cacuates PEC byte for any command or data received and compares it with the PEC byte foowing the command or data. The command or data is regarded as vaid ony if the PEC bytes match. LTC683 aso attaches the cacuated PEC byte at the end of the data it shifts out. Broadcast Commands: A broadcast command is one to which a devices on the bus wi respond, regardess of device address. See the Bus Protocos and Commands sections. With broadcast commands a devices can be sent commands simutaneousy. This is usefu for ADC conversion and poing commands. It can aso be used with write commands when a parts are being written with the same data. Broadcast read commands shoud not be used in the parae configuration. Address Commands: An address command is one in which ony the addressed device on the bus responds. The first byte of an address command consists of 4 bits with a vaue of 1 and 4 address bits. Foowing the address command is its PEC byte. The third and fourth bytes are the command byte and its PEC byte respectivey. See the Bus Protocos and Commands section. Poing Methods: For ADC conversions, three methods can be used to determine ADC competion. First, a controer can start an ADC conversion and wait for the specified conversion time to pass before reading the resuts. The second method is to hod CSBI ow after an ADC start command has been sent. The ADC conversion status wi be output on SDO (Figure 5). A probem with the second method is that the controer is not free to do other seria communication whie waiting for ADC conversions to compete. The third method overcomes this imitation. The controer can send an ADC start command, perform other tasks, and then send a po ADC converter status (PLADC) command to determine the status of the ADC conversions (Figure 6). For OV/UV interrupt status, the po interrupt status (PLINT) command can be used to quicky determine whether any ce in a stack is in an overvotage or undervotage condition (Figure 6). Tabe 1. Procedure to Cacuate PEC Byte CLOCK CYCLE DIN IN IN1 IN2 PEC[7] PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[]

19 LTC683-2/LTC683-4 OPERATION XOR PEC[7] IN DATAIN PEC[] 1 INO = DATAIN XOR PEC[7]; BEGIN PEC[7:] = x41 CLOCK D Q CLK Q DTFF 2 PEC1 = PEC[] XOR IN; INO XOR PEC1 PEC[] PEC[1] D Q CLK Q DTFF PEC Hardware and Software Exampe BEGIN PEC[7:] = x41 1 INO = DATAIN XOR PEC[7]; 2 PEC1 = PEC[] XOR IN; 3 PEC2 = PEC[1] XOR IN; 4 PEC[7:] = {PEC[6:2], PEC2, PEC1, IN}; END 3 PEC2 = PEC[1] XOR IN; 4 PEC[7:] = {PEC[6:2], PEC2, PEC1, IN}; IN XOR PEC2 PEC[2] D Q END PEC[2] PEC[3] PEC[3] PEC[4] PEC[4] D Q D Q PEC[5] D Q PEC[5] PEC[6] PEC[6] D Q PEC[7] PEC[7] PEC[1] CLK Q DTFF CLK Q DTFF Figure 4 D Q F4 Q CLK Q DTFF CLK Q DTFF CLK Q DTFF CLK DTFF 19

20 LTC683-2/LTC683-4 OPERATION CSBI t CYCLE SCKI SDI MSB (CMD) BIT6 (CMD) LSB (PEC) SDO TOGGLE OR LEVEL POLL F5 Figure 5. Transmission Format (ADC Conversion and Po) CSBI SCKI SDI MSB (CMD) BIT6 (CMD) LSB (PEC) SDO TOGGLE OR LEVEL POLL F6 Figure 6. Transmission Format (PLADC Conversion or PLINT) Togge Poing: Togge poing aows a robust determination both of device states and of the integrity of the connections between the devices in a stack. Togge poing is enabed when the LVLPL bit is ow. After entering a poing command, the data out ine wi be driven by the save devices based on their status. When poing for the ADC converter status, data out wi be ow when any device is busy performing an ADC conversion and wi togge at 1kHz when no device is busy. Simiary, when poing for interrupt status, the output wi be ow when any device has an interrupt condition and wi togge at 1kHz when none has an interrupt condition. Togge Poing Address Poing: The addressed device drives the SDO ine based on its state aone ow for busy/ in interrupt, togging at 1kHz for not busy/not in interrupt. Togge Poing Parae Broadcast Poing: No part address is sent, so a devices respond simutaneousy. If a device is busy/in interrupt, it wi pu SDO ow. If a device is not busy/not in interrupt, then it wi reease the SDO ine (TOS = ) or attempt to togge the SDO ine at 1kHz (TOS = 1).The master controer pus CSBI high to exit poing. 2 Leve Poing: Leve poing is enabed when the LVLPL bit is high. After entering a poing command, the data out ine wi be driven by the save devices based on their status. When poing for the ADC converter status, data out wi be ow when any device is busy performing an ADC conversion and wi be high when no device is busy. Simiary, when poing for interrupt status, the output wi be ow when any device has an interrupt condition and wi be high when none has an interrupt condition. Leve Poing Address Poing: The addressed device drives the SDO ine based on its state aone pued ow for busy/in interrupt, reeased for not busy/not in interrupt. Leve poing Parae Broadcast Poing: No part address is sent, so a devices respond simutaneousy. If a device is busy/in interrupt, it wi pu SDO ow. If a device is not busy/not in interrupt, then it wi reease the SDO ine. If any device is busy or in interrupt the SDO signa wi be ow. If a devices are not busy/not in interrupt, the SDO signa wi be high. The master controer pus CSBI high to exit poing.

21 LTC683-2/LTC683-4 OPERATION Revision Code The diagnostic register group contains a 2-bit revision code. If software detection of device revision is necessary, then contact the factory for detais. Otherwise, the code can be ignored. In a cases, however, the vaues of a bits must be used when cacuating the packet error code (PEC) byte on data reads. Bus Protocos There are 6 different protoco formats, depicted in Tabe 3 through Tabe 8. Tabe 2 is the key for reading the protoco diagrams. Tabe 2. Protoco Key PEC Packet Error Code Master-to-Save N Number of Bits Save-to-Master... Continuation of Protoco Compete Byte of Data Tabe 3. Broadcast Po Command 8 8 Command PEC Po Data Tabe 4. Broadcast Read Command PEC Data Byte Low Data Byte High PEC A bus coision wi occur if mutipe devices are on the same seria bus. Tabe 5. Broadcast Write Command PEC Data Byte Low Data Byte High PEC Tabe 6. Address Po Command Address PEC Command PEC Po Data Tabe 7. Address Read Address PEC Command PEC Data Byte Low Data Byte High PEC See Seria Command exampes Tabe 8. Address Write Address PEC Command PEC Data Byte Low Data Byte High PEC 21

22 LTC683-2/LTC683-4 OPERATION Commands Tabe 9. Command Codes and PEC Bytes COMMAND DESCRIPTION NAME CODE PEC Write Configuration Register Group WRCFG 1 C7 Read Configuration Register Group RDCFG 2 CE Read A Ce Votage Group RDCV 4 DC Read Ce Votages 1-4 RDCVA 6 D2 Read Ce Votages 5-8 RDCVB 8 F8 Read Ce Votages 9-12 RDCVC A F6 Read Fag Register Group RDFLG C E4 Read Temperature Register Group RDTMP E EA Start Ce Votage ADC Conversions and Po Status STCVAD A Ce 1 Ce 2 Ce 3 Ce 4 Ce 5 Ce 6 Ce 7 Ce 8 Ce 9 Ce 1 Ce 11 Ce 12 Cear (FF) Sef Test1 Sef Test2 Start Open-Wire ADC Conversions and Po Status STOWAD A Ce 1 Ce 2 Ce 3 Ce 4 Ce 5 Ce 6 Ce 7 Ce 8 Ce 9 Ce 1 Ce 11 Ce 12 Start Temperature ADC Conversions and Po Status STTMPAD A Externa1 Externa2 Interna Sef Test 1 Sef Test 2 Po ADC Converter Status PLADC 4 7 Po Interrupt Status PLINT 5 77 Start Diagnose and Po Status DAGN Read Diagnostic Register RDDGNR 54 6B A 1B 1C 1D 1E 1F A 2B 2C E 3F B B7 BE B9 AC AB A2 A5 88 8F A 9D E 29 3C 3B F E 59 7A 7D 22

23 OPERATION Tabe 9. Command Codes and PEC Bytes (continued) LTC683-2/LTC683-4 COMMAND DESCRIPTION NAME CODE PEC Start Ce Votage ADC Conversions and Po Status, STCVDC with Discharge Permitted Start Open-Wire ADC Conversions and Po Status, with Discharge Permitted STOWDC A Ce 1 Ce 2 Ce 3 Ce 4 Ce 5 Ce 6 Ce 7 Ce 8 Ce 9 Ce 1 Ce 11 Ce 12 A Ce 1 Ce 2 Ce 3 Ce 4 Ce 5 Ce 6 Ce 7 Ce 8 Ce 9 Ce 1 Ce 11 Ce 12 Tabe 1. Configuration (CFG) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT CFGR RD/WR WDT GPIO2 GPIO1 LVLPL CELL1 CDC[2] CDC[1] CDC[] CFGR1 RD/WR DCC8 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 CFGR2 RD/WR MC4I MC3I MC2I MC1I DCC12 DCC11 DCC1 DCC9 CFGR3 RD/WR MC12I MC11I MC1I MC9I MC8I MC7I MC6I MC5I CFGR4 RD/WR VUV[7] VUV[6] VUV[5] VUV[4] VUV[3] VUV[2] VUV[1] VUV[] CFGR5 RD/WR VOV[7] VOV[6] VOV[5] VOV[4] VOV[3] VOV[2] VOV[1] VOV[] A 6B 6C A 7B 7C E7 E E9 EE FB FC F5 F2 DF D8 D1 D6 C E 8B 8C AF A8 A1 A6 B3 23

24 LTC683-2/LTC683-4 OPERATION Tabe 11. Ce Votage (CV) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT CVR RD C1V[7] C1V[6] C1V[5] C1V[4] C1V[3] C1V[2] C1V[1] C1V[] CVR1 RD C2V[3] C2V[2] C2V[1] C2V[] C1V[11] C1V[1] C1V[9] C1V[8] CVR2 RD C2V[11] C2V[1] C2V[9] C2V[8] C2V[7] C2V[6] C2V[5] C2V[4] CVR3 RD C3V[7] C3V[6] C3V[5] C3V[4] C3V[3] C3V[2] C3V[1] C3V[] CVR4 RD C4V[3] C4V[2] C4V[1] C4V[] C3V[11] C3V[1] C3V[9] C3V[8] CVR5 RD C4V[11] C4V[1] C4V[9] C4V[8] C4V[7] C4V[6] C4V[5] C4V[4] CVR6 RD C5V[7] C5V[6] C5V[5] C5V[4] C5V[3] C5V[2] C5V[1] C5V[] CVR7 RD C6V[3] C6V[2] C6V[1] C6V[] C5V[11] C5V[1] C5V[9] C5V[8] CVR8 RD C6V[11] C6V[1] C6V[9] C6V[8] C6V[7] C6V[6] C6V[5] C6V[4] CVR9 RD C7V[7] C7V[6] C7V[5] C7V[4] C7V[3] C7V[2] C7V[1] C7V[] CVR1 RD C8V[3] C8V[2] C8V[1] C8V[] C7V[11] C7V[1] C7V[9] C7V[8] CVR11 RD C8V[11] C8V[1] C8V[9] C8V[8] C8V[7] C8V[6] C8V[5] C8V[4] CVR12 RD C9V[7] C9V[6] C9V[5] C9V[4] C9V[3] C9V[2] C9V[1] C9V[] CVR13 RD C1V[3] C1V[2] C1V[1] C1V[] C9V[11] C9V[1] C9V[9] C9V[8] CVR14 RD C1V[11] C1V[1] C1V[9] C1V[8] C1V[7] C1V[6] C1V[5] C1V[4] CVR15* RD C11V[7] C11V[6] C11V[5] C11V[4] C11V[3] C11V[2] C11V[1] C11V[] CVR16* RD C12V[3] C12V[2] C12V[1] C12V[] C11V[11] C11V[1] C11V[9] C11V[8] CVR17* RD C12V[11] C12V[1] C12V[9] C12V[8] C12V[7] C12V[6] C12V[5] C12V[4] *Registers CVR15, CVR16, and CVR17 can ony be read if the CELL1 bit in register CFGR is ow Tabe 12. Fag (FLG) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT FLGR RD C4OV C4UV C3OV C3UV C2OV C2UV C1OV C1UV FLGR1 RD C8OV C8UV C7OV C7UV C6OV C6UV C5OV C5UV FLGR2 RD C12OV* C12UV* C11OV* C11UV* C1OV C1UV C9OV C9UV * Bits C11UV, C12UV, C11OV and C12OV are aways ow if the CELL1 bit in register CFGR is high Tabe 13. Temperature (TMP) Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT TMPR RD ETMP1[7] ETMP1[6] ETMP1[5] ETMP1[4] ETMP1[3] ETMP1[2] ETMP1[1] ETMP1[] TMPR1 RD ETMP2[3] ETMP2[2] ETMP2[1] ETMP2[] ETMP1[11] ETMP1[1] ETMP1[9] ETMP1[8] TMPR2 RD ETMP2[11] ETMP2[1] ETMP2[9] ETMP2[8] ETMP2[7] ETMP2[6] ETMP2[5] ETMP2[4] TMPR3 RD ITMP[7] ITMP[6] ITMP[5] ITMP[4] ITMP[3] ITMP[2] ITMP[1] ITMP[] TMPR4 RD NA NA NA THSD ITMP[11] ITMP[1] ITMP[9] ITMP[8] Tabe 14. Packet Error Code (PEC) REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT PEC RD PEC[7] PEC[6] PEC[5] PEC[4] PEC[3] PEC[2] PEC[1] PEC[] Tabe 15. Diagnostic Register Group REGISTER RD/WR BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT DGNR RD REF[7] REF[6] REF[5] REF[4] REF[3] REF[2] REF[1] REF[] DGNR1 RD REV[1] REV[] MUXFAIL NA REF[11] REF[1] REF[9] REF[8] 24

25 LTC683-2/LTC683-4 OPERATION Tabe 16. Memory Bit Descriptions NAME DESCRIPTION VALUES CDC Comparator Duty Cyce CDC (Defaut) UV/OV COMPARATOR PERIOD N/A (Comparator Off) Standby Mode CELL1 1-Ce Mode = 12-ce mode (defaut); 1 = 1-ce mode LVLPL Leve Poing Mode = togge poing (defaut); 1 = eve poing V REF POWERED DOWN BETWEEN MEASUREMENTS Yes CELL VOLTAGE MEASUREMENT TIME 1 N/A (Comparator Off) No 13ms 2 13ms No 13ms 3 13ms No 13ms 4 5ms No 13ms 5 13ms Yes 21ms 6 5ms Yes 21ms 7 2ms Yes 21ms GPIO1 GPIO1 Pin Contro Write: = GPIO1 pin pu-down on; 1 = GPIO1 pin pu-down off (defaut) Read: = GPIO1 pin at ogic ; 1 = GPIO1 pin at ogic 1 GPIO2 GPIO2 Pin Contro Write: = GPIO2 pin pu-down on; 1 = GPIO2 pin pu-down off (defaut) Read: = GPIO2 pin at ogic ; 1 = GPIO2 pin at ogic 1 WDT Watchdog Timer Read: = WDTB pin at ogic ; 1 = WDTB pin at ogic 1 DCCx Discharge Ce x x = = turn off shorting switch for ce x (defaut); 1 = turn on shorting switch V UV Undervotage Comparison Votage* Comparison votage = (V U31) mV (Defaut V UV = ) V OV Overvotage Comparison Votage* Comparison votage = (V O32) mV (Defaut V OV = ) MCxI Mask Ce x Interrupts x = = enabe interrupts for ce x (defaut) 1 = turn off interrupts and cear fags for ce x CxV Ce x Votage* x = bit ADC measurement vaue for ce x ce votage for ce x = (Cx512) 1.5mV reads as xfff whie A/D conversion in progress CxUV Ce x Undervotage Fag x = ce votage compared to V UV comparison votage = ce x not fagged for undervotage condition; 1 = ce x fagged CxOV Ce x Overvotage Fag x = ce votage compared to V OV comparison votage = ce x not fagged for overvotage condition; 1 = ce x fagged ETMPx Externa Temperature Measurement* Temperature measurement votage = (ETMPx 512) 1.5mV THSD Therma Shutdown Status = therma shutdown has not occurred; 1 = therma shutdown has occurred Status ceared to on read of Therma Register Group REV Revision Code Device revision code ITMP Interna Temperature Measurement* Temperature measurement votage = (ITMP 512) 1.5mV = 8mV T( K) PEC Packet Error Code Cycic redundancy check (CRC) vaue REF Reference Votage for Diagnostics This reference votage = (REF 512) 1.5mV. Norma range is within 2.1V to 2.9V *Votage equations use the decima vaue of the registers, to 495 for 12-bit and to 255 for 8-bit registers N/A 25

26 LTC683-2/LTC683-4 OPERATION SERIAL COMMAND EXAMPLES LTC683-2/LTC683-4 (Addressabe Configuration) Exampes beow use a configuration of three stacked devices: bottom (B), midde (M), and top (T) Write Configuration Registers (Figure 7) (Broadcast Write) 1. Pu CSBI ow 2. Send WRCFG command and its PEC byte 3. Send CFGR byte, then CFGR1, CFGR5, PEC byte (A devices on the bus receive the same data) 4. Pu CSBI high; data atched into a devices on rising edge of CSBI. S pins respond as data atched Cacuation of seria interface time for sequence above: Number of devices in stack = N Number of bytes in sequence = B = 2 command byte and 7 data bytes = 2 7 Seria port frequency per bit = F Time = (1/F) * B * 8 bits/byte = (1/F) * (2 7) * 8 Time for 3-ce exampe above, with 1MHz seria port = (1/1) * (2 7)*8 = 72µs Read Ce Votage Registers (12 battery ces, addressabe read) 1. Pu CSBI ow 2. Send Address and PEC byte for bottom device 3. Send RDCV command and its PEC byte 4. Read CVR byte of bottom device, then CVR1 (B), CVR2 (B), CVR17 (B), and then PEC (B) 5. Pu CSBI high 6. Repeat steps 1-5 for midde device and top device Cacuation of seria interface time for sequence above: Number of devices in stack = N Number of bytes in sequence = B = 2 address bytes, 2 command bytes, and 18 data bytes pus 1 PEC byte = 23 * N Seria port frequency per bit = F Time = (1/F) * B * 8 bits/byte = (1/F) * (23 * N) * 8 Time for 3-ce exampe above, with 1MHz seria port = (1/1) * (23 * N) * 8 = 552µs 26

27 OPERATION Start Ce Votage ADC Conversions and Po Status (Broadcast Command with Togge Poing) LTC683-2/LTC Pu CSBI ow 2. Send STCVAD command and its PEC byte (a devices in stack start ADC conversions simutaneousy) 3. SDO output of a devices in parae pued ow for approximatey 12ms 4. SDO output togges at 1kHz rate, indicating conversions compete for a devices 5. Pu CSBI high to exit poing Po Interrupt Status (Leve Poing) 1. Pu CSBI ow 2. Send Address and PEC bytes for bottom device 3. Send PLINT command and PEC bytes 4. SDO output from bottom device pued ow if any device has an interrupt condition; otherwise, SDO high 5. Pu CSBI high to exit poing 6. Repeat steps 1-5 for midde device and top device CSBI SCKI SDI WRCFG CFGR PEC t d t d < 2µs IF Sn IS UNLOADED Sn (n = 1 TO 12) Sn, DISCHARGE PIN STATE F7 Figure 7. S Pin Action and SPI Transmission 27

28 LTC683-2/LTC683-4 APPLICATIONS INFORMATION DIFFERENCE BETWEEN THE LTC683-2 AND LTC683 4 The ony difference between the LTC683-2 and the LTC683-4 is the bonding of the and C pins. The and C are separate signas on every LTC683 die. In the LTC683-2 package, the and C signas are shorted together by bonding these signas to the same pin. In the LTC683 4 package, and C are separate pins. Therefore, the LTC683-2 is pin compatibe with the LTC For new designs the LTC683-4 pinout aows a Kevin connection to C (Figure 22). CELL VOLTAGE FILTERING The LTC683 empoys a samping system to perform its anaog-to-digita conversions and provides a conversion resut that is essentiay an average over the.5ms conversion window, provided there isn t noise aiasing with respect to the deta-sigma moduator rate of 512kHz. This indicates that a owpass fiter with 3dB attenuation at 5kHz may be beneficia. Since the deta-sigma integration bandwidth is about 1kHz, the fiter corner need not be ower than this to assure accurate conversions. Series resistors of 1Ω may be inserted in the input paths without introducing meaningfu measurement error. Shunt capacitors may be added from the ce inputs to, creating RC fitering as shown in Figure 8. The ce baancing MOSFET in Figure 11 can cause a sma transient when it switches on and off. Keeping the cutoff frequency of the RC fiter reativey high wi aow adequate setting prior to the actua conversion. A deay of about 5µs is provided in the ADC timing, so a 16kHz LPF is optima (1Ω,.1µF) and offers about 3dB of noise rejection. 1Ω 1nF 1Ω 1nF 7.5V F8 Figure 8. Adding RC Fitering to the Ce Inputs (One Ce Connection Shown) Cn C(n 1) Larger series resistors and shunt capacitors can be used to ower the fiter bandwidth. The measurement error due to the arger component vaues is a compex function of the component vaues. The error aso depends on how often measurements are made. Tabe 17 is an exampe. In each exampe a 3.6V ce is being measured and the error is dispayed in miivots. There is a RC fiter in series with inputs C1 through C12. There is no fiter in series with C. There is an interaction between ces. This is why the errors for C1 and C12 differ from C2 through C11. Tabe 17. Ce Measurement Errors vs Input RC Vaues R = 1Ω, C =.1µF R = 1k, C =.1µF R = 1k, C = 1µF R = 1k, C = 3.3µF Ce 1 Error (mv, LTC683-2) Ce 2 to Ce 12 (mv) For the LTC683-2, no resistor shoud be paced in series with the pin. Because the suppy current fows from the pin, any resistance on this pin coud generate a significant conversion error for ce 1, and the error of ce 1 caused by the RC fiter differs from errors of ce 2 to ce 2. OPEN-CONNECTION DETECTION When a ce input (C pin) is open, it affects two ce measurements. Figure 9 shows an open connection to C3, in an appication without externa fitering between the C pins and the ces. During norma ADC conversions (that is, using the STCVAD command), the LTC683 wi give near zero readings for B3 and B4 when C3 is open. The zero reading for B3 occurs because during the measurement of B3, the ADC input resistance wi pu C3 to the C2 potentia. Simiary, during the measurement of B4, the ADC input resistance pus C3 to the C4 potentia. Figure 1 shows an open connection at the same point in the ce stack as Figure 9, but this time there is an externa fitering network sti connected to C3. Depending on the vaue of the capacitor remaining on C3, a norma measurement of B3 and B4 may not give near-zero readings, since the C3 pin is not truy open. In fact, with a arge externa capacitance on C3, the C3 votage wi be charged midway 28

29 LTC683-2/LTC683-4 APPLICATIONS INFORMATION B4 B3 B4 B3 C F4 C F C4 C3 C2 C1 MUX Figure 9. Open Connection C4 C3 C2 C MUX 1µA LTC F9 1µA Figure 1. Open Connection with RC Fitering LTC F1 between C2 and C4 after severa cyces of measuring ces B3 and B4. Thus the measurements for B3 and B4 may indicate a vaid ce votage when in fact the exact state of B3 and B4 is unknown. To reiaby detect an open connection, the command STOWAD is provided. With this command, two 1µA current sources are connected to the ADC inputs and turned on during a ce conversions. Referring again to Figure 1, with the STOWAD command, the C3 pin wi be pued down by the 1µA current source during the B3 ce measurement AND during the B4 ce measurement. This wi tend to decrease the B3 measurement resut and increase the B4 measurement resut reative to the norma STCVAD command. The biggest change is observed in the B4 measurement when C3 is open. So, the best method to detect an open wire at input C3 is to ook for an increase in the vaue of battery connected between inputs C3 and C4 (battery B4). The foowing agorithm can be used to detect an open connection to ce pin Cn: 1. Issue a STOWAD command (with 1µA sources connected). 2. Issue a RDCV command and store a ce measurements into array CELLA(n). 3. Issue the 2nd STOWAD command (with 1µA sources connected). 4. Issue the 2nd RDCV command and store a ce measurements into array CELLB(n). 5. For battery ces, if CELLA(1) < or CELLB(1) <, must be open. If CELLA(12) < or CELLB(12) <, C12 must be open. For n = 2 to 11, if CELLB(n1) CELLA(n1) > 2mV, or CELLB(n1) reaches the fu scae of 5.375V, then Cn is open. The 2mV threshod is chosen to provide toerance for measurement errors. For a system with the capacitor connected to Cn arger than.5µf, repeating step 3 severa times wi discharge the externa capacitor enough to meet the criteria. If the top C pin is open yet V is sti connected, then the best way to detect an open connection to the top C pin is by comparing the sum of a ce measurements using the STCVAD command to an auxiiary measurement of the sum of a the ces, using a method simiar to that shown in Figure 19. A significanty ower resut for the sum of a 12 ces suggests an open connection to the top C pin, provided it was aready determined that no other C pin is open. 29

30 LTC683-2/LTC683-4 APPLICATIONS INFORMATION USING THE S PINS AS DIGITAL OUTPUTS OR GATE DRIVERS The S outputs incude an interna pu-up PMOS. Therefore the S pins wi behave as a digita output when oaded with a high impedance, e.g. the gate of an externa MOSFET. For appications requiring high battery discharge currents, connect a discrete PMOS switch device and suitabe discharge resistor to the ce, and the gate termina to the S output pin, as iustrated in Figure 11. Si2351DS 33Ω 1W Figure 11. Externa Discharge FET Connection (One Ce Shown) 3.3k F11 Cn Cn 1 POWER DISSIPATION AND THERMAL SHUTDOWN The MOSFETs connected to the Pins S1 through S12 can be used to discharge battery ces. An externa resistor shoud be used to imit the power dissipated by the MOSFETs. The maximum power dissipation in the MOSFETs is imited by the amount of heat that can be toerated by the LTC683. Excessive heat resuts in eevated die temperatures. The eectrica characteristics for the LTC683 I-grade are guaranteed for die temperatures up to 85 C. Litte or no degradation wi be observed in the measurement accuracy for die temperatures up to 15 C. Damage may occur above 15 C, therefore the recommended maximum die temperature is 125 C. To protect the LTC683 from damage due to overheating, a therma shutdown circuit is incuded. Overheating of the device can occur when dissipating significant power in the ce discharge switches. The probem is exacerbated when operating with a arge votage between V and. The therma shutdown circuit is enabed whenever the device is not in standby mode (see Modes of Operation). It wi aso be enabed when any current mode input or output is sinking or sourcing current. If the temperature Sn detected on the device goes above approximatey 145 C, the configuration registers wi be reset to defaut states, turning off a discharge switches and disabing ADC conversions. When a therma shutdown has occurred, the THSD bit in the temperature register group wi go high. The bit is ceared by performing a read of the temperature registers (RDTMP command). Since therma shutdown interrupts norma operation, the interna temperature monitor shoud be used to determine when the device temperature is approaching unacceptabe eves. USING THE LTC683 WITH LESS THAN 12 CELLS If the LTC683 is powered by the stacked ces, the minimum number of ces is governed by the suppy votage requirements of the LTC683. The sum of the ce votages must be 1V to guarantee that a eectrica specifications are met. Figure 12 shows an exampe of the LTC683-4 when used to monitor seven ces. The owest C inputs connect to the seven ces and the upper C inputs connect to C12. Other configurations, e.g., 9 ces, woud be configured in the same way: the owest C inputs connected to the battery ces and the unused C inputs connected to C12. The unused inputs wi resut in a reading of V for those channes. The ADC can aso be commanded to measure a stack of 1 or 12 ces, depending on the state of the CELL1 bit in the contro register. The ADC can aso be commanded to measure any individua ce votage. FAULT PROTECTION Care shoud aways be taken when using high energy sources such as batteries. There are numerous ways that systems can be (mis)configured when considering the assemby and service procedures that might affect a battery system during its usefu ifespan. Tabe 18 shows the various situations that shoud be considered when panning protection circuitry. The first five scenarios are to be anticipated during production and appropriate protection is incuded within the LTC683 device itsef. 3

31 APPLICATIONS INFORMATION NEXT HIGHER GROUP OF 7 CELLS 1 NEXT LOWER GROUP OF 7 CELLS V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 LTC683-4 C6 S6 C5 S5 C4 S4 C3 S3 C2 S2 C1 S1 C F12 Figure 12. Monitoring 7 Ces with the LTC683-4 LTC683-2/LTC683-4 Interna Protection Diodes Each pin of the LTC683 has protection diodes to hep prevent damage to the interna device structures caused by externa appication of votages beyond the suppy rais as shown in Figure 13. The diodes shown are conventiona siicon diodes with a forward breakdown votage of.5v. The unabeed Zener diode structures have a reverse breakdown characteristic which initiay breaks down at 12V then snaps back to a 7V camping potentia. The Zener diodes abeed Z CLAMP are higher votage devices with an initia reverse breakdown of 3V snapping back to 25V. The forward votage drop of a Zeners is.5v. Refer to this diagram in the event of unpredictabe votage camping or current fow. Limiting the current fow at any pin to ±1mA wi prevent damage to the IC. READING EXTERNAL TEMPERATURE PROBES The LTC683 incudes two channes of ADC input, V TEMP1 and V TEMP2, that are intended to monitor thermistors (tempco about 4%/ C generay) or diodes ( 2.2mV/ C typica) ocated within the ce array. Sensors can be powered directy from V REF as shown in Figure 14 (up to 6µA tota). Tabe 18. LTC683 Faiure Mechanism Effect Anaysis SCENARIO EFFECT DESIGN MITIGATION Ce input open-circuit (random) Power-up sequence at IC inputs Camp diodes at each pin to V and (within IC) provide aternate power path Ce input open-circuit (random) Differentia input votage overstress Zener diodes across each ce votage input pair (within IC) imits stress Disconnection of a harness between a group of battery ces and the IC (in a system of stacked groups) Loss of suppy connection to the IC Separate power may be provided by a oca suppy Data ink disconnection between LTC683 and the master Ce-pack integrity, break between stacked units Ce-pack integrity, break within stacked unit Ce-pack integrity, break within stacked unit Loss of seria communication (no stress to ICs) No effect during charge or discharge Ce input reverse overstress during discharge Ce input positive overstress during charge The device wi enter standby mode within 2 seconds of disconnect. Discharge switches are disabed in standby mode Use digita isoators to isoate the LTC683-2/LTC683-4 seria port from other LTC683-2/LTC683-4 seria ports Add parae Schottky diodes across each ce for oad-path redundancy. Diode and connections must hande fu operating current of stack, wi imit stress on IC Add SCR across each ce for charge-path redundancy. SCR and connections must hande fu charging current of stack, wi imit stress on IC by seection of trigger Zener 31

32 LTC683-2/LTC683-4 APPLICATIONS INFORMATION 1 V 2 C12 3 S12 4 C11 5 S11 6 C1 Z CLAMP 7 S1 8 C9 9 S9 1 C8 11 S8 12 C7 13 S7 14 C6 Z CLAMP 15 S6 16 C5 17 S5 18 C4 19 S4 2 C3 21 S3 22 C2 23 S2 Z CLAMP 24 C1 25 S1 26 C For sensors that require higher drive currents, a buffer op amp may be used as shown in Figure 15. Power for the sensor is actuay sourced indirecty from the V REG pin in this case. Probe oads up to about 1mA maximum are supported in this configuration. Since V REF is shut down during the LTC683 ide and shutdown modes, the thermistor drive is aso shut off and thus power dissipation minimized. Since V REG remains aways on, the buffer op amp (LT6 shown) is seected for its utraow power consumption (12µA). 32 Z CLAMP Z CLAMP Z CLAMP 27 NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 27 Figure 13. Interna Protection Diodes LTC683-4 A3 A2 A1 A V REG V REF V TEMP2 V TEMP1 CSBI SDO SDI SCKI GPIO2 GPIO1 WDTB TOS F13 LTC683-4 V REG V REF V TEMP2 V TEMP1 NC Figure 14. Driving Thermistors Directy from V REF LTC683-4 V REG V REF V TEMP2 V TEMP1 NC 1µF 1µF 1k NTC LT6 1k 1k NTC F F15 1k 1k NTC Figure 15. Buffering V REF for Higher Current Sensors Expanding Probe Count As shown Figure 16, a dua 4:1 mutipexer is used to expand the genera purpose V TEMP1 and V TEMP2 ADC inputs to accept 8 different probe signas. The channe is seected by setting the genera purpose digita outputs GPIO1 and GPIO2 and the resutant signas are buffered by sections of the LT64 micropower dua operationa ampifier. The probe excitation circuitry wi vary with probe type and is not shown here. Another method of mutipe sensor support is possibe without the use of any GPIO pins. If the sensors are PN diodes and severa used in parae, then the hottest diode wi produce the owest forward votage and effectivey estabish the input signa to the V TEMP input(s). The hottest diode wi therefore dominate the readout from the V TEMP inputs that the diodes are connected to. In this scenario, the specific ocation or distribution of heat is not known, but such information may not be important in practice. Figure 17 shows the basic concept. In any of the sensor configurations shown, a fu-scae cod readout woud be an indication of a faied-open sensor connection to the LTC683. 1k 1k 1k NTC

33 APPLICATIONS INFORMATION CPO2 GPO1 V REG V TEMP2 V TEMP /2 LT64 7 1/2 LT Y Y2 Y Y3 Y1 INH V EE GND 74HC452 Figure 16. Expanding Sensor Count with Mutipexing LTC683-4 V REG V REF V TEMP2 V TEMP1 NC 2k Figure 17. Using Diode Sensors as Hot Spot Detectors 1µF V CC X2 X1 X X X3 A B 2k F F16 PROBE8 PROBE7 PROBE6 PROBE5 PROBE4 PROBE3 PROBE2 PROBE1 LTC683-2/LTC683-4 ADDING CALIBRATION AND FULL-STACK MEASUREMENTS The genera purpose V TEMP ADC inputs may be used to digitize any signas from V to 4V with accuracy corresponding cosey with that of the ce 1 ADC input. One usefu signa to provide is a high accuracy votage reference, such as 3.3V from an LTC From periodic readings of this signa, the host software can provide correction of the LTC683 readings to improve the accuracy over that of the interna LTC683 reference and/or vaidate ADC operation. Figure 18 shows a means of seectivey powering an LTC from the battery stack, under the contro of the GPIO1 output of the LTC Since the operationa power of the reference IC woud add significant therma oading to the LTC683 if powered from V REG, an externa high votage NPN pass transistor is used to form a oca 4.4V (V be beow V REG ) from the battery stack. The GPIO1 signa contros a PMOS FET switch to activate the reference when caibration is to be performed. Since GPIO signas defaut to ogic high in shutdown, the reference wi automaticay turn off during ide periods. Another usefu signa is a measure of the tota stack potentia. This provides a redundant operationa measurement of the ces in the event of a mafunction in the norma acquisition process, or as a faster means of monitoring the entire stack potentia. Figure 19 shows how a resistive divider is used to derive a scaed representation of a fu ce group potentia. A MOSFET is used to disconnect TOP CELL POTENTIAL CZT5551 LTC683-2 GPIO1 35 V REG 31 V TEMP M Si2351DS 1µF 1µF 1nF LTC SHDN GND V IN V OUT_F GND V OUT_S GND GND F18 Figure 18. Providing Measurement of Caibration Reference 33

34 LTC683-2/LTC683-4 APPLICATIONS INFORMATION CELLGROUP WDTB V REG V TEMP1 CELLGROUP 1 499k 1M 8 1/2 LT64 4 Figure 19. Using a V TEMP Input for Fu-Stack Readings the resistive oading on the ce group when the IC enters standby mode (i.e., when WDTB goes ow). An LT64 micropower operationa ampifier section is shown for buffering the divider signa to preserve accuracy. This circuit has the virtue that it can be converted about four times more frequenty than the entire battery array, thus offering a higher sampe rate option at the expense of some precision/accuracy, reserving the high resoution ce readings for caibration and baancing data N72K 1µF nF F k PROVIDING HIGH SPEED ISOLATION OF THE SPI DATA PORT Isoation techniques that are capabe of supporting the 1Mbps data rate of the LTC683-2/LTC683-4 require more power on the isoated (battery) side than can be furnished by the V REG output of the LTC683-2/LTC To keep battery drain minima, this means that a DC/DC function must be impemented aong with a suitabe data isoation circuit, such as shown in Figure 2. A quad (3 1) data isoator Si8441AB-C-IS is used to provide non-gavanic SPI signa connections between a host microprocessor and an LTC683-2/LTC An inexpensive isoated DC/ DC converter provides powering of the isoator function competey from the host 5V power suppy. A quad threestate buffer is used to aow SPI inputs at the LTC683-2/ LTC683-4 to rise to a ogic high eve when the isoator circuitry powers down, assuring the owest power consumption in the standby condition. The pu-ups to V REG are seected to match the interna oading on V REG by ICs operating with a current mode SPI interface, thus baancing the current in a ces during operation. The additiona pu-up on the SDO ine (1k resistor and Schottky diode) is to improve rise time, in ower data rate appications this may not be needed. 5V_HOST SPI_CLOCK SPI_CHIPSELECT SPI_MASTEROUT SPI_MASTERIN GND_HOST 47pF 2.k 1Ω 1Ω 1Ω 1Ω 1µF 1µF 1 LTC IN1 V CC1 2 7 GND1 OUT1 3 6 IN2 V CC2 4 5 GND2 OUT2 Si8441AB-C-IS QUAD ISOLATOR V DD1 GND1 A1 A2 A3 A4 EN1 GND1 V DD2 GND2 B1 B2 B3 B4 EN2 GND nF PE µF BAT54S CMDSH /4 74ABT /4 74ABT k 1/4 74ABT /4 74ABT126 74ABT126 SUPPLY SHARED WITH ISOLATOR V DD2 and GND2 4.22k 4.22k 4.22k 4.22k F2 V REG SCKI CSB1 SCI SDO 1.k Figure 2. Providing an Isoated High Speed Data Interface 34

35 LTC683-2/LTC683-4 APPLICATIONS INFORMATION SUPPLY DECOUPLING IF BATTERY-STACK POWERED As shown in Figure 21, the LTC683-4 can have fitering on both V and, so differentia bypassing to the ce group potentias is recommended. The Zener suppresses overvotages from reaching the IC suppy pins. A sma ferrite-bead inductor provides protection for the Zener, particuary from energetic ESD strikes. Since the LTC683-2 cannot have a series resistance to, additiona Schottky diodes are needed to prevent ESD-induced reverse-suppy (substrate) currents to fow. ADVANTAGES OF KELVIN CONNECTION ON C The trace resistance can cause an observabe votage drop between the negative end of the bottom battery ce and pin of LTC683. This votage drop wi add to the measurement error of the bottom ce votage. The LTC683 4 separates C from, aowing Kevin connection on C as shown in Figure 22. Votage drop on the trace wi not affect the bottom ce votage measurement. The Kevin connection wi aso aow RC fitering on as shown in Figure 21. CELLGROUP BLM31PG33SN1L 1Ω V CELLGROUP CMHZ5265B BAT46W LTC683-2 Configuration 1nF F21 CELLGROUP BLM31PG33SN1L 1Ω V CELLGROUP CMHZ5265B 1nF 1Ω LTC683-4 Configuration Figure 21. Suppy Decouping BATTERY STACK R I SUPPLY LTC683-4 C1 C 6834 F2 Figure 22. Kevin Connection on C Improving Bottom Ce Votage Measurement Accuracy 35

36 LTC683-2/LTC683-4 APPLICATIONS INFORMATION HARDWARE SHUTDOWN To competey shut down the LTC683 a PMOS switch can be connected to V, or, V can be driven from an isoated power suppy. Figure 23 shows an exampe of a switched V. The breakdown votage of DZ4 is about 1.8V. If SHDN < 1.8V, no current wi fow through the stacked MMBTA42s and the 1M resistors. TP61Ks wi be competey shut off. If SHDN > 2.5V, M7 wi be turned on and then a TP61Ks wi be turned on. separation of traces at different potentias. The pinout of the LTC683 was chosen to faciitate this physica separation. There is no more than 5.5V between any two adjacent pins. The package body is used to separate the highest votage (e.g., 43.2V) from the owest votage (V). As an exampe, Figure 24 shows the DC votage on each pin with respect to when tweve 3.6V battery ces are connected to the LTC683. LTC683-4 IC #3 V C12 C V C12 LTC683-4 IC #2 C TP61K TP61K DZ1 15V DZ2 15V 1M D1 1M D2 43.2V 43.2V 43.2V 39.6V 39.6V 36V 36V 32.4V 32.4V 28.8V 28.8V 25.2V 25.2V V 18V 14.4V 14.4V V C12 S12 C11 S11 C1 S1 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 CSBI SDO SDI SCKI A3 A2 A1 LTC683-4 A GPIO2 GPIO1 WDTB TOS V REG V REF V TEMP2 V TEMP1 NC C S1 C1 S2 V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V V TO 5.5V 5V 3.1V 1.5V 1.5V V V V 3.6V 3.6V 7.2V LTC683-4 IC #1 Figure 23. Hardware Shutdown Circuit Reduces Tota Suppy Current of LTC683-4 to About µa 36 V C12 C TP61K DZ3 15V 1M SHDN DZ4 1.8V DZ1, DZ2, DZ3: MMSZ5245B DZ4: MMSZ4678T1 5k ALL NPN: MMBTA42 ALL PN: RS7J F23 PCB LAYOUT CONSIDERATIONS The V REG and V REF pins shoud be bypassed with a 1µF capacitor for best performance. The LTC683 is capabe of operation with as much as 55V between V and. Care shoud be taken on the PCB ayout to maintain physica F24 Figure 24. Typica Pin Votages for Tweve 3.6V Ces ADVANTAGES OF DELTA-SIGMA ADCS The LTC683 empoys a deta-sigma anaog-to-digita converter for votage measurement. The architecture of deta-sigma converters can vary consideraby, but the common characteristic is that the input is samped many times over the course of a conversion and then fitered or averaged to produce the digita output code. In contrast, a SAR converter takes a singe snapshot of the input votage and then performs the conversion on this singe sampe. For measurements in a noisy environment, a deta-sigma converter provides distinct advantages over a SAR converter. Whie SAR converters can have high sampe rates, the fupower bandwidth of a SAR converter is often greater than

37 APPLICATIONS INFORMATION 1MHz, which means the converter is sensitive to noise out to this frequency. And many SAR converters have much higher bandwidths up to 5MHz and beyond. It is possibe to fiter the input, but if the converter is mutipexed to measure severa input channes a separate fiter wi be required for each channe. A ow frequency fiter cannot reside between a mutipexer and an ADC and achieve a high scan rate across mutipe channes. Another consequence of fitering a SAR ADC is that any noise reduction gained by fitering the input cances the benefit of having a high sampe rate in the first pace, since the fiter wi take many conversion cyces to sette. For a given sampe rate, a deta-sigma converter can achieve exceent noise rejection whie setting competey in a singe conversion something that a fitered SAR converter cannot do. Noise rejection is particuary important in high votage switching controers, where switching noise wi invariaby be present in the measured votage. Other advantages of deta-sigma converters are that they are inherenty monotonic, meaning they have no missing codes, and they have exceent DC specifications. Converter Detais The LTC683 ADC has a 2nd order deta-sigma moduator foowed by a SINC2, finite impuse response (FIR) digita fiter. The front-end sampe rate is 512ksps, which greaty reduces input fitering requirements. A simpe 16kHz, 1-poe fiter composed of a 1Ω resistor and a.1 F capacitor at each input wi provide adequate fitering for most appications. These component vaues wi not degrade the DC accuracy of the ADC. Each conversion consists of two phases an autozero phase and a measurement phase. The ADC is autozeroed at each conversion, greaty improving CMRR. The second haf of the conversion is the actua measurement. Noise Rejection Figure 25 shows the frequency response of the ADC. The ro-off foows a SINC2 response, with the first notch at 4kHz. Aso shown is the response of a 1 poe, 85Hz fiter LTC683-2/LTC683-4 (187µs time constant) which has the same integrated response to wideband noise as the LTC683 ADC, which is about 135Hz. This means that if wideband noise is appied to the LTC683 input, the increase in noise seen at the digita output wi be the same as an ADC with a wide bandwidth (such as a SAR) preceded by a perfect 135Hz brick wa owpass fiter. Thus if an anaog fiter is paced in front of a SAR converter to achieve the same noise rejection as the LTC683 ADC, the SAR wi have a sower response to input signas. For exampe, a step input appied to the input of the 85Hz fiter wi take 1.55ms to sette to 12 bits of precision, whie the LTC683 ADC settes in a singe 1ms conversion cyce. This aso means that very high sampe rates do not provide any additiona information because the anaog fiter imits the frequency response. Whie higher order active fiters may provide some improvement, their compexity makes them impractica for high channe count measurements as a singe fiter woud be required for each input. Aso note that the SINC2 response has a 2nd order rooff enveope, providing an additiona benefit over a singe poe anaog fiter. FILTER GAIN (db) k 1k FREQUENCY (Hz) 1k F25 Figure 25. Noise Fitering of the LTC683-4 ADC 37

38 LTC683-2/LTC683-4 PACKAGE DESCRIPTION G Package 44-Lead Pastic SSOP (5.3mm) (Reference LTC DWG # Rev Ø) 1.25 ± * ( ) ( ).25 ±.5 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED.5 BSC * ( ) (.65.73) 2. (.79) MAX PARTING LINE.1.25 (.4.1).55.95** (.22.37) 1.25 (.492) REF 8 NOTE: 1.DRAWING IS NOT A JEDEC OUTLINE 2. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 3. DIMENSIONS ARE IN (INCHES) 4. DRAWING NOT TO SCALE 5. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN.8mm AT SEATING PLANE.5 (.1968) BSC.2.3 (.8.12) TYP * DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS, BUT DO INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH SHALL NOT EXCEED.15mm PER SIDE ** LENGTH OF LEAD FOR SOLDERRING TO A SUBSTRATE THE MAXIMUM DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSIONS DO NOT EXCEED.13mm PER SIDE.5 (.2) MIN G44 SSOP 67 REV Ø SEATING PLANE 38

39 LTC683-2/LTC683-4 REVISION HISTORY REV DATE DESCRIPTION PAGE NUMBER A 8/12 Carification to UV/OV Operation 15 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 39

40 LTC683-2/LTC683-4 TYPICAL APPLICATION CELL 12 Typica 12-Ce Measurement Bock MMSZ5267B IMC121ER1K BAT46W BAT46W 1Ω 1M 1M 1M 1 LTC683-2 V 44 CSBI nF C12FILTER C12 SDO 3 42 DC12 S12 SDI 4 41 C11FILTER C11 SCKI 5 4 DC11 S11 A C1FILTER C1 A DC1 S1 A C9FILTER C9 A M DC9 S9 GPIO M C8FILTER C8 GPIO DC8 S8 WDTB REPEAT INPUT CIRCUITS C7FILTER C7 NC 1M FOR CELL3 TO CELL DC7 S7 TOS C6FILTER C6 V REG 15 3 DC6 S6 V REF C5FILTER C5 V TEMP DC5 S5 VTEMP C4FILTER C4 NC 19 DC4 S C3FILTER C3 S DC3 S3 C C2 S2 CELL2 CELL1 33Ω RQJ33PGDQALT 475Ω RQJ33PGDQALT 3.3k 1Ω 1Ω 1nF 1nF C2FILTER PDZ7.5B C1FILTER PDZ7.5B CSBI SDO* SDI SCKI 1µF 1µF SPI PORT TO HOST µp OR DATA ISOLATOR *REQUIRES 1K PULL-UP RESISTOR AT HOST DEVICE /2 LT /2 LT k 1.k NTC2 1k 1nF NTC1 1k 1nF TA2 33Ω 475Ω 3.3k RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC681 Independent Mutice Battery Stack Faut Monitor Monitors Up to 12 Series-Connected Battery Ces for Undervotage or Overvotage. Companion to the LTC682 and LTC683 famiy LTC682-1 Mutice Battery Stack Monitor with Parae Addressed Seria Interface Functionay Equivaent to the LTC683-1 and the LTC683-3 LTC682-2 LTC683-1/ LTC683-3 Mutice Battery Stack Monitor with an Individuay Addressabe Seria Interface Mutice Battery Stack Monitor with Daisy-Chained Seria Interface Functionay Equivaent to LTC683-2/LTC Pin Compatibe with the LTC683-2 Functionaity Equivaent to LTC683-2/LTC683-4, Aows for Mutipe Devices to Be Daisy Chained 4 LT 812 REV A PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION 211