System-in-Package (SiP): A Guide for Electronics Design Engineers Task 2: Reporting - Report No. 3 SiP Design Routes, Guidance, Future Trends

18333/3/09 June 2009 System-in-Package (SiP): A Guide for Electronics Design Engineers Task 2: Reporting - Report No. 3 SiP Design Routes, Guidance, Future Trends For: The Electronics Knowledge Transfer Network

System-in-Package (SiP): A Guide for Electronics Design Engineers Task 2: Reporting - Report No. 3 SiP Design Routes, Guidance, Future Trends TWI Report 18333/3/09 June 2009 Prepared for: The Electronics Knowledge Transfer Network 10-12 Russel Square London WC1B 5EE Contact: Ashley Evans Author: Dr David Pedder TWI Endorsement This report has been reviewed in accordance with TWI policy. Project Leader. (Signature) TGM/Reviewer.. (Signature) Print name: Dr David Pedder Print name: Alec Gunner Secretary/Administrator (Signature) Print name: Gillian Dixon-Payne gdp Copyright EKTN, TWI 2009

Contents Executive Summary Background Objectives Work Carried Out Conclusions 1 Introduction 1 2 Objectives 1 3 Approach 1 4 SiP Design Routes 2 4.1 SiP technologies, applications, design team 2 4.2 SiP RF/analogue design 4 4.3 SiP digital design 8 4.4 SiP design tools 11 5 SiP Design Guidance 12 6 SiP Future Trends 13 7 Conclusions 14 8 References 14 9 Acknowledgements 14 18333/3/09 Copyright EKTN, TWI 2009

Executive Summary Background The past decade has seen the emergence of a range of system-in-package (SiP) technologies driven by the relentless demands of the portable and consumer electronics industry for ever-greater product functionality and for improved performance at ever-reducing costs. SiP technologies provide a system or sub-system level of functionality within a single package outline, combining multiple integrated circuit die with passive and other supporting components. This project was established to provide an overview of SiP technologies and trends with a focus on SiP design. Objectives The objectives of this SiP Design Guide for Electronics Engineers Project were as follows: To introduce the range of SiP technologies in current application. To review the benefits of SiP technology. To provide examples of SiP applications. To set out the available design routes, design tools for SiP. To provide initial guidance for UK engineers wishing to embark on SiP design. To outline future trends in SiP technology and applications. Work Carried Out This third and final report addresses the last three project objectives, ie to set out the available design routes for SiP, to provide initial guidance for UK engineers wishing to embark on SiP design and to outline future trends in SiP technology and applications. Conclusions 1 The available design routes and design tools for SiP have been described. 2 Initial guidance has been provided for UK engineers wishing to embark on SiP design. 3 Future trends in SiP technology and applications have been discussed. 18333/3/09 Copyright EKTN, TWI 2009

1 Introduction The past decade has seen the emergence of a range of system-in-package (SiP) technologies driven by the relentless demands of the portable and consumer electronics industry for ever-greater product functionality and for improved performance at everreducing costs. SiP technologies provide a system or sub-system level of functionality within a single package outline. SiP combines single die or multiple, mixed technology die with passive and other supporting components. The ability to integrate devices and to mix technologies within a standard package format can lead to smaller footprints than standard SMT implementations, and to improved performance, lower NREs and reduced new product introduction (NPI) cycle times when compared with the system-on-chip (SoC) option and to reduced product function level costs savings. The principal categories of SiP technologies include planar and stacked die SiPs, in 2D and 3D configurations that employ wire bond, flip chip, and solder ball and through-silicon-via (TSV) interconnection structures. A range of SiP packaging platforms are employed that include leadframe, LTCC, laminate and thin film substrate options, the latter three categories being with or without integrated passive components. One of the key barriers to the further take-up of SiP technologies has been the availability of design tools and robust design routes to ensure right-first-time design and minimal NPI cycle times. The latter is of particular relevance when integrated passives components are included since design iteration cycle times tend to be greater than for SMT passives. Design-for-test, for reliability, thermal design and a number of other design dimensions are also of particular relevance for SiP design. The provision of this SiP technology overview, design routes, applications and design guidance for the UK Design Community is intended to play to a key UK strength and to assist in the capture of significant added value for this industry sector. 2 Objectives The objectives of this SiP Design Guide for Electronics Engineers Project were as follows: To introduce the range of SiP technologies in current application. To review the benefits of SiP technology. To provide examples of SiP applications. To set out the available design routes, design tools for SiP. To provide initial guidance for UK engineers wishing to embark on SiP design. To outline future trends in SiP technology and applications. This third and final report addresses the last three project objectives, ie to set out the available design routes for SiP, to provide initial guidance for UK engineers wishing to embark on SiP design and to outline future trends in SiP technology and applications. 3 Approach The approach being adopted in this Design Guide project has involved a combination of networking activities and interviews with key SiP technology and applications experts in the UK, Europe and the USA. The project has also drawn upon the current TSB project, ADEPT-SiP, that is developing design routes for pcb-based SiP technology, which is being 18333/3/09 1 Copyright EKTN, TWI 2009

lead by TWI. Contacts from recent SiP and packaging seminars organised by TWI and NMI were also used to provide technology, design and applications data for this EKTN project. The results of the above interviews, together with SiP literature data and background data have been coordinated and compiled into a set of two interim reports and a final report, together with a set of supporting presentations that will be converted to webinars by the EKTN. This work has been completed over the thirteen month project period from May 2008 to June 2009. SiP networking and interview activities in 2008 included organisation and co-chairing of the joint NMI/TWI Design for SiP seminar at TWI, visits to IMEC in Leuven, participation in the inemi Roadmap European Workshop meeting in Germany in June, visits to NXP in Caen and to STMicroelectronics in Tour in July, attendance at the ESTC conference in Greenwich in September and a visit to Unisem in the UK in November. Related SiP networking and interview activities in 2009 included visits to TechSearch International, Skyworks and RFMD and discussions with Amkor in the USA in February, the organisation of a joint NMI/TWI Packaging Roadmap seminar held at TWI in April and discussions with AWR, Plextek, Cadence, Ansoft and Agilent in the UK in April and May. 4 SiP Design Routes 4.1 SiP technologies, applications, design team The SiP concept by definition integrates together a very wide range of different device and component technologies. These device and component technologies may include a range of three-five device (GaAs, InP etc), and silicon device technologies (CMOS, Bipolar, BiCMOS, SoI etc), passive component technologies (resistors, capacitors and inductors), passive network (filters, baluns, antennas) and/or mechanical and/or optical component technologies (MEMS, MOEMS, photonics devices). These various categories of SiP technologies are also employed across a very broad range of applications as revealed in the results of the earlier SiP applications survey. These applications include mobile phone, PA/RF modules and other wireless applications, camera modules, consumer products, audio visual, network and computing products, domestic products, automotive products, medical electronics, defence and aerospace applications. The design routes for SiP are therefore required to support this very mixed technology and mixed applications environment. Fortunately the SiP design routes may be divided into two broad categories, namely RF/analogue design routes and digital design routes. Certain high end modules may also combine elements of both categories. In either case it is important to establish an appropriate SiP design team and a full supply chain infrastructure before initiating a specific SiP product design. Again it should be born in mind that the SiP design activity is just one part of a company s new product introduction (NPI) cycle with its associated review and gating procedures as illustrated schematically in Figure 1. 18333/3/09 2 Copyright EKTN, TWI 2009

Opportunity evaluation SiP sampling Gate 1 Business case Gate 5 SiP sale Gate 2 SiP design Gate 6 SiP production Gate 3 Prototype build Gate 7 Project closure Gate 4 Figure 1 SiP design within the SiP NPI cycle. A successful SiP design project team should include at least one system expert, one or more IC/MEMS experts (depending upon the mix of IC and MEMS technologies), one passive integration expert and one packaging platform/module expert. The supply chain partners in a SiP design and manufacture programme will typically include the end user, the IC/MEMS house (or houses ), the IPD company, the packaging platform supplier company, the packaging and test house, an independent design house and/or a functional block specialist company. The SiP design activity may be undertaken by any one of the various companies within the supply chain, but is most commonly undertaken by the IC house, the packaging and test house, by an independent design house and/or a functional block specialist company, in all cases in close consultation with the end user. The typical SiP supply chain is illustrated schematically in Figure 2. IC manufacturer 1, 2 MEMS manufacturer SiP designer IPD manufacturer SiP assembly & test house SiP end user SiP packaging platform manufacturer Figure 2 A typical SiP supply chain. 18333/3/09 3 Copyright EKTN, TWI 2009

The establishment of a full set of SiP supply chain options is an essential prerequisite to the initiation of a SiP design and in particular should include access to the required range of packaging platform technologies, ie leadframe, LTCC, laminate and thin-film technologies. The SiP design team should also establish and maintain a living database of SiP technology design rules, performance and cost metrics. Important technology selection and partitioning decisions have to be taken in the early stages of the SiP design cycle that will have a vital impact on the costs and performance of the final SiP product. As in many product design situations, some eighty percent of the final product cost is typically determined in the first twenty percent of the design cycle. The choice of packaging platform is a key determiner of the final SiP size, weight, performance and cost and a careful comparison of the impact of different packaging platforms is therefore an important early phase design activity. 4.2 SiP RF/analogue design The key steps in the SiP design flow for RF/analogue product design are illustrated schematically in Figure 3 below. System specification Physical layout & circuit design Design rules System design & partitioning Design for manufacture, test Component & layout libraries RF/analogue circuit design System verification & design variants Models Analysis Design rule & layout checking Optimisation System fabrication, test & verification Figure 3 SiP design flow for RF/analogue product design. The SiP design flow commences with the generation of the system specification, for a custom product this being generated by the end user or, for a standard product, being derived from the relevant standards body documentation. The system architecture and its constituent functional blocks (amplifiers, filters, mixers, AGC etc) are then captured and candidate active device and passive component technologies evaluated and selected for the implementation of the various functional blocks. As noted earlier, this system technology partitioning exercise is the key to determining the size, weight, cost and performance of the final SiP product and must therefore be conducted with due care and attention, taking into proper account the end user and market requirements. Where the SiP database allows, active device, passive component and IPD and packaging platform floorplans should be generated and initial area and cost estimates made to guide the partitioning process. For the LTCC and laminate packaging platforms layer count estimates should also be generated since costs very much scale with layer count. The confirmation of the SiP partitioning also requires supply chain verification and the clear definition of 18333/3/09 4 Copyright EKTN, TWI 2009

responsibilities, known-good-die (KGD) and known-good-substrate (KGS) delivery and related requirements. A WLAN functional block diagram showing an example of passive filter function technology partitioning is presented in Figure 4 below (after Gaynor, see references). Diplexer Laminate Filter DPDT Diplexer LTCC IPD Balun Balun RFPA RFPA Transceiver Figure 4 WLAN functional block diagram showing passive filter technology partitioning. System architectural simulations for budget and spurious signal analysis, adjacent channel power ratio (ACPR), error vector magnitude (EVM) and bit error rate (BER) are also an important part of the top-level system design. Once the system specification and technology partitioning has been completed then RF/analogue circuit design and simulation can commence using the proposed circuit topologies and the appropriate technology process design kits (PDKs). The PDKs will contain the technology definition, layer allocations, device footprints and models for a given technology. The PDK will normally be supplied and supported by the technology supplier company and may include fixed or parameterised component footprint and models, the latter allowing effective circuit optimisation. Modern design tools also support the use of multiple PDKs within a single design environment which also facilitates more detailed design partitioning, for example in the allocation of a choke inductor component to an IC technology, to the silicon IPD, to the laminate substrate environment or as a discrete SMT component. The support for multiple PDKs also allows a true chip-package co-design approach which is vital for overall design optimisation. Packaging platform and IPD PDKs are particularly relevant where integrated passive components are involved (LTCC, laminate and thin-film platforms). In cases where PDKs are not available or appropriate then full 3D electromagnetic (EM) simulation may employed, albeit with an associated time penalty. An example of a mixed technology module integrating GaAs and silicon active devices on a laminate substrate using multiple PDKs is illustrated in Figure 5. 18333/3/09 5 Copyright EKTN, TWI 2009

Figure 5 Mixed technology module integrating GaAs and silicon active devices on a laminate substrate using multiple PDKs (courtesy of AWR). Initial circuit design and simulation is followed by parametric optimisation to obtain the specified performance from the circuit. A preliminary tolerancing analysis is then performed to establish the circuit sensitivity to known process variations and, if successful, a primary layout is produced. The layout process may produce deviations from the initial schematic design as component positions and interconnect lengths are adjusted to minimise circuit area (and hence cost). The altered circuit design is then fed back into the simulation and the design and layout are iterated until they converge to give the required performance. This approach results in well characterised designs optimised for both performance and cost. Packaging platform interconnect structures for RF/analogue SiP implementation may be modelled using microstrip, co-planar waveguide (CPW) and stripline formats that may be supported within the technology PDK and simulated using standard RF and microwave simulation tools. EM modelling or equivalent circuit extraction methods may also be employed for the analysis of multiple interconnection structures. Other key aspects of SiP design, including design for manufacture, test, EMC and shielding, reliability and thermal design should be addressed in detail at this stage in the design flow. A preliminary thermal design study at the earlier technology partitioning and floor-planning stage is also recommended to ensure that the choice of packaging platform meets the required thermal performance. This is of particular importance for SiP designs that include power amplifier devices. SiP designs by definition involve much higher levels of functional density than achieved with single chip packaging on standard PCBs. A detailed thermal design study is therefore also required at this stage of the design flow, in particular predicting active device junction temperatures and identifying thermal hot spots in the 2D and 3D device assemblies at the application operating temperature extremes. Many aspects of SiP design for manufacture will have been taken care of automatically through the use of technology PDKs that include design rule compliant component footprint generation. Manufacturability from a SiP assembly perspective can also be incorporated into technology PDKs in the form of die attach, wire bond, flip chip and solder ball pad designs and through the incorporation of keep-out structures in the active die footprints to allow for die-to-die clearances, underfill dispense needle access, underfill capillary profiles and related assembly requirements. The ability to inspect 3D views of the SiP design and layout can also be used to check wire bond array structures, die stacking and overmoulding clearances. 18333/3/09 6 Copyright EKTN, TWI 2009

Design for test is also a very important SiP design parameter. The high level of RF/analogue functionality inherent in a SiP module design significantly increases the level of functional test complexity and test time over that for a single device or functional block. Test programme generation should therefore start to be addressed as part of the system architecture design phase. Additional test point access should be built into the SiP packaging platform as required to set the SiP die into test mode. The requirements for KGD and KGS should also be defined and appropriate test programmes generated. This is of particular importance where the packaging platform substrate includes integrated passive components. While SiP product designs containing a single die and a low other component count may not require the use of KGD, the reverse is the case for the majority of SiP products. The close proximity of the different RF functional blocks in a typical RF SiP also calls for careful analysis of EMC performance and the design and integration of any necessary shielding structures using appropriate 3D EM modelling techniques. The ability to integrate shielding structures into a SiP build-up can remove the need for metal can shielding structures at the motherboard level and represents a further benefit of the SiP concept. Equally the general reduction in interconnection loop lengths in a SiP module, when compared with a conventional single chip packaged board level design, leads to reduced levels of EM emission. The design for reliability aspect of SiP design reflects the unique combinations of mixed technology active and passive devices integrated together in both 2D and 3D configurations using a range of interconnection structures onto a given packaging platform base. SiP reliability is also determined by the subsequent demands of SiP module assembly onto the full system motherboard (particularly the multiple solder reflow processes involved) and by the application service environment. Extensive reliability proving and qualification testing will have been undertaken across the SiP supply chain for a representative mix of device technologies, assembly and interconnection structures and packaging platforms, particularly by the SiP assembly and test house. This reliability data will have been employed as part of the design partitioning and technology selection process earlier in the design flow. Once the SiP design is completed any unproven or novel technology combinations should be identified, reliability modelling (using FEA and related techniques) should be conducted and full reliability qualification testing undertaken for every new SiP product using prototype samples. Once the primary SiP design is completed a rigorous process of design verification and design reviews should be undertaken, including design rule checking (DRC) and layout versus schematic (LVS). Centred and frequency shifted design variants should be included in the mask designs for first SiP prototype manufacture, together with a full set of the individual functional blocks that make up the complete SiP module. The inclusion of design variants maximises the chances of a first time functional SiP and allows an evaluation of manufacturing tolerance sensitivity. The availability of the individual functional blocks allows analysis of the contributions of each block to the overall SiP performance, assists debugging, future design iterations and technology/design re-use. Each SiP design, its design variants and functional block specifications, simulation results and layouts should be carefully and fully documented at this stage. Once a SiP design has been completed and signed off, then the design may be dumped, masks, devices, components and packaging platforms procured and the first SiP modules, design variants and functional blocks manufactured, assembled and tested. SiP modules and design variants should be tested for compliance and best fit to the SiP specification and 18333/3/09 7 Copyright EKTN, TWI 2009

for design sensitivity and indicative yield. SiP performance should be reviewed and design iterations initiated as required. An example of the layout and measured versus simulated performance on first lot manufacture for an RF filter functional block designed in a thin-film SiP substrate technology using a technology PDK is illustrated in Figure 6. This filter was designed for an operational frequency of 0.9GHz, an insertion loss of less than 0.7dB, return loss of over 15.0dB and out of band attenuation response of over 30dB@ 1.8GHz and at 2.7GHz. This simple example illustrates the basic robustness of this RF/analogue SiP design flow. Figure 6 Thin film RF filter lay out, simulated and measured performance (courtesy of Dow). 4.3 SiP digital design The design flow for digital SiP design has many similar stages to that employed for RF/analogue SiP design, but is concerned with very much higher device IO counts and consequently with much greater routing demands. The design flow emphasis is therefore on optimal chip placement and/or chip stacking, IO allocation and driver/receiver optimisation and with chip level redistribution layer and packaging platform substrate routing optimisation. A schematic digital SiP design flow is presented in Figure 7 below. 18333/3/09 8 Copyright EKTN, TWI 2009

System specification Physical layout & system simulation Design rules System synthesis & design partitioning Design for manufacture, test Component & layout libraries Digital circuit design System verification & design variants Models Connectivity analysis Design rule & layout checking Placement, IO and routing optimisation System fabrication, test & verification Figure 7 SiP design flow for digital product design. The digital SiP design flow again commences with the generation of the system specification, for a custom product this being generated by the end user or, for a standard product, being derived from the relevant standards body documentation. The digital SiP design will typically involve a chip set providing processor and memory device functionality and employing leading edge CMOS process technology to deliver the required gate counts in the smallest possible device footprints. The system level simulation and active device technology partitioning phase of the design flow will result in a SiP functional block diagram defining the chip boundaries, IO designations and chip-to-chip and external SiP interface interconnection netlists. Critical nets and differential pairs within the interconnection netlists will also have been identified. This activity is followed by the selection and evaluation of candidate chip placement architectures (2D or 3D), chip-to-chip, chip-to-substrate interconnection technologies and packaging platform substrate options. These structures and technologies are assessed to confirm they can support the required routing demands and feasible options selected for a range of SiP floorplans. Trade-off analysis is then conducted to short list preferred SiP architectures and floorplans. For the digital SiP design scenario where new IC designs are involved or where IC design involves a proven core but with new IO designation and placement, then the next SiP design phase involves a true chip-package co-design activity. Here the chip IO cell placements are optimised in order to minimise the number of packaging platform substrate routing layers required to route the design (for cost minimisation), and to minimise the total Manhattan routing length and the number of trace crossings (for maximum performance). Higher IO count silicon devices (over 500 IOs) will commonly employ area array flip chip connections from the chip to the substrate level and the associated chip IO placement and the bump array IC back-end redistribution layer routing will also require careful optimisation. Driver and receiver IO buffer designs will be optimised based on the actual SiP trace loadings. Signal integrity, propagation delays, ground bounce and IO performance as a 18333/3/09 9 Copyright EKTN, TWI 2009

function of load conditions will also be simulated prior to final layout. The final layout will involve bare die or CSP die footprint capture, active device and integrated passive, IPD and/or discrete passive device footprint placement and full trace and wire bond 3D routing. Packaging platform substrate integrated passive device configurations will vary from those employed in RF/analogue applications with a greater emphasis on pull-up/pull-down resistor utilisation and larger area, higher value distributed capacitance planes for device decoupling. As with the RF/analogue SiP design flow, other key aspects of SiP design, including design for manufacture, test, EMC and shielding, reliability and thermal design should be addressed in detail at this stage in the design flow. IO test bench design development can be conducted for downstream design layout and verification. Die and SiP level testability can be readily built into digital SiP modules using JTAG boundary scan technologies. Once the primary SiP design is completed a rigorous process of design verification and design reviews should again be undertaken, including DRC and LVS. The digital nature of the digital SiP module design by definition gives less scope for the inclusion of centred and frequency shifted design variants, but variants relating to decoupling or screening structures may be possible. Once a SiP design has been completed and signed off, then the design may be dumped, masks, devices, components and packaging platforms procured and the first SiP modules and any design variants manufactured, assembled and tested. SiP modules and design variants should be tested for compliance and best fit to the SiP specification and for design sensitivity and indicative yield. SiP performance should be reviewed and design iterations initiated as required. An example of CPU, Southbridge and EEPROM plus DDRII memory digital SiP laminate packaging platform substrate layout after co-design completion is illustrated in Figure 8. Here an original board level design involving two packaged devices on a 6-layer build-up pcb with 88 discrete passive components capable of performance to 133/166MHz was replaced after chip-package co-design by a digital SiP solution involving all bare die, a 4- layer build-up laminate substrate and a design capable of performance to 166/200MHz. See references. 18333/3/09 10 Copyright EKTN, TWI 2009

Figure 8 Co-designed CPU, chip set and memory digital SiP substrate layout (courtesy of ASE). 4.4 SiP design tools Design tools that may be employed in the various stages of SiP design, simulation and layout are available from a number of sources, including companies such as Applied Wave Research (AWR), Agilent, Ansoft, Cadence, Zuken and many others. The SiP designer s choice of design tools will once again vary according to their position in the SiP supply chain and their technology interests and background. The tools employed will thus reflect whether the SiP design is undertaken by the IC or MEMS house, the packaging and test house, by an independent design house and/or a functional block specialist company. Again different tools will commonly be employed for RF/analogue and for digital SiP IC and for MEMS device design, for IPD and for packaging platform design, requiring in turn robust, and ideally bi-directional interfacing between the different design tools. Other SiP design parameters such as design for manufacture, test, EMC and shielding, reliability and thermal design may again call for the use of different design tools, for example involving thermo-mechanical modelling using finite element analysis (FEA) methods. This report cannot and should not advise on the selection of particular design tool suppliers and the reader is advised to contact these and other suppliers to make their own tools selections. However the main SiP-related design tools and their capabilities for the companies listed above are summarised below for information. Applied Wave Research (AWR): AXIEM TM, Microwave Office TM (MWO), Analog Office TM (AO), Visual System Simulator TM (VSS), 3D planar EM simulation, component level circuit simulation, system simulation, circuit synthesis, support for multiple GaAs and Si PDKs with verification (DRC, LVS, ERC), circuit trace extraction, bi-directional links to PDB design tools for integrated design and manufacturing. Agilent:: Advanced Design System (ADS), Momentum, SystemVue, SpectraSys, Ptolemy, system and algorithm level design and verification, schematic design and verification, 18333/3/09 11 Copyright EKTN, TWI 2009

RFIC/MMIC design using PDKs, physical component design, layout, EMDS, AMDS, EM verification, DRC and physical verification, signal and power integrity analysis. Ansoft: HFSS, Q3D Extractor, SIWave, TPA, ephysics, 3D geometry full-wave electromagnetic field solver, parameter extraction, signal and power integrity analysis, coupled thermal and stress analysis, links to CAD and EDA tools including Cadence, Mentor, Zuken. Cadence: Cadence Virtuoso, Cadence Allegro, Allegro Package Designer, Allegro Package SI, 3D Design Viewer, RF and Digital SiP Architect, Layout, Signal Integrity. Chip-package co-design, physical, electrical and costs trade-off analysis, 3D visualisation and wirebond DRC, IO pad ring optimisation, signal integrity analysis. Zuken: CR-5000, System Designer, Constraint Manager, Lightning. Right-first-time laminate packaging platform design capture, layout and verification, including embedded passives. A number of these CAD and EDA tool suppliers also provide useful SiP case studies and design flow information that can assist in the choice of SiP design flow and design tools. 5 SiP Design Guidance Many of the recommended first steps for UK engineers wishing to embark on SiP design have been addressed in preceding sections of this report. These and other recommended key first steps towards building up an effective SiP design capability include: 1 Establishing the SiP design project team. This team should include at least one system expert, one or more IC/MEMS experts (depending upon the mix of IC and MEMS technologies), one passive integration expert and one packaging platform/module expert. 2 Establishing the SiP supply chain and understanding the designer s position within this supply chain. Setting up a full set of SiP supply chain options is an essential prerequisite to the initiation of a SiP design and in particular should include access to the required range of packaging platform technologies, ie leadframe, LTCC, laminate and thin-film technologies. 3 Establishing the required design tools, design flow(s), design review and documentation procedures for new SiP product design, development and manufacture as part of the SiP designers NPI business procedures. 4 Establishing and maintaining a living database of SiP technology design rules, performance and cost metrics to facilitate the important technology selection and partitioning decisions that have to be taken in the early stages of the SiP design cycle. 5 Undertake a series of SiP design exercises to build up relevant design capabilities and in particular to develop experience in SiP technology selection and design partitioning. These early design exercises should focus on designs of modest functional complexity (eg VCOs, PA/LNA modules rather than complete transceivers). Translations of existing, board-level designs can provide useful design vehicles at this stage, although active device drivers and receivers from such designs will not necessarily be optimised for the shorter trace lengths and reduced loads inherent in the SiP translation. Such what -if design activities can form a useful part of collaborative research and development projects as funded by the European Commission and the UK Technology Strategy Board. 6 Establishing and maintaining a living database of SiP design figures-of-merit to guide future SiP design effectiveness and ensure constant design improvements. Suitable figures-of-merit here may include area, headroom and costs reduction compared to the 18333/3/09 12 Copyright EKTN, TWI 2009

pcb implementation (if available), the area fraction of active devices within the module, number of packaging platform substrate routing layers, the integrated passives density level (passives/cm 2 ), active and passive device numbers, wire bond, flip chip and solder joint counts, and the number of stacked die. SiP design figures of merit should be grouped according to generic application area (RF/digital) and the packaging platform employed. 6 SiP Future Trends The future developments in SiP technology will be driven by three principal factors: time-tomarket, functional density and cost-performance. These elements provide the main competitive edge over the alternatives of SoC and conventional pcb implementations for electronics system delivery. The time-to-market metric will be supported by the development of further improved design routes. These design route improvements will be supported by a wider availability and adoption of packaging platform and IPD PDKs to ensure a higher level of right -first-time design. The development and roll-out of laminate and other packaging platform PDKs will be an important part of this process. The chip-package-sip co-design concept will see further growth, driven by the benefits of optimised cost-performance at the SiP level. In many cases the introduction of a new product in a SiP format will then be followed by SoC integration and the addition of greater levels of functionality within a given SiP footprint, the so-called SiP/SoC iteration sequence. The necessary improvements in SiP functional density will be supported by the wider adoption of flip chip technology for chip-to-chip and chip-to-next-level interconnect, by the greater take-up of IPD networks and TSV technologies. The TSV technology will make a significant move from the present research-and-development mode into SiP product applications over the next few years. The need for continuing improvements in the cost-performance metric will see the further enhancement of methods for early design partitioning and a move to larger substrate processing formats for the manufacture of thin-film IPDs and silicon substrates. Further specific areas for future SiP technology development are set out in detail in the 2009 inemi Roadmap (see references). The maximum number of die in SiP module is predicted to increase from today s figure of between six and nine to between eight and 14 by 2014 (depending on application area). The use of TSV structures first appeared on the inemi Roadmap in 2009 with take-up growing from 2 TSV die per module in 2009 to four die per module in 2014. SiP module IO counts are predicted to stay fairly level between now and 2014, with typical IO counts of 200 for RF applications, 800 to 1000 for hand-held and 3000 to 4000 for high-performance products. 18333/3/09 13 Copyright EKTN, TWI 2009

7 Conclusions 1 The available design routes and design tools for SiP have been described. 2 Initial guidance has been provided for UK engineers wishing to embark on SiP design. 3 Future trends in SiP technology and applications have been discussed. 8 References An Integrated Design Flow for RF Module and SiP: Malcolm Edwards, AWR, Proceedings of Design for System-in-Package Seminar, TWI Ltd, Great Abington, 3 June 2008. Arnold R G, Faulkner C C and Pedder D J, 1997: 'Silicon MCM -D Technology for RF Integration, GEC Journal of Technology, Vol. 14, no. 2, pp85-89. Chiu C T, 2008: Challenges in SiP Design: An Overview, ASE, Proceedings of Design for System-in-Package Seminar, TWI Ltd, Great Abington, 3 June 2008. International Electronics Manufacturing Initiative, European Workshop, Packaging Technology Working Group, IMEC, Leuven, June 2008. International Electronics Manufacturing Initiative (inemi), 2009 Roadmap. March 2009. International Technology Roadmap for Semiconductors (ITRS), 2007 Edition. Assembly and Packaging Chapter. Jan Vardaman E, Carpenter K and Matthew L, 2005: System-in-Package - The New Wave in 3D Packaging, TechSearch International, Austin, Texas. System-in-Package (SiP): A Guide for Electronics Design Engineers: Task 2: Reporting - Report No. 1 - SiP Technology - Introduction, Categories and Benefits. TWI Report 18333/1/08, October 2008. System Level Integration in the Package (SiP) - The Next Step in Assembly and Packaging. ITRS White Paper V9.0. System-in-Package (SiP): A Guide for Electronics Design Engineers: Task 2: Reporting - Report no. 2 - SiP Applications. TWI Report 18333/2/09, April 2009. System-in-Package RF Design and Applications: Michael P Gaynor, Artech House 2007. Yannou J-M, 2008: SiP and WLP-CSP Trends - State-of-the-Art and Future Trends, NXP Semiconductors, Electronic Systems Technology Conference 2008, University of Greenwich. 9 Acknowledgements The author of this report would like to acknowledge the most useful discussions held with Malcolm Edwards of AWR, Mike Bradford of Agilent, Charles Blackwood and David Edgar of Ansoft, Keith Felton and Gary Hinde of Cadence, Liam Devlin of Plextek and Brian Morris of Zuken. 18333/3/09 14 Copyright EKTN, TWI 2009