NDSAN N-Channel, Logic Level, PowerTrench MOSFET June NDSAN General Description These N-Channel Logic Level MOSFETs are produced using Fairchild Semiconductor s advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. Features. A, V. R DS(ON) = 6 mω @ V GS = V R DS(ON) = mω @ V GS =. V Ultra-Low gate charge Industry standard outline SOT- surface mount package using proprietary SuperSOT TM - design for superior thermal and electrical capabilities High performance trench technology for extremely low RDS(ON) D D S TM SuperSOT - G G S Absolute Maximum Ratings TA= o C unless otherwise noted Symbol Parameter Ratings Units V DSS Drain-Source Voltage V V GSS Gate-Source Voltage ± V I D Drain Current Continuous (Note a). A Pulsed Power Dissipation for Single Operation (Note a). P D (Note b).6 W T J, T STG Operating and Storage Junction Temperature Range to + C Thermal Characteristics R θja Thermal Resistance, Junction-to-Ambient (Note a) C/W R θjc Thermal Resistance, Junction-to-Case (Note ) 7 Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity A NDSAN 7 8mm units Fairchild Semiconductor Corporation NDSAN Rev E(W)
Electrical Characteristics T A = C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BV DSS Drain Source Breakdown Voltage V GS = V, I D = µa V BVDSS T J Breakdown Voltage Temperature Coefficient I D = µa,referenced to C 6 mv/ C I DSS Zero Gate Voltage Drain Current V DS = V, V GS = V µa V DS = V, V GS = V, T J = C µa I GSS Gate Body Leakage V GS = ± V, V DS = V ± na NDSAN On Characteristics (Note ) V GS(th) Gate Threshold Voltage V DS = V GS, I D = µa.8. V VGS(th) Gate Threshold Voltage I D = µa,referenced to C mv/ C T J Temperature Coefficient R DS(on) Static Drain Source V GS = V, I D =. A 9 6 mω On Resistance V GS =. V, I D =. A V GS = V, I D =. A, T J = C I D(on) On State Drain Current V GS =.V, V DS = V. A g FS Forward Transconductance V DS = V, I D =. A S Dynamic Characteristics C iss Input Capacitance V DS = V, V GS = V, pf C oss Output Capacitance f =. MHz pf C rss Reverse Transfer Capacitance pf R G Gate Resistance V GS = mv, f =. MHz.6 Ω Switching Characteristics (Note ) t d(on) Turn On Delay Time V DD = V, I D = A, 6 ns t r Turn On Rise Time V GS = V, R GEN = 6 Ω 8 6 ns t d(off) Turn Off Delay Time 6 9 ns t f Turn Off Fall Time ns Q g Total Gate Charge V DS = V, I D =. A,..8 nc Q gs Gate Source Charge V GS =. V. nc Q gd Gate Drain Charge. nc Drain Source Diode Characteristics and Maximum Ratings I S Maximum Continuous Drain Source Diode Forward Current. A V SD Drain Source Diode Forward V GS = V, I S =. A (Note ).8. V Voltage t rr Diode Reverse Recovery Time I F =. A, d if/d t = A/µs ns Q rr Diode Reverse Recovery Charge nc Notes:. R θja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θjc is guaranteed by design while R θca is determined by the user's board design. a) C/W when mounted on a. in pad of oz. copper. b) 7 C/W when mounted on a minimum pad. Scale : on letter size paper. Pulse Test: Pulse Width µs, Duty Cycle.% NDSAN Rev E(W)
Typical Characteristics V GS = V.V 6.V.V.V.. V DS, DRAIN TO SOURCE VOLTAGE (V) R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE.8.6...8.6.. V GS =.V.V.V.V.8 6.V V NDSAN Figure. On-Region Characteristics. Figure. On-Resistance Variation with Drain Current and Gate Voltage. R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE.6...8 I D =.A V GS = V.6 - - 7 T J, JUNCTION TEMPERATURE ( o C) R DS(ON), ON-RESISTANCE (OHM). I D =.7A...7 T A = o C... T A = o C.7 6 7 8 9 V GS, GATE TO SOURCE VOLTAGE (V) Figure. On-Resistance Variation with Temperature. Figure. On-Resistance Variation with Gate-to-Source Voltage. V DS = V T A = o C o C - o C.. V GS, GATE TO SOURCE VOLTAGE (V) I S, REVERSE DRAIN CURRENT (A).... V GS = V T A = o C o C - o C...6.8. V SD, BODY DIODE FORWARD VOLTAGE (V) Figure. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. NDSAN Rev E(W)
Typical Characteristics V GS, GATE-SOURCE VOLTAGE (V) I D =.A V DS = V V 8 V 6... Q g, GATE CHARGE (nc) CAPACITANCE (pf) 8 6 8 6 C ISS C OSS C RSS V DS, DRAIN TO SOURCE VOLTAGE (V) f = MHz V GS = V NDSAN Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.. R DS(ON) LIMIT V GS = V R θja = 7 o C/W T A = o C s DC ms ms ms.. V DS, DRAIN-SOURCE VOLTAGE (V) µs P(pk), PEAK TRANSIENT POWER (W).. t, TIME (sec) R θja = 7 C/W T A = C Figure 9. Maximum Safe Operating Area. Figure. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE.. D =........... t, TIME (sec) P(pk) R θja (t) = r(t) * R θja R θja = 7 o C/W t t T J - T A = P * R θja (t) Duty Cycle, D = t / t Figure. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note b. Transient thermal response will change depending on the circuit board design. NDSAN Rev E(W)
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