State-of-the-Art Flash Memory Technology, Looking into the Future April 16 th, 2012 大 島 成 夫 (Jeff Ohshima) Technology Executive Memory Design and Application Engineering Semiconductor and Storage Products Company Toshiba Corporation
Reorganization as of July. 1 st, 2011 Semiconductor and Storage Products Company Total Storage Solution by Toshiba SSD Flash Trad-Enterprise Near-line Mobile Industrial CE Client Enterprise
2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 Capacity [EB] 35000 30000 Storage Market Forecast The storage market continues to grow. Storage capacity will never catch up with the speed of the information explosion. Info-plosion Amount of information produced by human activities 35ZB 25000 20000 15000 10000 5000 0 1800EB 800EB This Gap contain 1. Unused Stream Data 2. Transfer Info. Data 3. Temporary Data Opt. Flash Contribution of Flash Memory 1% 2.5% 5% 出 展 :TSR 社 () 日 本 記 憶 メディア 工 業 会 (CD/DVD/BD) ベースにTSB 試 算 情 報 生 成 量 / 利 用 可 能 ストレージ(IDC 白 書 ) XX
Current System Global Server Side Changes in Data Storage in Cloud Computing Era DRAM Cloud Computing Network system Global Server Side SSD DRAM SSD Replace SaaS Grid Computing ASP Cloud Computing Utility Computing Ubiquitous Computing On Demand Computing Car Mobile Phone PC DSC Car Smart Phone PC SSD Smart TV Tablet DSC Tape Client Application SSD Client Application
Yokkaichi Factory
Next Gen. 3D Memory Technology
The Narrowing Road Map to the Future Costly Mountains 2 0
Memory Road Map for Emerging Memory 09 年 10 年 11 年 12 年 13 年 14 年 15 年 ~ 32n Post 24n 19n Extension of FG BiCS Cross Point 3D Post-post Many Candidates NEMS Memory Molecular Memory Organic Memory Race Track Working Memory MRAM
What is BiCS technology? A break-through concept for 3D memory Row Decoder Cell Array Stack Plate electrode Pillar electrode Punch Plug New 3D stacked memory High cost effectiveness Memory cell
BiCS Flash Memory BiCS technology applied to flash Upper SG Control Gate (WL) Lower SG (GSL) Vertical poly-si TFT for cell/select gate Charge trap memory with cylinder shape ONO Shared control gate Source Line (CSL) Bit Line Channel Poly Si Tunnel Ox Charge SiN Block Ox Control Gate String Bit Line Upper Select Gate Control Gate Lower Select Gate Source Line
P-BiCS Flash N+ Diffusion Bit Line Source Line Select Gate No Diffusion between gates Non-doped poly-si Channel Control Gates Back Gate P-BiCS has U shaped string with back gate to reduce parasitic resistance of bottom portion. There is no diffusion between CGs. Select gate has asymmetric source and drain structure to reduce off current.
Non-Volatile Random Access memory (Work memory) Introduction of STT-MRAM
STT-MRAM; Work Memory + Code Storage Capacity (bits) 100G Data Storage 10G Working Memory BiCS/ReRAM FG- 1G 100M DRAM Scaling PCM NOR Code Storage Target Area of FG-/ Post- 10M SRAM MRAM Target Area of High-density MRAM 1M 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 1E-2 Write/Program Cycle Time (s) MRAM > PCM Program time P/E Endurance
STT-MRAM Target Field etc Server PC DVC DRAM based Applications Handset DSC Tablet
Why STT-MRAM? DRAM Scaling Down continously?? Difficulty?? At DRAM Cell Capacitor beyond 20nm More Refresh More Power More Refresh Poor Performance STT-MRAM could cover beyond 20nm working RAM field.
What is STT-MRAM? STT (Spin-Transfer Torque) MRAM Non-volatile & Resistive Cell - Electron spin to store data - Magnetic storage elements (MTJ: Magnetic Tunnel Junction) State 0 (Low Resistance) State 1 (High Resistance) Ferromagnetic Reference Layer Tunnel Barrier Ferromagnetic Storage Layer Parallel Spin State Anti-Parallel Spin State
FG Summary Continuous scaling is on going for 2X/1Xnm FG- and as far as possible Post BiCS and ReRAM are most promising candidate. And now test chip learning is on going STT-MRAM Spin Transfer Torque MRAM is the promising memory, Non-volatile, high speed random access, unlimited cycling
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