INTEGRATED CIRCUITS. For a complete data sheet, please also download:

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1 INTEGRTED CIRCUITS DT SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS ogic Package Outlines 74C/CT181 Supersedes data of September 1993 File under Integrated Circuits, IC Jun 10

2 74C/CT181 FETURES Full carry look-ahead for high-speed arithmetic operation on long words Provides 16 arithmetic operations: add, subtract, compare, double, plus 12 others Provides all 16 logic operations of two variables: EXCUSIVE-OR, compare, ND, NND, NOR, OR plus 10 other logic operations Output capability: I CC category: MSI GENER DESCRIPTION standard, =B open drain The 74C/CT181 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7. The 74C/CT181 are 4-bit high-speed parallel rithmetic ogic Units (U). Controlled by the four function select inputs (S 0 to S 3 ) and the mode control input (M), they can perform all the 16 possible logic operations or 16 erent arithmetic operations on active IG or active OW operands (see function table). When the mode control input (M) is IG, all internal carries are inhibited and the device3 performs logic operations on the individual bits as listed. When M is OW, the carries are enabled and the 181 performs arithmetic operations on the two 4-bit words. The 181 incorporates full internal carry look-ahead and provides for either ripple carry between devices using the C n+4 output, or for carry look-ahead between packages using the carry (P) and carry generate (G) signals. P and G are not affected by carry in. When speed requirements are not stringent, it can be used in a simple ripple carry mode by connecting the carry output (C n+4 ) signal to the carry input (C n ) of the next unit. For high-speed operation the device is used in conjunction with the 182 carry look-ahead circuit. One carry look-ahead package is required for each group of four 181 devices. Carry look-ahead can be provided at various levels and offers high-speed capability over extremely long word lengths. The comparator output (=B) of the device goes IG when all four function outputs (F 0 to F 3 ) are IG and can be used to indicate logic equivalence over 4 bits when the unit is in the subtract mode. =B is an open collector output and can be wired-nd with other =B outputs to give a comparison for more than 4 bits. The open drain output =B should be used with an external pull-up resistor in order to establish a logic IG level. The =B signal can also be used with the C n+4 signal to indicate > B and < B. The function table lists the arithmetic operations that are performed without a carry in. n incoming carry adds a one to each operation. Thus, select code generates minus B minus 1 (2s complement notation) without a carry in and generates minus B when a carry is applied. Because subtraction is actually performed by complementary addition (1s complement), a carry out means borrow; thus, a carry is generated when there is no under-flow and no carry is generated when there is underflow. s indicated, the 181 can be used with either active OW inputs producing active OW outputs or with active IG inputs producing active IG outputs. For either case the table lists the operations that are performed to the operands. ORDERING INFORMTION TYPE NUMBER 74C181N3; 74CT181N3 74C181N; 74CT181N 74C181D; 74CT181D PCKGE NME DESCRIPTION VERSION DIP24 plastic dual in-line package; 24 leads (300 mil) SOT222-1 DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1 SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT Jun 10 2

3 74C/CT181 QUICK REFERENCE DT GND = 0 V; T amb =25 C; t r =t f =6ns SYMBO PRMETER CONDITIONS C TYPIC CT t P / t P C = 15 pf; V CC =5V n or B n to =B ns C n to C n ns C I input capacitance pf C PD power dissipation capacitance per package notes 1 and pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i + (C V 2 CC f o ) where: f i = input frequency in Mz f o = output frequency in Mz (C V 2 CC f o ) = of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For C the condition is V I = GND to V CC For CT the condition is V I = GND to V CC 1.5 V B Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol Jun 10 3

4 74C/CT181 PIN DESCRIPTION PIN NO. SYMBO NME ND FUNCTION 1, 22, 20, 18 B 0 to B 3 operand inputs (active OW) 2, 23, 21, 19 0 to 3 operand inputs (active OW) 6, 5, 4, 3 S 0 to S 3 select inputs 7 C n carry input 8 M mode control input 9, 10, 11, 13 F 0 to F 3 function outputs (active OW) 12 GND ground (0 V) 14 =B comparator output 15 P carry propagate output (active OW) 16 C n+4 carry output 17 G carry generate output (active OW) 24 V CC positive supply voltage ok, halfpage 2 0 F F F F B 0 C n+4 B 1 =B B 2 G B 3 P 15 7 C n 6 S 0 5 S 1 4 S 2 3 S 3 8 M MBK219 Fig.4 Functional diagram. Fig.5 ctive IG operands - active OW operands Jun 10 4

5 74C/CT181 FUNCTION TBES MODE SEECT INPUTS S 3 S 2 S 1 S 0 OGIC (M=) Notes to the function tables 1. Each bit is shifted to the next more significant position. 2. rithmetic operations expressed in 2s complement notation. = IG voltage level = OW voltage level CTIVE IG INPUTS ND OUTPUTS + B B logical 0 B B B B +B B B B logical 1 +B +B RITMETIC (2) (M=; C n =) +B +B minus 1 plus B ( + B) plus B minus B minus 1 B minus 1 plus B plus B ( + B) plus B B minus 1 plus (1) ( + B) plus ( + B) plus minus 1 MODE SEECT INPUTS S 3 S 2 S 1 S 0 OGIC (M=) Notes to the function tables 1. Each bit is shifted to the next more significant position. 2. rithmetic operations expressed in 2s complement notation. = IG voltage level = OW voltage level CTIVE OW INPUTS ND OUTPUTS B +B logical 1 + B B B +B B B B + B logical 0 B B RITMETIC (2) (M=; C n =) minus 1 B minus 1 B minus 1 minus 1 plus ( + B) B plus ( + B) minus B minus 1 +B plus ( + B) plus B B plus ( + B) +B plus (1) B plus B plus 1998 Jun 10 5

6 74C/CT181 Fig.6 ogic diagram Jun 10 6

7 74C/CT181 Table 1 SUM MODE TEST Function inputs S 0 =S 3 = V, M = S 1 =S 2 =0V PRMETER INPUT UNDER TEST OTER INPUT, SME BIT OTER DT INPUTS OUTPUT UNDER pply V pply GND pply V pply GND TEST t P / t P i B i none remaining and B C n F i t P / t P B i i none remaining and B C n F i t P / t P i B i none none remaining and B, C n P t P / t P B i i none none remaining and B, C n P t P / t P i none B i remaining B remaining, C n G t P / t P B i none i remaining B remaining, C n G t P / t P i none B i remaining B remaining, C n C n+4 t P / t P B i none i remaining B remaining, C n C n+4 t P / t P C n none none all all B any F or C n+4 Table 2 DIFFERENTI MODE TEST Function inputs S 1 =S 2 = V, M = S 0 =S 3 =0V PRMETER INPUT UNDER TEST OTER INPUT, SME BIT OTER DT INPUTS OUTPUT UNDER pply V pply GND pply V pply GND TEST t P / t P i none B i remaining remaining B, C n F i t P / t P B i i none remaining remaining B, C n F i t P / t P i none B i none remaining and B, C n P t P / t P B i i none none remaining and B, C n P t P / t P i B i none none remaining and B, C n G t P / t P B i none i none remaining and B, C n G t PZ / t PZ i none B i remaining remaining B, C n =B t PZ / t PZ B i i none remaining remaining B, C n =B t P / t P i B i none none remaining and B, C n C n+4 t P / t P B i none i none remaining and B, C n C n+4 t P / t P C n none none all and B none any F or C n+4 Table 3 OGIC MODE TEST Function inputs M = S 1 =S 2 = V, S 0 =S 3 =0V PRMETER INPUT UNDER TEST OTER INPUT, SME BIT OTER DT INPUTS OUTPUT UNDER pply V pply GND pply V pply GND TEST t P / t P i B i none none remaining and B, C n F i t P / t P B i i none none remaining and B, C n F i 1998 Jun 10 7

8 74C/CT181 RTINGS (for =B output only) imiting values in accordance with the bsolute Maximum System (IEC 134) Voltage are referenced to GND (ground = 0 V) SYMBO PRMETER MIN. MX. CONDITIONS V O DC output voltage V I OK DC output diode current 20 m for V O < 0.5 V I O DC output source or sink current 25 m for 0.5 V < V O DC CRCTERISTICS FOR 74C For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI Voltages are referenced to GND (ground = 0 V) T amb ( C) TEST CONDITIONS SYMBO PRMETER 74C to to +125 min. typ. max. min. max. min. max. V CC (V) V I OTER I OZ IG level output leakage current µ 2.0 to V I note 1 V O =0or6V Note to the DC characteristics 1. The maximum operating output voltage (V O(max) ) is V Jun 10 8

9 74C/CT181 C CRCTERISTICS FOR 74C GND = 0 V; t r =t f = 6 ns; C = 50 pf SYMBO t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P PRMETER 55 C n to C n C n to F n n to G B n to G n to G B n to G n to P B n to P n to P B n to P T amb ( C) 74C to to +125 min. typ. max. min. max. min. max i to F i B i to F i i to F i B i to F i Jun V CC (V) TEST CONDITIONS MODE OTER M=0V; Fig.9; Tables 1 and 2 M=0V; Fig.9; Tables 1 and 2 M=S 1=S 2 =0V; S 0 =S 3 = V; M=S 1 =S 2 =0V; S 0 =S 3 = V; S 1 =S 2 = V; S 1 =S 2 = V; M=S 1 =S 2 =0V; S 0 =S 3 = V; M=S 1 =S 2 =0V; S 0 =S 3 = V; S 1 =S 2 = V; S 1 =S 2 = V; M=S 1 =S 2 =0V; S 0 =S 3 = V; M=S 1 =S 2 =0V; S 0 =S 3 = V; S 1 =S 2 = V; S 1 =S 2 = V;

10 74C/CT181 SYMBO t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t PZ / t PZ t PZ / t PZ t P / t P t P / t P t P / t P t P / t P t T / t T PRMETER 74 i to F i B i to F i n to C n B n to C n n to C n B n to C n n to =B B n to =B n to F n B n to F n n to F n B n to F n output transition time Note to the C characteristics 1. For the open drain output (=B) only t T is valid. T amb ( C) 74C to to +125 min. typ. max. min. max. min. max V CC (V) TEST CONDITIONS MODE logic logic OTER M = V; Fig.8; Table 3 M = V; Fig.8; Table 3 M=S 1 =S 2 =0V; S 0 =S 3 = V; Fig.8; Table 1 M=S 1 =S 2 =0V; S 0 =S 3 = V; Fig.8; Table 1 S 1 =S 2 = V; Fig.10; Table 2 S 1 =S 2 = V; Fig.10; Table 2 S 1 =S 2 = V; Fig.11; Table 2 S 1 =S 2 = V; Fig.11; Table 2 M=S 1 =S 2 =0V; S 0 =S 3 = V; M=S 1 =S 2 =0V; S 0 =S 3 = V; S 1 =S 2 = V; S 1 =S 2 = V; note ; Figs 7 and Jun 10 10

11 74C/CT181 DC CRCTERISTICS FOR 74CT For the DC characteristics see 74C/CT/CU/CMOS ogic Family Specifications. Output capability: standard I CC category: MSI Voltages are referenced to GND (ground = 0 V) SYMBO I OZ PRMETER IG level output leakage current T amb ( C) 74CT to to +125 min. typ. max. min. max. min. max. V CC (V) µ 2.0 to TEST CONDITIONS V I OTER V I note 1 V O = 0 or 6 V Note to the DC characteristics 1. The maximum operating output voltage (V O(max) ) is V. Note to CT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT OD COEFFICIENT C n, M 0.50 n, B n 0.75 S n Jun 10 11

12 74C/CT181 C CRCTERISTICS FOR 74CT GND = 0 V; t r =t f = 6 ns; C = 50 pf T amb ( C) TEST CONDITIONS SYMBO PRMETER 74CT to to +125 min. typ. max. min. max. min. max. V CC (V) MODE OTER t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P C n to C n+4 C n to F n n to G B n to G n to G B n to G n to P B n to P n to P B n to P i to F i B i to F i ns ns M=0V; Fig.9; Tables 1 and 2 M=0V; Fig.9; Tables 1 and ns M = S 1 =S 2 =0V; S 0 =S 3 = V; ns M = S 1 =S 2 =0V; S 0 =S 3 = V; ns M = S 0 =S 3 =0V; S 1 =S 2 = V; ns M = S 0 =S 3 =0V; S 1 =S 2 = V; ns M = S 1 =S 2 =0V; S 0 =S 3 = V; ns M = S 1 =S 2 =0V; S 0 =S 3 = V; ns M = S 0 =S 3 =0V; S 1 =S 2 = V; ns M = S 0 =S 3 =0V; S 1 =S 2 = V; ns M = S 1 =S 2 =0V; S 0 =S 3 = V; ns M = S 1 =S 2 =0V; S 0 =S 3 = V; 1998 Jun 10 12

13 74C/CT181 T amb ( C) TEST CONDITIONS SYMBO PRMETER 74CT to to +125 min. typ. max. min. max. min. max. V CC (V) MODE OTER t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t P / t P t PZ / t PZ t PZ / t PZ t P / t P t P / t P i to F i B i to F i i to F i B i to F i n to C n+4 B n to C n+4 n to C n+4 B n to C n+4 n to =B B n to =B n to F n B n to F n ns M = S 0 =S 3 =0V; S 1 =S 2 = V; ns M = S 0 =S 3 =0V; S 1 =S 2 = V; ns logic M = V; Fig.8; Table ns logic M = V; Fig.8; Table ns M = S 1 =S 2 =0V; S 0 =S 3 = V; Fig.8; Table ns M = S 1 =S 2 =0V; S 0 =S 3 = V; Fig.8; Table ns M = S 0 =S 3 =0V; S 1 =S 2 = V; Fig.10; Table ns M = S 0 =S 3 =0V; S 1 =S 2 = V; Fig.10; Table ns M = S 0 =S 3 =0V; S 1 =S 2 = V; Fig.11; Table ns M = S 0 =S 3 =0V; S 1 =S 2 = V; Fig.11; Table ns M = S 1 =S 2 =0V; S 0 =S 3 = V; ns M = S 1 =S 2 =0V; S 0 =S 3 = V; 1998 Jun 10 13

14 74C/CT181 T amb ( C) TEST CONDITIONS SYMBO PRMETER 74CT to to +125 min. typ. max. min. max. min. max. V CC (V) MODE OTER t P / t P t P / t P t T / t T n to F n n to F n output transition time ns M = S 0 =S 3 =0V; S 1 =S 2 = V; ns M = S 0 =S 3 =0V; S 1 =S 2 = V; ns Figs 7 and 11; note 1 Note to the C characteristics 1. For the open drain output (=B) only t T is valid Jun 10 14

15 74C/CT181 C WVEFORMS Fig.7 Propagation s for carry input to carry output, carry input to function outputs, operands to carry generate operands, outputs and output transition lines. Fig.8 Propagation s for operands to carry generate, propagate outputs and function outputs. Fig.9 Propagation s for operands to carry output and function outputs. Fig.10 Propagation s for operands to carry output. Note to C waveforms (1) C: V M = 50%; V I = GND to V CC. CT: V M = 1.3 V; V I = GND to 3 V. PPICTION INFORMTION Fig.11 Waveforms showing the input ( i, B j ) to output (=B) s and output transition time of the open drain output (=B). and B inputs and F outputs of 181 are not shown Fig.12 pplication example showing 16-bit U ripple-carry configuration Jun 10 15

16 74C/CT181 PCKGE OUTINES DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1 seating plane D 2 M E 1 Z e b 1 w M c (e ) 1 24 b 13 M pin 1 index E mm scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 M E M w (1) Z max Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. OUTINE VERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT222-1 MS-001F Jun 10 16

17 74C/CT181 DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1 seating plane D 2 M E 1 Z 24 e b b 1 13 w M c (e ) 1 M pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 M E M w Z (1) max Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTINE VERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT G02 MO-015D Jun 10 17

18 74C/CT181 SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E X c y E v M Z Q 2 1 ( ) 3 pin 1 index p θ 1 e b p 12 w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) mm inches max b p c D (1) E (1) e (1) E p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included θ o 8 o OUTINE VERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT E05 MS-013D Jun 10 18

19 74C/CT181 SODERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. owever, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. more in-depth account of soldering ICs can be found in our Data andbook IC26; Integrated Circuit Packages (order code ). DIP SODERING BY DIPPING OR BY WVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T stg max ). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPIRING SODERED JOINTS pply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFOW SODERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WVE SODERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow. The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPIRING SODERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C Jun 10 19

20 74C/CT181 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. imiting values imiting values given are in accordance with the bsolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. pplication information Where application information is given, it is advisory and does not form part of the specification. IFE SUPPORT PPICTIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale Jun 10 20