PROGRAMOWANIE STRUKTUR CYFROWYCH
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1 PROGRAMOWANIE STRUKTUR CYFROWYCH FPGA r inż. Igncy Pryk, UJK Kielce Mteriły źrółowe:. Slies to ccompny the textbook Digitl Design, First Eition, by Frnk Vhi, John Wiley n Sons Publishers, 7, Slies to compny the textbook Embee Systems: A Contemporry Design Tool, by Jmes K.Peckol, John Wiley n Sons Publishers, 8. Copyright 7 Frnk Vhi Instructors of courses requiring Vhi's Digitl Design textbook (publishe by John Wiley n Sons) hve permission to moify n use these slies for customry course-relte ctivities, subject to keeping this copyright notice in plce n unmoifie. These slies my be poste s unnimte pf versions on publicly-ccessible course websites.. PowerPoint source (or pf Digitl Design with nimtions) my not be poste to publicly-ccessible websites, but my be poste for stuents on internl protecte sites or istribute irectly to stuents by other electronic mens. Copyright 6 /6 Instructors my mke printouts of the slies vilble to stuents for resonble photocopying chrge, without incurring roylties. Any other use requires explicit permission. Instructors Frnk Vhi my obtin PowerPoint source or obtin specil use permissions from Wiley see for informtion. Embee Systems, 8, Jmes K. Peckol
2 7. Progrmmble IC Technology FPGA Mnufcture IC technologies require weeks to months to fbricte An hve lrge (hunre thousn to million ollr) initil costs Progrmmble ICs re pre-mnufcture Cn implement circuit toy Just ownlo bits into evice Slower/bigger/more-power thn mnufcture ICs But get it toy, n no fbriction costs Populr progrmmble IC FPGA "Fiel-progrmmble gte rry" Develope lte 98s Though no "gte rry" insie Nme when gte rrys were very populr in the 98s Progrmmble in secons Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol /6
3 FPGA Internls: Lookup Tbles (LUTs) Bsic ie: Memory cn implement combintionl logic e.g., -ress memory cn implement -input logic -bit wie memory function; -bits wie functions Such memory in FPGA known s Lookup Tble (LUT) F = x'y' + xy x y F x y 4x Mem. r x= D y= 4x Mem. r D (b) (c) Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol x 4x Mem. y F G x y r D D F= F () F = x'y' + xy G = xy' () F G (e) /6
4 FPGA Internls: Lookup Tbles (LUTs) Exmple: Set-belt wrning light (gin) k BeltWrn p w s () k p s (c) 8x Mem IC (b) k p s w Progrmming (secons) Fb - months D w Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol 4/6
5 FPGA Internls: Lookup Tbles (LUTs) Lookup tbles become inefficient for more inputs inputs only 8 wors 8 inputs 56 wors; 6 inputs 65,56 wors! FPGAs thus hve numerous smll (, 4, 5, or even 6-input) LUTs If circuit hs more inputs, must prtition circuit mong LUTs Exmple: Extene set-belt wrning light system: Sub-circuits hve only -inputs ech k BeltWrn p k w p s s t t 5-input circuit, but input LUTs vilble Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol x x+ inputs t+ output w=x+t+ (b) w k p s inputs output x=kps' () kps' BeltWrn 8x Mem x D D t Prtition circuit into -input sub-circuits 8x Mem (c) w Mp to -input LUTs5/6
6 FPGA Internls: Lookup Tbles (LUTs) Prtitioning mong smller LUTs is more size efficient Exmple: 9-input circuit b c e f g h i F () Originl 9-input circuit Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol b c e f g h i 5xMem. x x x F 8xMem. x (b) Prtitione mong x LUTs (c) Requires only 4 -input LUTs (8x memories) much smller thn 9-input LUT (5x memory) 6/6
7 FPGA Internls: Lookup Tbles (LUTs) LUT typiclly hs (or more) outputs, not just one Exmple: Prtitioning circuit mong -input -output lookup tbles b c 8x Mem. F e b c () t b c F e Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol D D D D t (b) (Note: ecompose one 4input AND input two smller ANDs to enble prtitioning into -input sub-circuits) 8x Mem. e F (c) First column unuse; secon column implements AND Secon column unuse; first column implements AND/OR sub-circuit 7/6
8 FPGA Internls: Lookup Tbles (LUTs) out put s Exmple: Mpping x4 ecoer to -input -output LUTs inp u ts, ircu it h s i i Su in b-c p u ir ts, cui th ou s tp ut s Sub -c () Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol i i 8x Mem x Mem D D D D (b) 8/6
9 FPGA Internls: Switch Mtrices Previous slies h hrwire connections between LUTs Inste, wnt to progrm the connections too Use switch mtrices (lso known s progrmmble interconnect) Simple mux-bse version ech output cn be set to ny of the four inputs just by progrmming its -bit configurtion memory Switch mtrix -bit memory FPGA (prtil) P P P P 8x Mem D D 8x Mem o o m m m m Switch mtrix Embee Systems, 8, Jmes K. Peckol P7 -bit memory D D s s i o i 4x i mux i P8 P9 P4 P5 Digitl Design Copyright 6 Frnk Vhi P6 s s i o i 4x i mux i m m m m () (b) 9/6
10 FPGA Internls: Switch Mtrices Mpping x4 ecoer onto n FPGA with switch mtrix i i 8x Mem. 8x Mem D D o m o m m m Switch mtrix s s i o i 4x i mux i m m m m D D s s i o i 4x i mux i i i (b) () Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol /6 These bits estblish the esire connections Switch mtrix FPGA (prtil)
11 FPGA Internls: Switch Mtrices Mpping the extene setbelt wrning light onto n FPGA with switch mtrix k p s D D x o m o m m m Switch mtrix w s s i o i 4x i mux i m m m m D D s s i o i 4x i mux i () Embee Systems, 8, Jmes K. Peckol t Digitl Design Copyright 6 Frnk Vhi t Switch mtrix FPGA (prtil) 8x Mem x s Recll erlier exmple (let's ignore input for simplicity) 8x Mem BeltWrn k p (b) /6 w
12 FPGA Internls: Configurble Logic Blocks (s) LUTs cn only implement combintionl logic Nee flip-flops to implement sequentil logic A flip-flop to ech LUT output Configurble Logic Block () LUT + flip-flops Cn progrm outputs to come from flip-flops or from LUTs irectly Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol FPGA P P P P output flip-flop -bit output configurtion memory 8x Mem. 8x Mem D x D o m o m m m Switch mtrix D x x D x P6 P7 P8 P9 P4 P5 /6
13 FPGA Internls: Sequentil Circuit Exmple using s b c FPGA w x y b z () Left lookup tble D b w=' x=b' below unuse (b) Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol 8x Mem. 8x Mem D D D x o m o m m m Switch mtrix D x x D x z y x w c (c) /6
14 FPGA Internls: Overll Architecture Consists of hunres or thousns of s n switch mtrices (SMs) rrnge in regulr pttern on chip Connections for just one shown, but ll s re obviously connecte to chnnels Represents chnnel with tens of wires SM SM SM Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol SM 4/6
15 FPGA Internls: Progrmming n FPGA FPGA All configurtion memory bits re connecte s one big shift register Pin Pclk b () Known s scn chin Shift in "bit file" of esire circuit (b) Pin Pclk Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol 8x Mem D D x x 8x Mem o m o m m m Switch mtrix D D x x z y x w c Conceptul view of configurtion bit scn chin is tht of 4-bit shift register (c) Bit file contents for esire circuit: This isn't wrong. Although the bits pper s "" bove, note tht the scn chin psses through those bits from right to left so "" is correct here. 5/6
16 Procesor i pmięć wbuowne w FPGA W strukturze FPGA możn skonfigurowć Procesor np. open source PicoBlze (Verilog, VHDL) Pmięć progrmu (ROM) Pmięć nych Interfejsy Ukły we/wy Jenostki obliczeniowe Inne potrzebne mouły Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol 6/6
17 up bse system Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol 7/6
18 uc bse system Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol 8/6
19 Xilinx FPGA n płycie Nexys Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol 9/6
20 Xilinx FPGA n płycie Nexys Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol /6
21 Xilinx FPGA n płycie Nexys Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol /6
22 Xilinx FPGA n płycie Nexys Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol /6
23 Xilinx FPGA n płycie Nexys Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol /6
24 Xilinx FPGA n płycie Nexys Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol 4/6
25 Xilinx FPGA n płycie Nexys Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol 5/6
26 Xilinx FPGA n płycie Nexys Digitl Design Copyright 6 Frnk Vhi Embee Systems, 8, Jmes K. Peckol 6/6
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