Digital Design. Chapter 7: Physical Implementation
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1 Digitl Deign Chter : Phyicl Imlementtion Slide to ccomny the textoo Digitl Deign, ith RTL Deign, VHDL, nd Verilog, nd Edition, y Frn Vhid, John Wiley nd Son Puliher,. htt://.ddvhid.com Coyright Frn Vhid Intructor of coure requiring Vhid' Digitl Deign textoo (ulihed y John Wiley nd Son) hve ermiion to modify nd ue thee lide for cutomry coure-relted ctivitie, uject to eeing thi coyright notice in lce nd unmodified. Thee lide my e oted unnimted df verion on ulicly-cceile coure eite.. PoerPoint ource (or df ith nimtion) Digitl my Deign not e oted e to ulicly-cceile eite, ut my e oted for tudent on internl rotected ite or ditriuted directly to tudent y other electronic men. Intructor my Coyright me rintout of the lide ville to tudent for reonle hotocoying chrge, ithout incurring royltie. Any other ue require exlicit ermiion. Intructor my otin PoerPoint Frn Vhid ource or otin ecil ue ermiion from Wiley ee htt://.ddvhid.com for informtion.
2 Introduction. A digitl circuit deign i jut n ide, erh drn out Need to imlement the circuit on hyicl device Ho do e get from deign to IC (integrted circuit, chi)? Belt Wrn. IC () Digitl circuit deign () Phyicl imlementtion on n IC Digitl Deign e Coyright Frn Vhid Note: Slide ith nimtion re denoted ith mll red "" ner the nimted item
3 IC Tye, Deign Flo Mny IC tye Some ft ut exenive Other cheer ut loer Tye lo differ in deign flo Some long time Other offthe-helf No dicu oulr tye FPGA (c) ASIC Cutom IC () BeltWrn () FPGA comny Digitl Deign e Coyright Frn Vhid
4 Mnufctured IC Technologie. Deigner cn mnufcture ne IC Month of time, million of dollr () Full-cutom IC Convert deign to lyout: Decrie loction/ize of every trnitor on IC Tyiclly creted y CAD tool Send to friction lnt (f) to convert lyout to ctul IC Photogrhic, ler, chemicl equiment Hrd! F etu cot ("non-recurring engineering", or NRE) high million of dollr Long f time (month) Error rone (everl "rein") Uncommon Only ecil IC tht demnd the very et erformnce or the very mllet ize/oer () (d) BeltWrn (month) () (c) Digitl Deign e Coyright Frn Vhid
5 Mnufctured IC Technologie Stndrd Cell ASIC () Semicutom IC (ASIC) "Aliction-ecific" IC () Stndrd cell ASIC Pre-lyed-out tndrd-ized "cell" exit in lirry Deigner intntite cell into redefined ro, nd connect V. full cutom Con: Bigger/loer circuit Pro: Eier/fter to deign/mnufcture () BeltWrn Cell lirry cell ro () cell ro cell ro (d) (c) ( month: cell nd iring) Digitl Deign e Coyright Frn Vhid
6 Mnufctured IC Technologie Stndrd Cell ASIC Exmle: Ming hlf-dder to tndrd cell ASIC co = = ' + ' Cell lirry ' cell ro co ' cell ro cell ro Digitl Deign e Coyright Frn Vhid
7 Mnufctured IC Technologie Gte Arry ASIC () Gte rry ASIC "Structured" ASIC Arry of gte lredy lyed out on chi Jut need to ire them together V. tndrd cell ASIC Con: Even igger/loer circuit Pro: Even eier/fter to deign/mnufcture () (d) BeltWrn () (c) Very oulr (ee: jut iring) Digitl Deign e Coyright Frn Vhid
8 Mnufctured IC Technologie Gte Arry ASIC Exmle: Ming hlf-dder to gte rry ASIC Hlf-dder eqution: = ' + ' co = ' ' co Gte rry Digitl Deign e Coyright Frn Vhid 8
9 Imlementing Circuit Uing NAND Gte Only Recll NAND/NOR more efficient thn AND/OR Gte rry my hve NAND only Std cell more efficient uing NAND NAND i univerl gte Any circuit cn e med to NAND only Ech of AND, OR, nd NOT cn e converted to equivlent circuit of NAND Convert AND/OR/NOT circuit to NAND-only circuit uing ming rule After converting, remove doule inverion x F=x' Inut x F= x Outut F ()' F=x' F= Doule inverion F=+ F=('')'=''+''=+ Digitl Deign e Coyright Frn Vhid 9
10 Imlementing Circuit Uing NAND Gte Only Exmle: Hlf-dder x F=x' x F=x' F= ()' F= F=+ F=('')'=''+''=+ Rule doule inverion () Digitl Deign e Coyright Frn Vhid () doule inverion (c)
11 Imlementing Circuit Uing NAND Gte Only Shortcut hen converting y hnd Ue inverion ule rther thn dring inverter -inut NAND Then remove doule inverion efore doule inverion doule inverion () () (c) doule inverion (delete) Digitl Deign e Coyright Frn Vhid doule inverion (delete)
12 Imlementing Circuit Uing NOR Gte Only NOR gte i lo univerl Converting AND/OR/NOT to NOR done uing imilr rule ' ' + + Digitl Deign e Coyright Frn Vhid
13 Imlementing Circuit Uing NOR Gte Only Exmle: Hlf dder doule inverion () doule inverion () (c) Digitl Deign e Coyright Frn Vhid
14 Imlementing Circuit Uing NOR Gte Only Exmle: Set elt rning light on NOR-ed gte rry Note: if uing -inut NOR gte, firt convert AND/OR gte to -inut + () () (c) (d) Digitl Deign e Coyright Frn Vhid
15 Off-the-Shelf Progrmmle IC Tye FPGA. Mnufctured IC technologie require month to fricte Alo lrge (million dollr) NRE cot Progrmmle IC re re-mnufctured Uer jut donlod it into device, in jut econd Sloer/igger/more-oer thn mnufctured IC But get it tody, nd no NRE cot Poulr rogrmmle IC FPGA "Field-rogrmmle gte rry" Develoed lte 98 Though no "gte rry" inide Nmed hen gte rry ere oulr in 98 Progrmmle in the "field" (e.g, your l) rther thn requiring f Digitl Deign e Coyright Frn Vhid
16 FPGA Internl: Loou Tle (LUT) Bic ide: Memory cn imlement comintionl logic Ex: -ddre memory cn imlement -inut logic -it ide memory function; -it ide function Such memory in FPGA non loou tle (LUT) F = x'y' + xy x y () F x y x Mem. rd D () F x= y= x Mem. + rd D (c) F= F = x'y' + xy G = xy' x y (d) F G x y rd x Mem. D D F (e) G Digitl Deign e Coyright Frn Vhid
17 Ming Comintionl Circuit to LUT Exmle: Set-elt rning light (gin) BeltWrn () + (c) IC 8x Mem. D () Progrmming (econd) F Digitl Deign e Coyright Frn Vhid
18 FPGA More Efficient With Numerou Smll LUTS Loou tle ecome inefficient for more inut inut only 8 ord 8 inut ord inut, ord! FPGA thu hve numerou mll (,,, or even -inut) LUT If circuit h more inut, mut rtition circuit mong LUT Ex: 9-inut circuit more efficient on 8x mem rther thn x c d e f g h i F c d e f g h i x + x x x F x Mem. 8x Mem. () () (c) Originl 9-inut circuit Digitl Deign e Coyright Frn Vhid Prtitioned mong x LUT Require only -inut LUT (8x memorie) much mller thn 9-inut LUT (x memory) 8
19 Circuit Mut e Prtitioned mong Smll LUT Exmle: Extended et-elt rning light ytem (Aume for no e cn crete ny ire to/eteen LUT) t d BeltWrn () -inut circuit, ut - inut LUT ville Su-circuit hve only -inut ech t d inut outut x=' BeltWrn () + Prtition circuit into -inut u-circuit x inut outut =x+t+d ' x+t+d d t 8x Mem. D (c) M to -inut LUT x 8x Mem. D Digitl Deign e Coyright Frn Vhid 9
20 Ming Circuit to x LUT c d e f () Y c d e f () u t Y c + 8xMem. D 8xMem. D 8xMem. D e f d t (c) u Y Divide circuit into -inut u-circuit M ech u-circuit to x LUT (Aume for no tht e cn crete ny ire to/eteen LUT) Digitl Deign e Coyright Frn Vhid
21 Underutilized LUT re Common t () t () x Su-circuit 烰 ь h only inut t 8xMem. D x 8xMem. D (c) Itlic: content don t mtter Digitl Deign e Coyright Frn Vhid
22 Ming to x LUT Exmle: Ming x decoder to -inut -outut LUT Su-circuit h inut, outut i i () Su-circuit h inut, outut d d d d i i 牠 Ն 8x Mem. D D d d () 8x Mem. D D d d Digitl Deign e Coyright Frn Vhid
23 More Ming Iue Gte h more inut thn doe LUT Decomoe gte firt Su-circuit h feer outut thn LUT Jut don't ue outut c d e c d e Digitl Deign e Coyright Frn Vhid () (Note: decomoed one - inut AND inut to mller AND to enle rtitioning into -inut u-circuit) t () F F 㯐 Չ Firt column unued; econd column imlement AND c d e 8x Mem. D D t (c) 8x Mem. D D F Second column unued; firt column imlement AND/OR u-circuit
24 Digitl Deign e Coyright Frn Vhid FPGA Internl: Sitch Mtrice Previou lide hd hrdired connection eteen LUT Inted, nt to rogrm the connection too Ue itch mtrice (lo non rogrmmle interconnect) Simle mux-ed verion ech outut cn e et to ny of the four inut jut y rogrmming it -it configurtion memory P P P P P 8x Mem. D D FPGA Sitch mtrix m o m m o m o () 8x Mem. D D Q Q Sitch mtrix m m m m... -it mem. i i x i mux i i i x i mux i () d -it mem. d o o -it mem. o Lieie for o...
25 Ex: FPGA ith Sitch Mtrix t Ming the extended etelt rning light circuit onto n FPGA ith itch mtrix P P P P P 8x Mem. D D x (') FPGA Sitch mtrix m o m o m m o t 8x Mem. D D Q Q Sitch mtrix m m m m... i i x i mux i i i x i mux i d d o o o Lieie for o... Thee it etlih the deired connection Digitl Deign e Coyright Frn Vhid () ()
26 Configurle Logic Bloc (CLB) Include fliflo to uort equentil circuit Muxe rogrmmed to outut regitered or nonregitered LUT outut CLB outut fli-flo -it CLB outut configurtion memory P P P P P CLB 8xMem. D 㯐 Չ D x x FPGA Sitch mtrix m o m m o m o CLB 8xMem. D D x x Q Q Digitl Deign e Coyright Frn Vhid
27 Sequentil Circuited Med to FPGA CLB 8x Mem. FPGA CLB 8x Mem. c t u P P c P F D t D c v u d D v D d c v d G P P x u v Sitch mtrix m o m o m m o Q F Q G () Digitl Deign e Coyright Frn Vhid
28 FPGA Internl: Overll Architecture Conit of hundred or thound of CLB nd itch mtrice (SM) rrnged in regulr ttern on chi Rereent chnnel ith ten of ire CLB 騐 я CLB CLB Connection for jut one CLB hon, ut ll CLB re oviouly connected to chnnel SM SM CLB CLB CLB SM SM CLB CLB CLB Digitl Deign e Coyright Frn Vhid 8
29 Progrmming n FPGA All configurtion memory it re connected one ig hift regiter Knon cn chin Shift in the "it file" of the deired circuit Pin Pcl P P P P P CLB 8xMem. D D x x FPGA Sitch mtrix m o m m o m o v u d CLB 8xMem. D v D x x Q Q Digitl Deign e Coyright Frn Vhid Bit file content: 9
30 Other Off-the-Shelf IC Tye. Off-the-helf logic (SSI) IC Logic IC h fe gte, connected to IC' in Knon Smll Scle Integrtion (SSI) Poulr logic IC erie: Originlly develoed 9 ᵀԿ Bc then, ech IC cot $ Tody, cot jut ten of cent VCC I I I I I I9 I8 IC I I I I I I I GND Digitl Deign e Coyright Frn Vhid
31 -Serie Logic IC Կ Digitl Deign e Coyright Frn Vhid
32 Uing Logic IC Exmle: Set elt rning light uing off-the-helf IC Otion : Ue one LS8 IC hving -inut AND gte, nd one LS IC hving inverter () Deired circuit I I I I I I9 I8 瀀 LS8 IC (c) Connect IC to crete deired circuit () I I I I I I I n I I I I I I9 I8 n LS IC Digitl Deign e Coyright Frn Vhid () () Decomoe into -inut AND gte (c) I I I I I I I
33 Uing Logic IC Exmle: Set elt rning light uing off-the-helf IC Otion : Ue ingle LS IC hving -inut NOR gte I I I I I I9 I8 () ḰԿ LS IC Digitl Deign e Coyright Frn Vhid () Converting to -inut NOR gte I I I I I I (c) I Connecting the in to crete the deired circuit
34 SPLD Simle Progrmmle Logic Device (SPLD) Develoed 9 (thu, re-dte FPGA) Prefricted IC ith lrge AND- OR tructure Connection cn e "rogrmmed" to crete cutom circuit Progrmmle circuit hon cn imlement ny -inut function of u to term e.g., F = c + 'c' I I I PLD IC O rogrmmle node Digitl Deign e Coyright Frn Vhid
35 Progrmmle Node in n SPLD I I I Fue ed "lon" fue remove connection Memory ed crete connection rogrmmle node Fue ed O () Fue "unlon" fue "lon" fue rogrmmle node PLDIC mem Memory ed mem () Digitl Deign e Coyright Frn Vhid
36 PLD Dring nd PLD Imlementtion Exmle Common y of dring PLD connection: Ue one ire to rereent ll inut of n AND Ue "x" to rereent connection Croing ire re not connected unle "x" i reent Exmle: Set elt rning light uing SPLD BeltWrn I I I ired AND I I' PLD IC ' O PLD IC Digitl Deign e Coyright Frn Vhid To y to generte term
37 PLD Extenion I I I I I I rogrmmle it O O FF x Digitl Deign e Coyright Frn Vhid () PLD IC To-outut PLD O O x FF PLD IC () cl PLD ith rogrmmle regitered outut
38 More on PLD Originlly (9) non Progrmmle Logic Arry PLA Hd rogrmmle AND nd OR rry AMD creted "Progrmmle Arry Logic" "PAL" (trdemr) Only AND rry rogrmmle (fue ed) Lttice Semiconductor Cor. creted "Generic Arry Logic "GAL" (trdemr) Memory ed A IC ccitie increed, comnie ut multile PLD tructure on one chi, 㟠 Կ interconnecting them Becme non Comlex PLD (CPLD), nd older PLD ecme non Simle PLD (SPLD) GENERALLY SPEAKING, difference of SPLD v. CPLD v. FPGA: SPLD: ten to hundred of gte, nd uully non-voltile (ve it ithout oer) CPLD: thound of gte, nd uully non-voltile FPGA: ten of thound of gte nd more, nd uully voltile (ut no reon hy couldn't e non-voltile) Digitl Deign e Coyright Frn Vhid 8
39 FPGA-to-Structured-ASIC FPGA ometime ued ASIC rototye Tyicl flo () Imlement uer circuit on FPGA nd tet () Imlement uer circuit on ASIC (lrge NRE cot) FPGA-to-tructured-ASIC flo () Imlement uer circuit on FPGA nd tet () Imlement FPGA on ASIC ASIC reflect FPGA tructure, NOT the uer' circuit tructure But remove rogrmmility LUT nd itch mtrice re "hrdired" ASIC loer lyer refricted, only to lyer remining Le chnce of rolem (ASIC i imilr to FPGA, feer chnge) Reult in le NRE cot nd le time to mnufcture But loer/igger thn if imlement uer circuit on ASIC directly Digitl Deign e Coyright Frn Vhid 9
40 IC Trdeoff, Trend, nd Comrion. Off-the-helf Mnufctured Eier deign Digitl Deign e Coyright Frn Vhid Quicer vilility Loer NRE cot Fter erformnce Smller ize Loer oer Loer unit cot More ccity Logic IC More otimized FPGA 㠰 Կ SPLD/CPLD Progrmmle Smle vlue Full-cutom Stndrd cell ASIC Gte rry (tructured) ASIC. (month) (M$).. (GHz) (q mm) (W) ($) (B gte)
41 Chooe n IC Tye for Ech Project Project A involve utting the circuit into million moile hone; encrytion eed mut e. GHz, nd ech chi cn e riced u to $. Only IC tye ith t let. GHz eed i tndrd cell ASIC. The $ million in NRE cot cn e mortized over the million chi y dding jut $. to the rice of ech chi, hich hen dded to the $ unit cot reult in rice of $. er chi, much le thn the limit of $. Ue tndrd cell ASIC. Project B involve utting the circuit into, medicl device; encrytion eed mut e MHz, nd ech chi cn e riced u to $. All three IC tye meet eed requirement of MHz. The $ million of NRE for tndrd cell ASIC mortized over, chi ould involve dding $, to the rice of ech chi, hich clerly exceed the limit of $ er chi. Even the $ million of NRE for gte rry ASIC ould require dding $ to the rice of ech chi, hich i till too much. Fortuntely, the FPGA h no NRE cot, nd unit cot of $, hich i le thn the $ limit er chi. Ue FPGA. Project C involve utting the circuit into, utomoile; encrytion eed mut e MHz, nd ech chi cn e riced u to $. All three IC tye meet eed requirement of MHz. Amortizing tndrd cell NRE ould reult in too high chi rice. Amortizing the gte rry ASIC NRE of $ million over, chi ould dd $ er chi, hich hen dded to the $ unit cot ould reult in $ er chi, lightly exceeding the $ er chi limit. Hoever, the unit cot er FPGA chi i $. Thu, none of the three IC tye meet roject C rice er chi requirement, ut the gte rry IC tye come very cloe Ue gte rry. (Chooe from mong tndrd cell ASIC, gte rry ASIC, or FPGA IC tye only, ue metric vlue from reviou lide.) Digitl Deign e Coyright Frn Vhid
42 Key Trend in Imlementtion Technologie Trnitor er IC douling every 8 month for t three decde Knon "Moore' L" Tremendou imliction liction infeile t one time due to outrgeou roceing requirement ecome feile fe yer lter Cn Moore' L continue? Trnitor er IC (million),,, Digitl Deign e Coyright Frn Vhid
43 Technology Comrion Proceor vrietie Cutom roceor Progrmmle roceor PLD FPGA Gte rry Digitl Deign e Coyright Frn Vhid () () More otimized () Eier deign () Stndrd cell IC technologie Full-cutom 㢠 Կ (): Cutom roceor in full-cutom IC Highly otimized (): Cutom roceor in FPGA Prllelized circuit, loer IC technology ut rogrmmle (): Progrmmle roceor in tndrd cell IC Progrm run (motly) equentilly on moderte-coting IC (): Progrmmle roceor in FPGA Not only cn roceor e rogrmmed, ut FPGA cn e rogrmmed to imlement multile roceor/coroceor
44 Chter Summry Mny y to get from deign to hyicl imlementtion Mnufctured IC technologie Full-cutom IC Decide on every trnitor nd ire Semi-cutom IC Trnitor detil re-deigned Gte rry: Jut ire exiting gte Stndrd cell: Plce re-deigned cell nd ire them FPGA Fully rogrmmle Other technologie Logic IC, PLD Numerou trdeoff mong technologie, mut chooe et for given roject Trend tord rogrmmle IC Belt Wrn () Digitl circuit deign IC () Phyicl imlementtion Digitl Deign e Coyright Frn Vhid
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