CS99S Laboratory 2 Preparation Copyright W. J. Dally 2001 October 1, 2001


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1 CS99S Lortory 2 Preprtion Copyright W. J. Dlly 2 Octoer, 2 Ojectives:. Understnd the principle of sttic CMOS gte circuits 2. Build simple logic gtes from MOS trnsistors 3. Evlute these gtes to oserve logic function, DC chrcteristics, nd AC chrcteristics The MOS Trnsistor Almost ll of modern digitl electronics re uilt from one simple device, the metloidesemiconductor (MOS) fieldeffect trnsistor. MOS trnsistors come in two flvors, nchnnel trnsistors sometimes clled NFETs, nd pchnnel trnsistors (PFETs). A FET hs three terminls the gte, the, nd the drin. The schemtic symol for n NFET is shown elow with the terminls leled. The schemtic symol does not distinguish etween the nd drin terminls. This is ecuse they re interchngele, for n NFET, whichever terminl is more negtive is the nd the other is the drin. gte drin gte drin closed if gte= nd = open if gte= otherwise undefined For the purposes of understnding logic circuits, we cn model the NFET s switch etween the nd the drin tht is controlled y the gte. When the gte voltge is high (logic ) nd the voltge is low (logic ), the switch is closed effectively connecting the nd drin. When the gte is low (logic ), the switch is open disconnecting the nd drin. When the gte is high (logic ) nd the more negtive of the other two terminls is not t zero, the stte of the trnsistor is undefined. For this reson, we cn use n NFET to pss zeros, ut not ones we use PFET to pss s. gte drin gte closed if gte= nd = open if gte= otherwise undefined drin The PFET works ectly the sme wy n NFET does if you reverse nd. The PFET is open (or off) when the gte is high nd closed (or on) when the gte is low nd the is high hence it cn pss logic or not under control of the gte. The schemtic symol for PFET is shown ove long with our switch model for the PFET. For the PFET the is the more positive of the two interchngele terminls, so we
2 tend to drw it on the top (y convention we drw schemtics with voltge decresing from top to ottom nd signls propgting from left to right). The symol for the PFET is the sme s the NFET ecept tht it includes n inversion ule on the gte terminl. This ule indictes logicl inversion from to or to indicting tht the device is on when the gte is s opposed to the NFET which is on when the gte is. Series nd prllel switches We cn perform logicl function y connecting two switches or two FETs together in series or prllel. For emple, terminl c t the left elow will e connected to if AND re oth. Similrly, terminl f t the right elow will e connected to if either d OR e (or oth of them) is. c d e f We cn uild similr series nd prllel circuits out of PFETs. Also, while these re 2 input series nd prllel networks, we cn clerly etend these circuits to hndle n ritrry numer of inputs. Prep question : Drw n NFET network tht connects the output to when AND ( OR c) is true ( ( c) in shorthnd). Mking n Inverter To e composle circuit must generte n output tht is suitle for use s n input to similr circuit. A simple series or prllel comintion of NFETs s shown ove won t do this since the input needs to e either or, ut the output is either or open circuited. We need to dd PFETs (or resistor) to generte on the output in this stte. The simplest composle circuit is the inverter, shown ove long with its schemtic symol. When input is, the NFET is on nd the PFET is off, so output is. Similrly, when input is, output is connected to vi the PFET nd the NFET is off. To sve time in drwing, we use the schemtic symol on the left to indicte n inverter
3 nd omit the power supply connections (to nd ). In short, the inverter genertes the logicl inverse of its input. We sy tht = NOT(), or = ~ (for shorthnd). Logic Functions nd Boolen Alger While inverters re useful (signls never seem to e the polrity you wnt) we need to comine multiple logic signls to compute most functions. We cn specify logicl function of severl vriles in severl wys including n eqution or truth tle. For emple, the eqution for the NAND (not nd) function is = NOT( AND ), or = ~( ) for shorthnd. A truth tle shows the vlue of the function for every possile comintion of input vlues. For emple, the truth tle for the NAND function is: Sometimes it is convenient to write our truthtle out in two dimensions with the vlues of long one is nd the vlues of long the other. This form of truth tle for the NAND is shown elow nd is clled Krnugh (pronounced Crgnw) mp. Just like we re used to using lgeric identities to simplify equtions using + nd * nd rel numer vriles, we cn use the identities of Boolen Alger to simplify equtions using NOT (~) AND ( ), nd OR ( ) nd inryvlued vriles. The sic lws of Boolen Alger re Zero = = Identity = = Negtion ~ = ~ = ~(~) = ~ = ~ = Commuttivity = = Associtivity ( c) = ( ) c ( c) = ( ) c Distriutivity ( c) = ( ) ( c) ( c) = ( ) ( c) Idempotence = = De Morgn s ~( ) = ~ ~ ~( ) = ~ ~ Note tht these rules re similr to, ut not identicl to those of lger over + nd *. For emple, we cn distriute OR over AND nd AND over OR, ut we cn only distriute * over + nd not the other wy round. Also, + nd * re certinly not idempotent. For this reson I discourge people from using + nd * to represent OR nd AND respectively lthough it is common prctice.
4 We cn esily convert ck nd forth etween truth tles nd equtions. To write the truth tle for n eqution, just sustitute ll possile vlues of the input vriles into the eqution nd evlute the resulting epression. Ech set of vlues gives one row of the truth tle. To convert from truth tle to n eqution, we cn write the logic function in norml form s sum of products (n OR of ANDs). For ech line of the truth tle for which the output is, write down the AND tht corresponds to tht line (e.g., ~ ~ corresponds to the line =, =) nd OR the resulting ANDs together. For emple, the norml form for NAND gte is (~ ~) (~ ) ( ~). We cn then pply the lws of Boolen lger to simplify this epression to ~ ~. Prep question 2: Write down the norml form nd simplify the eqution for the following truth tle. Logic Gtes To implement logicl function of multiple signls, we uild logic gte, s shown elow, y replcing the PFET of the inverter with network (e.g., series or prllel) of PFETs tht pulls up (connects the output to ) when some logicl function, f, of the inputs is true, so the output,, is when f(,, ) is true. To hndle the cse when f is flse, we replce the NFET of the inverter with network of NFETs tht pulls down the output (connects it to ) when f is flse, so the output is when ~f(,, ) is true. PFET Network NFET Network We mke NAND gte (or notnd) gte, s shown elow, y using series network for the pulldown side of the gte so the output is when AND re oth (in shorthnd, when = ). We use prllel network of PFETs to pull up the output when OR is zero (in shorthnd when ~ ~ = ). Thus, for this connection, f = ~( ) = ~ ~. nd ~f =. The circuit digrm for the NAND nd its schemtic symols re shown elow. The schemtic symol on the left reflects the = ~( ) interprettion the squred gte
5 symol mens AND nd the ule (s ove) mens NOT, so = NOT( AND ) or ~( ). The symol on the right is the = ~ ~ interprettion, the rounded gte symol mens OR nd the inversion ules gin men not, so = (NOT ) OR (NOT ) or ~ ~. This is the sme function s ~( ) write out the truth tles to convince yourself if you re not sure. Another useful gte is the NOR gte which hs the eqution = ~( ). The two symols for the NOR gte re shown elow long with the truth tle for NOR Prep question 3: Sketch trnsistor digrm for 2input NOR gte. At this point, you my hve noticed tht ll of the gtes we re mking re inverting. This is ecuse the NFETs tke input to generte output nd the PFETs tke input to mke output. Any sttic CMOS gte you mke ccording to the rules ove will e inverting. To mke noninverting gte, like n AND we need to use two levels of gtes s shown elow. The figure t the left shows how we relize the AND function with NAND gte nd n inverter. Note tht we cn drw n inverter with the ule on either side nd here we oey the convention tht we connect ules to ules to preserve the polrity of the logic. The figure t the right is the schemtic symol for n AND gte. Finlly we lso show the truth tle for n AND. ~
6 As noted in the reding, n inverting gte like NAND is complete in tht we cn uild ny function out of just NAND gtes. This is not true of AND gtes since there is no wy to mke n inverter out of n AND. Prep question 4: Show how to crete n OR gte y composing inverting gtes. Another useful logic function is eclusiveor, sometimes clled XOR. The eqution for XOR is = ( ~) (~ ) nd we sometimes revite XOR y writing =. The truth tle for XOR is shown elow in oth forms. Prep question 5 (optionl chllenge question): Sketch n implementtion of n XOR gte using NFETs nd PFETs. A prize goes to the solution with the minimum numer of trnsistors. The CD47 To eperiment with uilding sttic CMOS logic gtes from MOS trnsistors, we will e using the Firchild CD47 integrted circuit. As shown in the pinout elow, this device consists of three NFETs nd three PFETs with some of their terminls tied together. Note tht you must tie pin 4 to (Vdd) nd pin 7 to (GND) for this prt to work properly. Using this device, we will wire up some simple logic gtes nd chrcterize their AC nd DC chrcteristics. The gtes we will wire up will e. An inverter
7 2. A 2input NAND gte 3. A ~( ( c)) gte (see prep question ). 4. (optionl) Your XOR gte from prep question 5 In preprtion for the l, sketch how you will wire up these gtes using the CD47. Specificlly, drw schemtic showing the pins used y the, gte, nd drin of ech trnsistor. Once you wire up these three gtes, you will evlute ech of them using the following three steps.. Verify their logicl opertion using switch inputs nd n LED s output. Note tht due to the low drive strength of the CD47, you my need to uffer the LED using your 74AC4. 2. Trce the DC trnsfer curve input voltge vs. output voltge for t lest one of your gtes. 3. Oserve the AC trnsfer curve input nd output wveforms vs time.
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