About Programmable Logic Controller - step by step
|
|
|
- Mae Horton
- 10 years ago
- Views:
Transcription
1 Edward HRYNKIEWIZ, Mirosław HMIEL Politechnika Śląska, Instytut Elektroniki bout Programmable Logic ontroller - step by step treszczenie. W artykule krok po kroku przedstawiona jest i objaśniona podstawowa struktura logicznego sterownika programowalnego (PL) oraz omawione są podstawy programowania takiego sterownika. utorzy prowadzą czytelnika od prostego cyfrowego układu mikroprogramowanego poprzez kolejne etapy rozbudowy o licznik programu, dekoder instrukcji, moduły wejścia wyjścia, liczniki i układy czasowe, wewnętrzne magistrale układ arytmetyczno logicznywyjaśniając diałanie sterownika, ideę programowania i jego wykorzystanie. Ponadto zaprezentowano kilka prostych przykładów zastosowania. (O programowalnym sterowniku logicznym - krok po kroku). bstract. In the paper a structure of PL and PL programming are described and explained step by step. The authors start description from simple micro-programmed digital circuit and next developing it with program counter, instruction decoder, input/output modules, counter and timer modules, internal busses and arithmetic logic unit explain an operation of the PL and the idea of programming and utilization of such devices. few examples of considered PL simple applications are presented. łowa kluczowe: mikroprogramowany, struktura programowanego sterownik logiczny (PL), programowanie sterowników. Keywords: micro-programmed digital circuit, PL structure, PL programming. Introduction Programmable logic controllers (PL) are used for control different processes in industry, automotive, intelligent buildings and other applications. Due to this fact they should be universal. n universality is obtained by reconfigurability (the PLs are equipped with different I/O modules) and programmability (the PLs are specialized for given control task by configuring and programming). Even though the programmable logic controllers are first applied in industry at seventies years of the last century the questions are often asked about their structure and the way of their operation. There are a lot of publications devoted to programmable logic controllers as for example [1,2,3,4,5,6,7,8,9] but they describe them on very general level. From the point of view of electronic structure a PL is a especially designed digital system. The idea of such system will be explained by means of following example: Example 1 Let us consider a control unit for an electric heater. The heater is equipped with push button for controlling a fan, push button B for controlling a heater and sensor informing that adjusted temperature has been reached. n operation of the electric heater may be described by the state diagram presented in fig heater and fan are switched of 2 - fan is switched on 3 - heater and fan are switched on Fig.2. The heater control unit in counter-multiplexer version. t the moment let us change the structure of the electric heater and its behavior at state 3. Let us equip the heater fun with fan rotor revolution sensor D. The sensor output equal to logic 1 means that the fun operates properly. The fun is out of operation if the sensor output is equal to logic 0. In state 3 the condition is checked and if it is equal to logic 0 the system goes to state 3 in which the condition D is observed. If D is equal to logic 0 the heater is immediately turned off. In opposite situation the system come back to state 3. This is shown in state diagram presented in fig. 3. Fig.1. tate diagram for example 1. To design a control unit it is necessary to introduce state encoding: For such state encoding the state diagram from fig.1. may be implemented in logic circuit shown in fig.2. Fig.3. Modified state diagram from Fig.1. tate encoding for modified state diagram can be written as follows: PRZEGLĄD ELEKTROTEHNIZNY (Electrical Review), IN , R. 88 NR 9a/2012
2 If control unit is described by a state diagram consisting of the states from which there are two outputs - one to the same state and other to the next state (as it is seen in fig.1.) - the implementation may be done in counter- multiplexer form. For the state diagram shown in fig.3. such implementation would be complicated and expensive. better solution is utilizing microprogrammed control circuit shown in fig.4 [10,11]. Next Fun switch on Heater switch on connected to the condition multiplexer too, as it was shown in fig.6. The condition flip flop (FF) is set at the beginning of series of test instructions. uch arrangement supports calculation of logic product (conjunction) of binary variables - inputs and outputs for example. This way we obtain simple programmable logic controller (PL) which may be called logic or bit processor [12,13,14]. D3 D2 D1 D0 D1 Q1 2 LK D0 Q0 ddress register 1 0 ROM D B ond. ounter Fig.4. The microprogrammed implementation of the control unit described be the state diagram shown in Fig.3. The microprogram stored in Read Only Memory (ROM) is written in Table 1. Table 1. The microprogram representing the state diagram from fig.4. ctual Data tate Q 1 Q 0 ond. Next Fan Heater D 3 D 2 D 1 D The ROM in fig.4 has only four bits output word and three bits. But when a control task is more complicated, especially when number of states in state diagram is large and number of output control signals is large the ROM capacity become large too. To avoid expanding of a number of output word bits the counter may be used for generating an instead of storing next in memory. Moreover the states of output signals may be coded. It means that it is necessary to use decoder (called instruction decoder) at the memory outputs to obtain control signals for particular states of control unit. ome decoded instructions are dedicated for the control unit itself (for example such instruction is jump which writes-in to the program counter new when it occurs in control program). The described modifications are shown in fig.5. The tructure of a imple PL In solution shown in fig.5. a valid condition is chosen by means of an of current state. More universal ing a valid condition may be done directly from the program memory. It means that a condition test instruction is stored in a memory together with the condition. The states of output signals may be set or reset in the same way. To create possibility for testing the output states and for designing sequential automata the outputs should be Fig.5. The control unit with program counter and instruction decoder. Fig.6. The structure of simple programmable logic controller logic processor. PL Programming Despite simplicity of presented logic controller its functionality is relatively high. ssuming instruction list presented below one can use it in different industrial applications for control binary objects. Mnemonic Test I/O et et(ff=1) et(ff=0) Reset Reset(FF=1) Data 304 PRZEGLĄD ELEKTROTEHNIZNY (Electrical Review), IN , R. 88 NR 9a/2012
3 Reset(FF=0) Jump Jump(FF=1) Jump(FF=0) NOP Reset(FF=0) 0111 Jump 1000 Jump(FF=1) 1001 Jump(FF=0) 1010 NOP 0000 Example 2 Let us use the programmable logic controller instead the relay flip flop with dominative reset (R) (see fig.7). Therefore taking into account the PL es assigned to the inputs and output the program describing PL operation as flip-flop with dominating reset (R) may be written as: line instr. number code addr. 0. Test R Jump(FF=1) line Test Jump(FF=1) line Test Q et(ff=1) Q Reset(FF=0) Q Jump line t the moment let us come back to the above considered heater control. Using denotations: Fig.7. The relay flip flop with dominative reset. H heater F fun D fun operation sensor R main switch fun switch B heater switch set temperature reached For PL input ing as it is seen in fig.9. Fig.8. The exemplary es of PL inputs and output. The inputs and R are applied to PL pins 3 and 5 as it is shown in fig.8. The output Q at pin 4 represents the state of the relay Q from fig.7. The control program for which the PL operates in the same way as relay flip flop has a form as follows: 0. Test R 1. Jump(FF=0) line6 2. Test 3. Jump(FF=1) line5 4. Test Q 5. et(ff=1) Q 6. Reset(FF=0) Q 7. Jump line0 One can notice that at line 7 is jump to line 0. It means that control program is executed in serial-cyclic way. This is typical for programmable logic controllers. In the system the instructions are represented by the code words. For example the following coding can be used in the considered controller: Mnemonic ode Test 0001 et 0010 et(ff=1) 0011 et(ff=0) 0100 Reset 0101 Reset(FF=1) 0110 Fig.9. The exemplary PL input ing for heater control. One can write the heater control program in the following form: line instr. number code addr. 0 Test R Jump(FF=1) line Test H Jump(FF=0) line Test D Reset(FF=0) H Reset(FF=0) F Test Reset(FF=1) H Reset(FF=1) F Test et(ff=1) F Test B et(ff=1) H Jump Reset H Reset F Jump line PRZEGLĄD ELEKTROTEHNIZNY (Electrical Review), IN , R. 88 NR 9a/2012
4 From imple to Developed PL In practical applications it is necessary to delay some actions of the controller. It happens, for example, when set of conveyors are controlled (a next conveyor is typically switched on few seconds after previous one) or when a buzzer is switched on for a few seconds before machine drive is put into operation. In such application a timer have to be used. For PL types as considered in this section a timer is hardware module with manually adjustable delay time or a value of time delay can be programmed by means load operation (L). Its inputs are located in PL output area while its state is tested as a typical input. The way of timer connection to PL structure is shown in fig.10. The instruction set starts a timer while instruction reset prepares the timer to next using. The example of timer using is presented below: fg FF et l LP c Q Q FF J K Jump T R Instruction decoder ROM Inputs l Reg. et Reset Output register E Timer R OUTs (Ys) 0. Test ondition 1. Jump(FF=0) line3 2. et(ff=1) Timer 3. Test Timer 4. Jump(FF=0) line7 5. et(ff =1) Output 6. Reset Timer 7.??? In some applications a controller should count manufactured elements or external events. To provide a controller with such functionality it should be equipped with a counter module. The value to each a counter should count may be adjusted by means a few positions tomb wheels or it may be programmed by means load operation (L). The connection of such counter to the considered PL structure is shown in fig.10. Fig.10. The PL with a timer and counter. U ounter s it was said before presented programmable logic controller is able to control binary objects. To control continuous (analog) objects the unit should be equipped with D and D converters and arithmetic logic unit (LU) for processing numeric values. The general block diagram of such PL is shown in fig.11. Beside load instruction (L) a few of new instructions have to be added to the instruction set for control numeric operations. These are addition ( + ), subtraction ( - ) and comparison (omp). numeric value is loaded always to the accumulator 1. Next load causes that new value is written to the 1 while previous state of 1 is transmitted to accumulator 2. The comparison operation compares value in 1 to value in 2. R E Fig.11. The whole structure of the PL. 306 PRZEGLĄD ELEKTROTEHNIZNY (Electrical Review), IN , R. 88 NR 9a/2012
5 Example 3 Let us write control program which switch on binary output when numeric value of analog input reaches value 150 and switch off this output when the numeric value drops to value 50. It means that it is dual level control with hysteresis (see fig.12). The control program written with using the mnemonics assumed above has the following form: 0. Load IN 1. Load omp 3. Test 1<2 4. Reset(FF=1) OUT 5. Jump(FF=1) line11 6. Load IN 7. Load omp 9. Test 1>2 10. et(ff=1) OUT 11. Jump line 0 Fig.12. The analog control example. onclusions In the paper the structure of programmable logic controller was described and idea of such unit programming and applications was explained on few simple examples. In fig.11. the arithmetic-logic unit was included for word operation execution as, for example, results of analogue to digital conversion comparison to given value (see example 3). In more sophisticated constructions a microprocessor/ microcontroller may be used for byte/word operation instead of arithmetic logic unit [15]. uch PL structure is called bitbyte [16,17] because bit operations are executed by above described fast bit-processor while byte/word operations are executed in software way by microprocessor. The bit-byte structure of the PL one can meet in number of PLs present on the market [1,4,12]. The PL structure can be considered as bit-byte even though the manufacturers introduced their product as microprocessor based but they usually offer special module for fast bit operations [13]. The processors in bit-byte structure of PL can execute their operations concurrently. Very interesting problem is how to put both processors in concurrent operation as far as it is possible? More about this problem a reader can find in [18,19]. It is necessary to added that a PL programming was standardized. The reader should refer to the standard EN/PN where control program representation forms are described [20]. The paper is the authors replay for questions expressed by the new PL users who often are not electronic engineers. cknowledgement The works was supported by Ministry of cience and Higher Education of Republic of Poland No, 5391/B/T02/2010/38 REFERENE [1] Michel G.: Programmable Logic ontrollers, rchitecture and pplications. John Wiley & ons, West ussex, England, 1990 [2] Broel-Plater B.: terowniki programowalne, właściwości I zasady stosowania (Programmable Logic ontrollers, Features and Rules of pplication). eria Tempus. zczecin, Wydziała Elektryczny Politechniki zczecińskiej, Poland, 2000 [3] Erickson K.T.: Programmable Logic ontrollers. IEEE Potentials, vol.15, no.1, Feb.-March 1996, pp Publisher: IEEE, U, 1996 [4] Irwin J.D.: Industrial Electronics. Handbook. R Handbook Published in ooperation with IEEE Press 1997 [5] Kwaśniewski J.: Programowalne sterowniki przemysłowe w systemach sterowania (PL in ontrol ystems). Fundacja Dobrej Książki, Kraków, Poland, 1999 [6] Mandado E., Marcos J., Perez..: Programmable Logic Devises and Logic ontrollers. Prentice Hall, London 1996 [7] Warnock I. G.: Programmable ontrollers. Operation and pplication. Hemel Hempdtead, Prentice Hall Int., 1998 [8] Legierski T., Kasprzyk J., Wyrwał J., Hajda J.: Programowanie sterowników PL (Programming PL). Wydawnictwo Komputerowe Jacka kalmierskiego, Gliwice, 2008 [9] hmiel M., Mocha J., Hrynkiewicz E., Milk.: entral Processing Units for PL implementation in Virtex-4 FPG. Proceedings of the 18th IF World ongress, ugust 28- eptember 2, Milano, Italy, 2011 [10] Łuba T.:Układy mikroprogramowane (Microprogrammed circuits). Oficyna Wydawnicza Politechniki Warszawskiej, Poland, 1996 [11] Molski M.: Modułowe i mikroprogramowalne układy cyfrowe (Module and microprogrammed digital curcuits). WKŁ, Warszawa, Poland, 1986 [12] Getko Z.: Programmable systems of binary control in PL, Elektronizacja, WKiŁ, Warszawa, 1983 (in polish) [13] Donandt J.: Improving response time of Programmable Logic ontrollers by use of a Boolean coprocessor, IEEE omput. oc. Press. 4: , Washington, D, U, 1989 [14] ramaki N., himokawa Y., Kuno., aitoh T., Hashimoto H.: new rchitecture for High-performance Programmable Logic ontroller, Proc. of the IEON 97 23rd Inter. onf. on Industrial Electronics, ontrol and Instrumentation, IEEE part vol.1, pp , New York, U, 1997 [15] Milik., Hrynkiewicz E.: PID Module for Reconfigurable Logic ontroller. Preprints of the IF Workshop on Programmable Devices and ystems, PDe 2000, Ostrava, zech Republic, February 2000 [16] hmiel M., Hrynkiewicz E.: Remarks on Parallel Bit-Byte PU structures of Programmable Logic ontrollers. In: Design of Embedded ontrol ystems, ection V, (damski M.., Karatkevich., Węgrzyn M), pp , pringer cience+business Media, Inc., 2005 [17] hmiel M., Mocha J., Hrynkiewicz E.: FPG-Based Bit- Word PL PUs Development Platform, The International IF Workshop on Programmable Devices and Embedded ystems, PDe 10, October 6-7, Pszczyna, Poland, pp , 2010 [18] hmiel M., Hrynkiewicz E., Milik.: oncurrent operation of the processors in Bit-Byte PU of a PL, Preprints of the IF World ongress, Prague, zech Republic, July 3-8, 2005 [19] hmiel M., Hrynkiewicz E.: Fast Operating Bit-Byte PL, Preprints of the 17th IF World ongress (on DVD-ROM), eoul, Korea, July 6-11, pp , 2008 [20] Norma PN-EN :2004(U). Programmable ontrollers - Part 3; Programming Languages, International Electrotechnical ommission, Geneva, 2004 uthors: dr hab. inż. Edward Hrynkiewicz, prof. Politechniki Śląskiej, dr inż. Mirosław hmiel, Politechnika Śląska, Instytut Elektroniki, ul. kademicka 16, Gliwice, [email protected], [email protected] 307 PRZEGLĄD ELEKTROTEHNIZNY (Electrical Review), IN , R. 88 NR 9a/2012
MICROPROCESSOR. Exclusive for IACE Students www.iace.co.in iacehyd.blogspot.in Ph: 9700077455/422 Page 1
MICROPROCESSOR A microprocessor incorporates the functions of a computer s central processing unit (CPU) on a single Integrated (IC), or at most a few integrated circuit. It is a multipurpose, programmable
Chapter 2 Logic Gates and Introduction to Computer Architecture
Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are
MICROPROCESSOR AND MICROCOMPUTER BASICS
Introduction MICROPROCESSOR AND MICROCOMPUTER BASICS At present there are many types and sizes of computers available. These computers are designed and constructed based on digital and Integrated Circuit
AUTOMATIC NIGHT LAMP WITH MORNING ALARM USING MICROPROCESSOR
AUTOMATIC NIGHT LAMP WITH MORNING ALARM USING MICROPROCESSOR INTRODUCTION This Project "Automatic Night Lamp with Morning Alarm" was developed using Microprocessor. It is the Heart of the system. The sensors
Programming Logic controllers
Programming Logic controllers Programmable Logic Controller (PLC) is a microprocessor based system that uses programmable memory to store instructions and implement functions such as logic, sequencing,
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill
Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill Objectives: Analyze the operation of sequential logic circuits. Understand the operation of digital counters.
Programmable Logic Controllers Definition. Programmable Logic Controllers History
Definition A digitally operated electronic apparatus which uses a programmable memory for the internal storage of instructions for implementing specific functions such as logic, sequencing, timing, counting,
ETEC 2301 Programmable Logic Devices. Chapter 10 Counters. Shawnee State University Department of Industrial and Engineering Technologies
ETEC 2301 Programmable Logic Devices Chapter 10 Counters Shawnee State University Department of Industrial and Engineering Technologies Copyright 2007 by Janna B. Gallaher Asynchronous Counter Operation
150127-Microprocessor & Assembly Language
Chapter 3 Z80 Microprocessor Architecture The Z 80 is one of the most talented 8 bit microprocessors, and many microprocessor-based systems are designed around the Z80. The Z80 microprocessor needs an
Programmable Logic Controller PLC
Programmable Logic Controller PLC UPCO ICAI Departamento de Electrónica y Automática 1 PLC Definition PLC is a user friendly, microprocessor based, specialized computer that carries out control functions
SAFE IMPLEMENTATION OF AUTOMATIC MICROPROCESSOR SYSTEMS OF LEVEL CROSSING ON THE EXAMPLE OF THE SPA-4 SYSTEM
TRANSPORT PROBLEMS 2007 PROBLEMY TRANSPORTU Tom 2 Zeszyt 2 MIECZYSŁAW KORNASZEWSKI*, ZBIGNIEW ŁUKASIK Technical University of Radom Faculty of Transport Malczewskiego 29, 26 600 Radom, Poland *Corresponding
(Cat. No. 1775-L3) Product Data
(Cat. No. 1775-L3) Product Data When it comes to programmable controllers, the more power you can put into a chassis slot, the more control potential you have. The PLC-3 programmable controller, already
Lecture N -1- PHYS 3330. Microcontrollers
Lecture N -1- PHYS 3330 Microcontrollers If you need more than a handful of logic gates to accomplish the task at hand, you likely should use a microcontroller instead of discrete logic gates 1. Microcontrollers
Lecture 8: Synchronous Digital Systems
Lecture 8: Synchronous Digital Systems The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered
How to read this guide
How to read this guide The following shows the symbols used in this Quick start guide with descriptions and examples. Symbol Description Example P oint Reference Caution [ ] This symbol explains information
A Parallel Processor for Distributed Genetic Algorithm with Redundant Binary Number
A Parallel Processor for Distributed Genetic Algorithm with Redundant Binary Number 1 Tomohiro KAMIMURA, 2 Akinori KANASUGI 1 Department of Electronics, Tokyo Denki University, [email protected]
Read-only memory Implementing logic with ROM Programmable logic devices Implementing logic with PLDs Static hazards
Points ddressed in this Lecture Lecture 8: ROM Programmable Logic Devices Professor Peter Cheung Department of EEE, Imperial College London Read-only memory Implementing logic with ROM Programmable logic
Fig 3. PLC Relay Output
1. Function of a PLC PLC Basics A PLC is a microprocessor-based controller with multiple inputs and outputs. It uses a programmable memory to store instructions and carry out functions to control machines
CSE2102 Digital Design II - Topics CSE2102 - Digital Design II
CSE2102 Digital Design II - Topics CSE2102 - Digital Design II 6 - Microprocessor Interfacing - Memory and Peripheral Dr. Tim Ferguson, Monash University. AUSTRALIA. Tel: +61-3-99053227 FAX: +61-3-99053574
An Introduction to MPLAB Integrated Development Environment
An Introduction to MPLAB Integrated Development Environment 2004 Microchip Technology Incorporated An introduction to MPLAB Integrated Development Environment Slide 1 This seminar is an introduction to
Microcontroller-based experiments for a control systems course in electrical engineering technology
Microcontroller-based experiments for a control systems course in electrical engineering technology Albert Lozano-Nieto Penn State University, Wilkes-Barre Campus, Lehman, PA, USA E-mail: [email protected]
INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 ISSN 0976 6464(Print)
Computer Organization and Components
Computer Organization and Components IS1500, fall 2015 Lecture 5: I/O Systems, part I Associate Professor, KTH Royal Institute of Technology Assistant Research Engineer, University of California, Berkeley
To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC.
8.1 Objectives To design digital counter circuits using JK-Flip-Flop. To implement counter using 74LS193 IC. 8.2 Introduction Circuits for counting events are frequently used in computers and other digital
(Refer Slide Time: 00:01:16 min)
Digital Computer Organization Prof. P. K. Biswas Department of Electronic & Electrical Communication Engineering Indian Institute of Technology, Kharagpur Lecture No. # 04 CPU Design: Tirning & Control
Design and Implementation of an Accidental Fall Detection System for Elderly
Design and Implementation of an Accidental Fall Detection System for Elderly Enku Yosef Kefyalew 1, Abubakr Rahmtalla Abdalla Mohamed 2 Department of Electronic Engineering, Tianjin University of Technology
Chapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language
Chapter 4 Register Transfer and Microoperations Section 4.1 Register Transfer Language Digital systems are composed of modules that are constructed from digital components, such as registers, decoders,
Computer System: User s View. Computer System Components: High Level View. Input. Output. Computer. Computer System: Motherboard Level
System: User s View System Components: High Level View Input Output 1 System: Motherboard Level 2 Components: Interconnection I/O MEMORY 3 4 Organization Registers ALU CU 5 6 1 Input/Output I/O MEMORY
Digitale Signalverarbeitung mit FPGA (DSF) Soft Core Prozessor NIOS II Stand Mai 2007. Jens Onno Krah
(DSF) Soft Core Prozessor NIOS II Stand Mai 2007 Jens Onno Krah Cologne University of Applied Sciences www.fh-koeln.de [email protected] NIOS II 1 1 What is Nios II? Altera s Second Generation
Computer Systems Structure Main Memory Organization
Computer Systems Structure Main Memory Organization Peripherals Computer Central Processing Unit Main Memory Computer Systems Interconnection Communication lines Input Output Ward 1 Ward 2 Storage/Memory
Control of Boiler Operation using PLC SCADA
Control of Boiler Operation using PLC SCADA K. Gowri Shankar Abstract This paper outlines the various stages of operation involved in the conversion of a manually operated boiler towards a fully automated
Programming A PLC. Standard Instructions
Programming A PLC STEP 7-Micro/WIN32 is the program software used with the S7-2 PLC to create the PLC operating program. STEP 7 consists of a number of instructions that must be arranged in a logical order
Microcontroller Based Anti-theft Security System Using GSM Networks with Text Message as Feedback
International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 2, Issue 10 (August 2012), PP. 18-22 Microcontroller Based Anti-theft Security System
EE360: Digital Design I Course Syllabus
: Course Syllabus Dr. Mohammad H. Awedh Fall 2008 Course Description This course introduces students to the basic concepts of digital systems, including analysis and design. Both combinational and sequential
Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa
Experiment # 9 Clock generator circuits & Counters Eng. Waleed Y. Mousa 1. Objectives: 1. Understanding the principles and construction of Clock generator. 2. To be familiar with clock pulse generation
A SHORT NOTE ON RELIABILITY OF SECURITY SYSTEMS
A SHORT NOTE ON RELIABILITY OF SECURITY SYSTEMS Jóźwiak Ireneusz J., Laskowski Wojciech Wroclaw University of Technology, Wroclaw, Poland Keywords computer security, reliability, computer incidents Abstract
Module 3: Floyd, Digital Fundamental
Module 3: Lecturer : Yongsheng Gao Room : Tech - 3.25 Email : [email protected] Structure : 6 lectures 1 Tutorial Assessment: 1 Laboratory (5%) 1 Test (20%) Textbook : Floyd, Digital Fundamental
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Question Bank Subject Name: EC6504 - Microprocessor & Microcontroller Year/Sem : II/IV
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Question Bank Subject Name: EC6504 - Microprocessor & Microcontroller Year/Sem : II/IV UNIT I THE 8086 MICROPROCESSOR 1. What is the purpose of segment registers
PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 OUTCOME 3 PART 1
UNIT 22: PROGRAMMABLE LOGIC CONTROLLERS Unit code: A/601/1625 QCF level: 4 Credit value: 15 OUTCOME 3 PART 1 This work covers part of outcome 3 of the Edexcel standard module: Outcome 3 is the most demanding
Computer organization
Computer organization Computer design an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + datapath Control = finite state machine inputs
REMOTE CONTROL AND MONITORING OF AN INDUCTION MOTOR
Proceedings of COMADEM 2007 The 20 th International Congress on Condition Monitoring and Diagnostic Engineering Management Faro, Portugal, June 13-15, 2007 REMOTE CONTROL AND MONITORING OF AN INDUCTION
Automating witfi STEP7 in LAD and FBD
Automating witfi STEP7 in LAD and FBD Programmable Controllers SIMATIC S7-300/400 by Hans Berger 2nd revised edition, 2001 Publicis MCD Corporate Publishing Contents Contents Indroduction 19 1 SIMATIC
Sensor network infrastructure for intelligent building monitoring and management system
Sensor network infrastructure for intelligent building monitoring and management system 1 R.VENKATESH, 2 K.RADHA, 3 M.GANTHIMATHI 1.B.E-CSE, Muthayammal Engineering College, Rasipuram. 2. Assistant Professor
Automating with STEP7 in LAD and FBD
bisk Automating with STEP7 in LAD and FBD Programmable Controllers SIMATIC S7-300/400 by Hans Berger Publicis MCD Verlag Contents Indroduction 19 1 SIMATIC S7-300/400 Programmable Controller... 20 1.1
Digital Design. Assoc. Prof. Dr. Berna Örs Yalçın
Digital Design Assoc. Prof. Dr. Berna Örs Yalçın Istanbul Technical University Faculty of Electrical and Electronics Engineering Office Number: 2318 E-mail: [email protected] Grading 1st Midterm -
Keywords ATM Terminal, Finger Print Recognition, Biometric Verification, PIN
ATM Terminal Security Using Fingerprint Reconition. Prof. B.Jolad, Tejshree Salunkhe, Rutuja Patil, Puja Shindgi Padmashree Dr. D. Y. Patil Institute Of Engineering and Technology,Pimpri,Pune - 411018
Counters and Decoders
Physics 3330 Experiment #10 Fall 1999 Purpose Counters and Decoders In this experiment, you will design and construct a 4-bit ripple-through decade counter with a decimal read-out display. Such a counter
EE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/20 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
TIMING, COUNTING, AND DATA-HANDLING INSTRUCTIONS. Key Points
M O D U L E F O U R TIMING, 4 COUNTING, AND DATA-HANDLING INSTRUCTIONS Key Points This module is a further exploration of the MicroLogix s programming instructions. Module 3 covered basic relay instructions,
An overview of Computerised Numeric Control (C.N.C.) and Programmable Logic Control (P.L.C.) in machine automation
An overview of Computerised Numeric Control (C.N.C.) and Programmable Logic Control (P.L.C.) in machine automation By Pradeep Chatterjee, Engine Division Maintenance, TELCO, Jamshedpur 831010 E-mail: [email protected]
PROGRAMMABLE LOGIC CONTROL
PROGRAMMABLE LOGIC CONTROL James Vernon: control systems principles.co.uk ABSTRACT: This is one of a series of white papers on systems modelling, analysis and control, prepared by Control Systems Principles.co.uk
Designing an efficient Programmable Logic Controller using Programmable System On Chip
Designing an efficient Programmable Logic Controller using Programmable System On Chip By Raja Narayanasamy, Product Apps Manager Sr, Cypress Semiconductor Corp. A Programmable Logic Controller (PLC) is
LADDER LOGIC/ FLOWCHART PROGRAMMING DIFFERENCES AND EXAMPLES
page 1/10 This document is designed as a quick-start primer to assist industrial automation programmers who are familiar with PLCs and Relay Ladder Logic programming to better understand the corresponding
Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop.
Objectives Having read this workbook you should be able to: recognise the arrangement of NAND gates used to form an S-R flip-flop. describe how such a flip-flop can be SET and RESET. describe the disadvantage
Lumousoft Visual Programming Language and its IDE
Lumousoft Visual Programming Language and its IDE Xianliang Lu Lumousoft Inc. Waterloo Ontario Canada Abstract - This paper presents a new high-level graphical programming language and its IDE (Integration
Management Challenge. Managing Hardware Assets. Central Processing Unit. What is a Computer System?
Management Challenge Managing Hardware Assets What computer processing and storage capability does our organization need to handle its information and business transactions? What arrangement of computers
Introducción. Diseño de sistemas digitales.1
Introducción Adapted from: Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg431 [Original from Computer Organization and Design, Patterson & Hennessy, 2005, UCB] Diseño de sistemas digitales.1
Keywords: rainfall detection, rain sensor, buzzer and alarm system.
Volume 5, Issue 4, April 2015 ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: www.ijarcsse.com Design of Rain
Using The PIC I/O Ports
EE2801 -- Lecture 22 Using The PIC I/O Ports EE2801-L22P01 The Variety Of Available IO Ports The PIC 16F874 microcontroller has five different IO ports, accounting for thirty three of the processors forty
COMBINATIONAL CIRCUITS
COMBINATIONAL CIRCUITS http://www.tutorialspoint.com/computer_logical_organization/combinational_circuits.htm Copyright tutorialspoint.com Combinational circuit is a circuit in which we combine the different
Monitoring of the single-point diamond dresser wear
ARCHIVES OF CIVIL AND MECHANICAL ENGINEERING Vol. V 2005 No. 1 Monitoring of the single-point diamond dresser wear W. HABRAT, A. BATSCH, J. PORZYCKI Rzeszów University of Technology, ul. Wincentego Pola
CpE358/CS381. Switching Theory and Logical Design. Class 4
Switching Theory and Logical Design Class 4 1-122 Today Fundamental concepts of digital systems (Mano Chapter 1) Binary codes, number systems, and arithmetic (Ch 1) Boolean algebra (Ch 2) Simplification
PART B QUESTIONS AND ANSWERS UNIT I
PART B QUESTIONS AND ANSWERS UNIT I 1. Explain the architecture of 8085 microprocessor? Logic pin out of 8085 microprocessor Address bus: unidirectional bus, used as high order bus Data bus: bi-directional
University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54
Fall 2005 Instructor Texts University of St. Thomas ENGR 230 ---- Digital Design 4 Credit Course Monday, Wednesday, Friday from 1:35 p.m. to 2:40 p.m. Lecture: Room OWS LL54 Lab: Section 1: OSS LL14 Tuesday
Architectures and Platforms
Hardware/Software Codesign Arch&Platf. - 1 Architectures and Platforms 1. Architecture Selection: The Basic Trade-Offs 2. General Purpose vs. Application-Specific Processors 3. Processor Specialisation
COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
Interfacing Credit Card-sized PCs to Board Level Electronics
10th ICALEPCS Int. Conf. on Accelerator & Large Expt. Physics Control Systems. Geneva, 10-14 Oct 2005, PO2.062-4 (2005) Interfacing Credit Card-sized PCs to Board Level Electronics Flavio Fontanelli 1,
TYPES OF COMPUTERS AND THEIR PARTS MULTIPLE CHOICE QUESTIONS
MULTIPLE CHOICE QUESTIONS 1. What is a computer? a. A programmable electronic device that processes data via instructions to output information for future use. b. Raw facts and figures that has no meaning
Construction and Application of a Computer Based Interface Card
Session 4 Construction and Application of a Computer Based Interface Card Michael Combs Telescope Operations Engineer [email protected] Morehead State University Morehead, Kentucky Ahmad Zargari,
Collided Vehicle Position Detection using GPS & Reporting System through GSM
Collided Vehicle Position Detection using GPS & Reporting System through GSM M.M.Raghaveendra 1, N.Sahitya 2, N.Nikhila 3, S.Sravani 4 1 Asst.Professor ECE Department, 2 Student, 3 Student, 4 Student,
Computer Organization and Components
Computer Organization and Components IS5, fall 25 Lecture : Pipelined Processors ssociate Professor, KTH Royal Institute of Technology ssistant Research ngineer, University of California, Berkeley Slides
Lab Experiment 1: The LPC 2148 Education Board
Lab Experiment 1: The LPC 2148 Education Board 1 Introduction The aim of this course ECE 425L is to help you understand and utilize the functionalities of ARM7TDMI LPC2148 microcontroller. To do that,
BASIC COMPUTER ORGANIZATION AND DESIGN
1 BASIC COMPUTER ORGANIZATION AND DESIGN Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle Memory Reference Instructions Input-Output and Interrupt Complete
Measuring, Controlling and Regulating with labworldsoft
Kai-Oliver Linde IKA-Werke Staufen Neumagenstraße 27 79219 Staufen Measuring, Controlling and Regulating with labworldsoft Rapid and easy networking of lab devices from different manufacturers The user
2011, The McGraw-Hill Companies, Inc. Chapter 5
Chapter 5 5.1 Processor Memory Organization The memory structure for a PLC processor consists of several areas, some of these having specific roles. With rack-based memory structures addresses are derived
Ladder and Functional Block Programming
CHPTER 11 Ladder and Functional lock Programming W. olton This (and the following) chapter comes from the book Programmable Logic Controllers by W. olton, ISN: 9780750681124. The first edition of the book
CHAPTER 4 MARIE: An Introduction to a Simple Computer
CHAPTER 4 MARIE: An Introduction to a Simple Computer 4.1 Introduction 195 4.2 CPU Basics and Organization 195 4.2.1 The Registers 196 4.2.2 The ALU 197 4.2.3 The Control Unit 197 4.3 The Bus 197 4.4 Clocks
Logical Operations. Control Unit. Contents. Arithmetic Operations. Objectives. The Central Processing Unit: Arithmetic / Logic Unit.
Objectives The Central Processing Unit: What Goes on Inside the Computer Chapter 4 Identify the components of the central processing unit and how they work together and interact with memory Describe how
7a. System-on-chip design and prototyping platforms
7a. System-on-chip design and prototyping platforms Labros Bisdounis, Ph.D. Department of Computer and Communication Engineering 1 What is System-on-Chip (SoC)? System-on-chip is an integrated circuit
Series Six Plus Programmable Controller
Series Six Plus Programmable Controller Gl?K-0147B June 1989 Central Processor Unit 8-Slot Rack 1l-Slot Rack General Description The Central Processor Unit (CPU) for the Series Six Plus Programmable Logic
Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students
Session: 2220 Technical Aspects of Creating and Assessing a Learning Environment in Digital Electronics for High School Students Adam S. El-Mansouri, Herbert L. Hess, Kevin M. Buck, Timothy Ewers Microelectronics
İSTANBUL AYDIN UNIVERSITY
İSTANBUL AYDIN UNIVERSITY FACULTY OF ENGİNEERİNG SOFTWARE ENGINEERING THE PROJECT OF THE INSTRUCTION SET COMPUTER ORGANIZATION GÖZDE ARAS B1205.090015 Instructor: Prof. Dr. HASAN HÜSEYİN BALIK DECEMBER
Automated Security System using ZigBee
IJIRST International Journal for Innovative Research in Science & Technology Volume 2 Issue 01 June 2015 ISSN (online): 2349-6010 Automated Security System using ZigBee Sneha Susan Abraham Saveetha School
Counters. Present State Next State A B A B 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0
ounter ounters ounters are a specific type of sequential circuit. Like registers, the state, or the flip-flop values themselves, serves as the output. The output value increases by one on each clock cycle.
Machine Architecture and Number Systems. Major Computer Components. Schematic Diagram of a Computer. The CPU. The Bus. Main Memory.
1 Topics Machine Architecture and Number Systems Major Computer Components Bits, Bytes, and Words The Decimal Number System The Binary Number System Converting from Decimal to Binary Major Computer Components
Lecture-3 MEMORY: Development of Memory:
Lecture-3 MEMORY: It is a storage device. It stores program data and the results. There are two kind of memories; semiconductor memories & magnetic memories. Semiconductor memories are faster, smaller,
Location-Aware and Safer Cards: Enhancing RFID Security and Privacy
Location-Aware and Safer Cards: Enhancing RFID Security and Privacy 1 K.Anudeep, 2 Mrs. T.V.Anantha Lakshmi 1 Student, 2 Assistant Professor ECE Department, SRM University, Kattankulathur-603203 1 [email protected],
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter
NTE2053 Integrated Circuit 8 Bit MPU Compatible A/D Converter Description: The NTE2053 is a CMOS 8 bit successive approximation Analog to Digital converter in a 20 Lead DIP type package which uses a differential
Memory Elements. Combinational logic cannot remember
Memory Elements Combinational logic cannot remember Output logic values are function of inputs only Feedback is needed to be able to remember a logic value Memory elements are needed in most digital logic
AUTOMATIC LPG BOOKING, LEAKAGE DETECTION AND A REAL TIME LPG MEASUREMENT MONITORING SYSTEM
AUTOMATIC LPG BOOKING, LEAKAGE DETECTION AND A REAL TIME LPG MEASUREMENT MONITORING SYSTEM R.Padmapriya, E.Kamini, [email protected],[email protected], IV Year Electronics and Communication Engineering,
Digital Logic Design Sequential circuits
Digital Logic Design Sequential circuits Dr. Eng. Ahmed H. Madian E-mail: [email protected] Dr. Eng. Rania.Swief E-mail: [email protected] Dr. Eng. Ahmed H. Madian Registers An n-bit register
Automazione Industriale 3 - I linguaggi di programmazione.
Automation Robotics and System CONTROL Università degli Studi di Modena e Reggio Emilia Automazione Industriale 3 - I linguaggi di programmazione. (Prima Parte) Cesare Fantuzzi ([email protected])
CPU Organisation and Operation
CPU Organisation and Operation The Fetch-Execute Cycle The operation of the CPU 1 is usually described in terms of the Fetch-Execute cycle. 2 Fetch-Execute Cycle Fetch the Instruction Increment the Program
CELL PHONE CONTROL ROBOT CAR
CELL PHONE CONTROL ROBOT CAR Sakshi Choudhary 1, Satendra Singh 2, Vikrant 3, SK Dubey 4 1,2 UG Students of Department of ECE AIMT, Greater Noida (India) 3 Assistant Professor, Department of ECE AIMT,
Flip-Flops and Sequential Circuit Design. ECE 152A Winter 2012
Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
Flip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Winter 22 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
DESIGN OF SMS ENABLED CAR SECURITY SYSTEM
DESIGN OF SMS ENABLED CAR SECURITY SYSTEM K. A. Amusa Federal University of Agriculture, Abeokuta, O. O. Nuga Federal University of Agriculture, Abeokuta, A. A. Adetomi Federal University of Agriculture,
SafeSPI - Serial Peripheral Interface for Automotive Safety
Page 1 / 16 SafeSPI - Serial Peripheral Interface for Automotive Safety Technical SafeSPI_specification_v0.15_published.doc 30 July 2015 Page 2 / 16 1 INTRODUCTION 3 1.1 Requirement specification types
