Adding reliable data-plane acknowledgements to OpenFlow. (Project #4)

Transcription

1 Adding reliable data-plane acknwledgements t OpenFlw Peter Peresini [email protected] (Prject #4) OpenFlw visin OpenFlw hides switch diversity behind a cmmn cnfiguratin interface 1

2 OpenFlw reality Nt really unifying behavir: different capabilities (e.g., flw table size) different rule installatin speed different fidelity t the specificatin Barrier messages OpenFlw Barrier messages: enfrce rule installatin rdering infrm when a rule was installed Used by many slutins! Cnsistent Updates, etc. 2

3 Barriers - reality Despite barriers, rules are installed: up t 400 ms after barrier cnfirmatin ut f rder Barriers - fix switches are difficult t mdify users need t wait fr vendrs t apply fixes what abut lder, existing mdels? Slutin: Build a sftware layer belw the cntrller that hides incrrect switch behavir 3

4 High-level prject verview 1. develp layer fixing bad switch behavir 2. test yur slutin in a netwrk emulatr 3. evaluate & prfile perfrmance Layer fixing bad switch behavir transparent prxy between SDN cntrller and SDN switches hlds/mdifies/creates OF messages OpenFlw OpenFlw Cntrller Prxy Switch Switch Switch Switch 4

5 Prxy implementatin details speaks OpenFlw 1.0 (and 1.3?) reuse existing OF serializatin libraries investigate Flwgrammable vs OfSftSwitch r thers need t create wn prxy-sdk kit abve that write wn prxy-sdk framewrk (add timers, ptential message queues, etc.) Different prxy functins pass-thrugh (t test if things wrk) rate-limiting, keep-alive, etc. message id rewriting ensuring crrect barriers based n rule-is-in-dataplane acks rule-is-in-dataplane ack fr different types f switches delayed-drp enables dataplane ack fr drp rules 5

6 Multi-functinal prxy Idea = chain several prxies decuples functinality easily deply cmplex cmbinatins f functinality e.g. different prxy fr each switch SDN multi-functin prxy OpenFlw OpenFlw Cntrller Prxy 1 Prxy 2 OpenFlw Switch Switch Switch Switch 6

7 Chaining prxies Ptential perfrmance hg repeated serializatin-deserializatin f OF messages ne slw prxy delays whle path Chaining prxies If perfrmance is a prblem a. bypass cnnectin t next prxy which really needs it cmplex cnfiguratin :-( b. create framewrk fr creating cmplex prxies each sub-prxy running in its wn thread cnnect thrugh message queues 7

8 Prxy functins - impl. details mst f described functins semi-trivial interesting = rule-is-in-dataplane acknwledgement quite technical, especially fr sme switches Rule-is-in-dataplane ack prxy installs several new rules n the switch send peridic prbe packets using neighburing switches need t cmpute these prbes receive prbes and decide whether flw is installed in dataplane 8

9 Cmputing prbe packets highly technical! requires SAT/SMT slving reuse existing SMT slvers such as Z3 / STP reuse existing SAT slvers (e.g. MiniSat, Picsat, etc.) and write wn cnversin frm SMT t SAT start with existing Pythn implementatin expected t be the perfrmance bttleneck experiment with varius ptimizatins and alternatives Testing & evaluating Unittesting write unit-tests and micrbenchmarks re-use existing framewrks such as GgleTest r CppUnit, etc. 9

10 Testing & evaluating Integratin testing write prxy simulating bad behavir f a real hardware switch use Mininet t emulate whle netwrk run different wrklads and SDN cntrllers (details nt knwn yet) Dcumentatin & cde setup/readme guides must be easy t deply extensive in-cde dcumentatin f API expected high quality f cde clean design cde reviews wrking tests adherence t cde style 10

11 Additinal wrk research prttype is incmplete need t d a lt f things prperly Additinal wrk missing features multi-rule mdificatins/deletins, actin grup mdificatins, etc. handle switch/cntrller re-cnnect crrect XID prxying with XID expiratin, handling f all messages, etc. better OF 1.0 and 1.3 supprt lts f devilish details there! (including prbe generatin, etc.) 11

12 Expected utput We really want prject t be easily deplyable we want thers t try and use it! reliable n memry leaks, n crashes, n race cnditins Expected perfrmance We hpe that prxy will be fast >40k OF messages prxied/sec >5k generated prbes/sec 12

13 Caching prject will have PhD student as a tech lead knws all relevant details can give advice n design will ensure cde quality! hwever yu shuld be practive yu need t manage yurselves 13